Hi,
On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos
wrote:
>
> Hi again,
>
> On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
> wrote:
> >
> > Hi Rob,
> >
> > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> > [snip]
> > > > +
> > > > + ralink,sysctl:
> > > > +$ref:
Hi again,
On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
wrote:
>
> Hi Rob,
>
> On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> [snip]
> > > +
> > > + ralink,sysctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > + phandle of syscon used to
Hi Rob,
On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
[snip]
> > +
> > + ralink,sysctl:
> > +$ref: /schemas/types.yaml#/definitions/phandle
> > +description:
> > + phandle of syscon used to control system registers
> > +
> > + ralink,memctl:
> > +$ref:
Hi Rob!
On Sat, Mar 6, 2021 at 6:48 AM Rob Herring wrote:
>
> On Thu, Feb 18, 2021 at 08:07:05AM +0100, Sergio Paracuellos wrote:
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> >
On Thu, Feb 18, 2021 at 08:07:05AM +0100, Sergio Paracuellos wrote:
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++
> 1 file changed, 66 insertions(+)
>
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644
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