On Mon, Aug 19, 2019 at 11:56 AM Christoph Hellwig wrote:
>
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management.
From: Song Hui
add ls1088a gpio specify compatible.
Signed-off-by: Song Hui
---
Changes in v4:
- update the patch description.
Changes in v3:
- delete the attribute of little-endian.
Changes in v2:
- update the subject.
diff --git
hi Tglx
Agreed. Please find the dmesg output below. We see the problem on
[1456773.366951].
Let us know if you find anything suspicious.
[0.00] Linux version 4.9.0-8-amd64
(debian-ker...@lists.debian.org) (gcc version 6.3.0 20170516 (Debian
6.3.0-18+deb9u1) ) #1 SMP Debian
On 07-08-19, 15:31, Saravana Kannan wrote:
> Not all devices quantify their performance points in terms of frequency.
> Devices like interconnects quantify their performance points in terms of
> bandwidth. We need a way to represent these bandwidth levels in OPP. So,
> add support for parsing
From: Long Li
This patch set tries to fix interrupt swamp in NVMe devices.
On large systems with many CPUs, a number of CPUs may share one NVMe hardware
queue. It may have this situation where several CPUs are issuing I/Os, and
all the I/Os are returned on the CPU where the hardware queue is
From: Long Li
This function is useful for device drivers to check if this CPU has work to
do in process context.
Signed-off-by: Long Li
---
include/linux/sched.h | 1 +
kernel/sched/core.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/linux/sched.h b/include/linux/sched.h
From: Long Li
When a NVMe hardware queue is mapped to several CPU queues, it is possible
that the CPU this hardware queue is bound to is flooded by returning I/O for
other CPUs.
For example, consider the following scenario:
1. CPU 0, 1, 2 and 3 share the same hardware queue
2. the hardware
From: Long Li
The number of context switches on a CPU is useful to determine how busy this
CPU is on processing IRQs. Export this information so it can be used by device
drivers.
Signed-off-by: Long Li
---
include/linux/sched.h | 1 +
kernel/sched/core.c | 6 ++
2 files changed, 7
When transitioning to supend state, uniphier_aio_dai_suspend() is called
and asserts reset lines and disables clocks.
However, if there are two or more DAIs, uniphier_aio_dai_suspend() are
called multiple times, and double reset assersion will cause.
This patch defines the counter that has the
Hey Vinod,
There seems to be a mismatch
between the commit description
and the dt node (This is the
aoss qmp node not the APPS
shared node).
On 2019-08-19 23:11, Vinod Koul wrote:
On 14-08-19, 10:17, Stephen Boyd wrote:
Quoting Vinod Koul (2019-08-14 05:50:12)
> @@ -338,6 +339,16 @@
>
In omfs_get_imap(), 'sbi->s_imap' is allocated through kcalloc(). However,
it is not deallocated in the following execution if 'block' is not less
than 'sbi->s_num_blocks', leading to a memory leak bug. To fix this issue,
go to the 'nomem_free' label to free 'sbi->s_imap'.
Signed-off-by: Wenwen
Hello,
just noticed while reading through my linux-arm-kernel folder:
$Subject ~= s/assersion/assertion/
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König|
Industrial Linux Solutions | http://www.pengutronix.de/ |
On 2019-08-19 09:51, Nishka Dasgupta wrote:
The static structures ht16k33_fb_fix and ht16k33_fb_var, of types
fb_fix_screeninfo and fb_var_screeninfo respectively, are not used
except to be copied into other variables. Hence make both of them
constant to prevent unintended modification.
Issue
On 20-08-19, 11:50, Sibi Sankar wrote:
> Hey Vinod,
>
> There seems to be a mismatch
> between the commit description
> and the dt node (This is the
> aoss qmp node not the APPS
> shared node).
Thanks for pointing, I have squashed this and other into single patch
and updated the description
>
On 20/08/19 02:52, kernel test robot wrote:
> FYI, we noticed the following commit (built with gcc-7):
>
> commit: 323d73a8ecad22bf3284f2a7cce576ade6af ("KVM: nVMX: Change
> KVM_STATE_NESTED_EVMCS to signal vmcs12 is copied from eVMCS")
>
Hi,
On 20/08/19 13:35, kbuild test robot wrote:
> Hi Juri,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [cannot apply to v5.3-rc5 next-20190819]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve
On 19/08/19 15:57, Steven Rostedt wrote:
> On Mon, 19 Aug 2019 14:27:31 +0200
> Juri Lelli wrote:
>
> > The following BUG has been reported while running ipsec tests.
>
> Thanks!
>
> I'm still in the process of backporting patches to fix some bugs that
> showed up with the latest merge of
Add base DTS file for pm8150 along with GPIOs, power-on, rtc and vadc
nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 95
1 file changed, 95 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
diff --git
PMIC pm8150b is a slave pmic and this adds base DTS file for pm8150b
with pon, adc, and gpio nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 84 +++
1 file changed, 84 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150b.dtsi
This add base DTS file for sm8150-mtp and enables boot to console, adds
tlmm reserved range, resin node, volume down key and also includes pmic
file.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 48
PMIC pm8150l is a slave pmic and this adds base DTS file for pm8150l
with power-on, adc and gpio nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 78 +++
1 file changed, 78 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150l.dtsi
This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
the MTP for SM8150.
Changes in v2:
- Squash patches
- Fix comments given by Stephen namely, lowercase for hext numbers,
making rpmhcc have xo_board as parent, rename pon controller to
power-on controller, make pmic nodes
This add base DTS file with cpu, psci, firmware, clock, tlmm and
spmi nodes which enables boot to console
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 305 +++
1 file changed, 305 insertions(+)
create mode 100644
Add apss_shared and apps_rsc including the rpmhcc child node, pmu, SMEM
nodes
Co-developed-by: Sibi Sankar
Signed-off-by: Sibi Sankar
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 63
1 file changed, 63 insertions(+)
diff --git
Add the reserved memory regions in SM8150
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 111 +++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index
Add the regulators found in the mtp platform. This platform consists of
pmic PM8150, PM8150L and PM8009.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 327
1 file changed, 327 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
On Mon, Aug 19, 2019 at 08:59:33AM +0100, Raphael Gault wrote:
> Hi,
>
> On 8/18/19 1:37 PM, kbuild test robot wrote:
> > Hi Raphael,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on linus/master]
> > [cannot apply to v5.3-rc4 next-20190816]
> > [if
On Mon, 19 Aug 2019, Matthew Garrett wrote:
> After chatting with James in person, I'm resending the full set with the
> fixes merged in in order to avoid any bisect issues. There should be no
> functional changes other than avoiding build failures with some configs,
> and fixing the oops in
Hi,
Artem S. Tashkinov wrote:
> Once you hit a situation when opening a new tab requires more RAM than
> is currently available, the system will stall hard. You will barely be
> able to move the mouse pointer. Your disk LED will be flashing
> incessantly (I'm not entirely sure why). You will not
> Am 19.08.2019 um 21:43 schrieb Adam Ford :
>
>> Thanks to the help from the Pyra community, I was able to get a (binary)
>> reference
>> implementation using DRM that works on Pyra/OMAP5. At least the gles1test1.
>
> just a question,
>
> If DRM is working, does that mean it works without
Remove unnecessary empty return statement at the end of a void
function in the arch/x86/kernel/quirks.c.
Signed-off-by: Krzysztof Wilczynski
---
arch/x86/kernel/quirks.c | 4
1 file changed, 4 deletions(-)
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index
While your mention of quirks-table.h certainly had possibilities, I'm
afraid adding the "AU0828_DEVICE(0x05e1, 0x0400, "Hauppauge",
"Woodbury")," entry for my tuner did not make any difference regarding
the "Tuner is busy. Error -19" message.
I don't know if this means anything, but I see
Cc Mel Gorman, Kirill, Dave Hansen,
On Tue, 11 Jun 2019 at 07:51, Naoya Horiguchi wrote:
>
> On Wed, May 29, 2019 at 04:31:01PM -0700, Mike Kravetz wrote:
> > On 5/28/19 2:49 AM, Wanpeng Li wrote:
> > > Cc Paolo,
> > > Hi all,
> > > On Wed, 14 Feb 2018 at 06:34, Mike Kravetz
> > > wrote:
> > >>
On Mon, 19 Aug 2019 22:40:07 +0200,
Paweł Rekowski wrote:
>
> This patch adds a new PCI subsys ID for the SBZ, as found and tested by
> me and some reddit users.
>
> Signed-off-by: Paweł Rekowski
Thanks, applied with Cc to stable.
Takashi
On 2019-08-20 00:16:40, Wenwen Wang wrote:
> In parse_tag_1_packet(), if tag 1 packet contains a key larger than
> ECRYPTFS_MAX_ENCRYPTED_KEY_BYTES, no cleanup is executed, leading to a
> memory leak on the allocated 'auth_tok_list_item'. To fix this issue, go to
> the label 'out_free' to perform
Hi all,
Changes since 20190819:
The drm-misc tree gained a conflict against the drm-intel tree.
The security tree lost its build failure.
Non-merge commits (relative to Linus' tree): 6824
7412 files changed, 368368 insertions(+), 221059 deletions(-)
On 2019-08-20 00:33:54, Wenwen Wang wrote:
> In ecryptfs_init_messaging(), if the allocation for 'ecryptfs_msg_ctx_arr'
> fails, the previously allocated 'ecryptfs_daemon_hash' is not deallocated,
> leading to a memory leak bug. To fix this issue, free
> 'ecryptfs_daemon_hash' before returning the
On Mon, Aug 19, 2019 at 5:07 PM Andy Shevchenko
wrote:
> The proper fix is to revert the culprit since we call
> acpi_gpiochip_request_interrupts() for all controllers.
> Linus, please re-do the approach with IRQ handling,
Exactly what do you refer to when you want me to
"re-do the approach for
Hi,
On Mon, Aug 19, 2019 at 10:23:03PM -0500, Samuel Holland wrote:
> On sun8i, sun9i, and sun50i SoCs, system suspend/resume support requires
> firmware running on the AR100 coprocessor (the "SCP"). Such firmware can
> provide additional features, such as thermal monitoring and poweron/off
>
Hi,
On Mon, Aug 19, 2019 at 10:23:04PM -0500, Samuel Holland wrote:
> This mailbox hardware is present in Allwinner sun8i, sun9i, and sun50i
> SoCs. Add a device tree binding for it.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Samuel Holland
> ---
> .../mailbox/allwinner,sunxi-msgbox.yaml
On Aug 19 2019, "h...@infradead.org" wrote:
> This looks a little odd to m and assumes we never pass a size smaller
> than PAGE_SIZE. Whule that is probably true, why not something like:
>
> if (size < PAGE_SIZE && size != -1)
ITYM size <= PAGE_SIZE. And since size is unsigned it cannot
Kindly reminder, :)
On Mon, 15 Jul 2019 at 17:16, Paolo Bonzini wrote:
>
> On 15/07/19 03:28, Wanpeng Li wrote:
> > From: Wanpeng Li
> >
> > Allow guest reads CORE cstate when exposing host CPU power management
> > capabilities
> > to the guest. PKG cstate is restricted to avoid a guest to get
On Tue, Aug 20, 2019 at 09:14:58AM +0200, Andreas Schwab wrote:
> On Aug 19 2019, "h...@infradead.org" wrote:
>
> > This looks a little odd to m and assumes we never pass a size smaller
> > than PAGE_SIZE. Whule that is probably true, why not something like:
> >
> > if (size < PAGE_SIZE &&
> > > +#define VFIO_IRQ_TYPE_GFX(1)
> > > +/*
> > > + * vGPU vendor sub-type
> > > + * vGPU device display related interrupts e.g. vblank/pageflip */
> > > +#define VFIO_IRQ_SUBTYPE_GFX_DISPLAY_IRQ (1)
> >
> > If this is a GFX/DISPLAY IRQ, why are we
On Sun, Aug 18, 2019 at 09:58:16AM -0700, Deepa Dinamani wrote:
> Leaving granularity at 1ns because it is dependent on the specific
> attached backing pstore module. ramoops has microsecond resolution.
>
> Fix the readback of ramoops fractional timestamp microseconds,
> which has incorrectly
Back in 2004 we added logic to arch/ppc64/Makefile to pass
the --synthetic option to nm, if it was supported by nm.
Then in 2005 when arch/ppc64 and arch/ppc were merged, the logic to
add --synthetic was moved inside an #ifdef CONFIG_PPC64 block within
arch/powerpc/Makefile, and has remained
Will Deacon writes:
> Hi Michael,
>
> On Fri, Aug 16, 2019 at 02:52:40PM +1000, Michael Ellerman wrote:
>> Will Deacon writes:
>> > Although Alpha, Itanic and PowerPC all override NM, only PowerPC does it
>> > conditionally so I agree with you that passing '--synthetic'
>> > unconditionally
>>
From: Hou Zhiqiang
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected
SerDes protocol. The current num-lanes indicates the max lanes
PCIe controller can support up to, instead of the lanes assigned
to the PCIe controller. This
On Mon, Aug 19, 2019 at 05:59:48PM +0100, Mark Rutland wrote:
> Hi,
>
> I found that when I enable both KCOV and UBSAN on arm64, clang fails to
> emit any __sanitizer_cov_trace_*() calls in the resulting binary,
> rendering KCOV useless.
>
> For example, when building v5.3-rc3's
From: Hou Zhiqiang
Remove the num-lanes to avoid the driver setting the link width.
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected SerDes
protocol in the RCW (Reset Configuration Word), and the PCIe link
training is
From: Hou Zhiqiang
The num-lanes is optional, so probably it isn't added
on some platforms. The subsequent programming is base
on the num-lanes, hence return when it is not found.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Andrew Murray
---
V2:
- No change.
From: Hou Zhiqiang
The num-lanes is not a mandatory property, e.g. on FSL
Layerscape SoCs, the PCIe link training is completed
automatically base on the selected SerDes protocol, it
doesn't need the num-lanes to set-up the link width.
It is previously in both Required and Optional properties,
From: Hou Zhiqiang
Remove the num-lanes to avoid the driver setting the link width.
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected SerDes
protocol in the RCW (Reset Configuration Word), and the PCIe link
training is
Hi,
On Tue, Jul 30, 2019 at 05:43:37AM -0600, Naga Sureshkumar Relli wrote:
> Add driver for arm pl353 static memory controller nand interface.
> This controller is used in Xilinx Zynq SoC for interfacing the
> NAND flash memory.
Is there a reason that you dropped me from the Cc list? If you Cc
Hi,
On 20/08/2019 08:48, H. Nikolaus Schaller wrote:
>
>> Am 19.08.2019 um 21:43 schrieb Adam Ford :
>>
>>> Thanks to the help from the Pyra community, I was able to get a (binary)
>>> reference
>>> implementation using DRM that works on Pyra/OMAP5. At least the gles1test1.
>>
>> just a
Hi Ted,
Thanks for raising this question.
For UEFI based system, they have a config table that carries rng seed
and can be passed to device randomness. However, they also use
add_device_randomness (not sure if it's the same reason that they
can't guarantee _all_ bootloader can be trusted)
This
On Aug 19 2019, Atish Patra wrote:
> @@ -42,20 +43,44 @@ static inline void flush_tlb_range(struct vm_area_struct
> *vma,
>
> #include
>
> -static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long
> start,
> - unsigned long size)
>
Hi Geert,
sorry for the delayed response..
On Mon, Aug 19, 2019 at 03:45:54PM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Mon, Jul 8, 2019 at 9:58 AM Geert Uytterhoeven
> wrote:
> > On Sat, Jul 6, 2019 at 4:07 PM Jacopo Mondi
> > wrote:
> > > Add device tree bindings documentation
pti_clone_pgtable() increases addr by PUD_SIZE for pud_none(*pud) case.
This is not accurate because addr may not be PUD_SIZE aligned.
In our x86_64 kernel, pti_clone_pgtable() fails to clone 7 PMDs because
of this issuse, including PMD for the irq entry table. For a memcache
like workload, this
> > How is this feature supposed to work for external modules?
> >
> > klp-convert receives:
> > "symbols from vmlinux" + "symbols from no-klp in-tree modules"
> > + "symbols from no-klp external modules" ??
> >
>
> I don't think that this use-case has been previously thought out (Miroslav,
>
In nfs4_try_migration(), if nfs4_begin_drain_session() fails, the
previously allocated 'page' and 'locations' are not deallocated, leading to
memory leaks. To fix this issue, free 'page' and 'locations' before
returning the error.
Signed-off-by: Wenwen Wang
---
fs/nfs/nfs4state.c | 6 +-
1
Now that we have the DT validation in place, let's convert the device tree
bindings for the Synopsys DWMAC Glue for Amlogic SoCs over to a YAML schemas.
Reviewed-by: Rob Herring
Reviewed-by: Martin Blumenstingl
Signed-off-by: Neil Armstrong
---
.../bindings/net/amlogic,meson-dwmac.yaml |
This patchsets converts the Amlogic Meson DWMAC glue bindings over to
YAML schemas using the already converted dwmac bindings.
The first patch is needed because the Amlogic glue needs a supplementary
reg cell to access the DWMAC glue registers.
Changes since v3:
- Specified net-next target tree
The Amlogic Meson DWMAC glue bindings needs a second reg cells for the
glue registers, thus update the reg minItems/maxItems to allow more
than a single reg cell.
Also update the allwinner,sun7i-a20-gmac.yaml derivative schema to specify
maxItems to 1.
Signed-off-by: Neil Armstrong
Acked-by:
On Sun, 2019-08-18 at 11:16 -0700, h...@infradead.org wrote:
> On Fri, Aug 16, 2019 at 07:21:52PM +, Atish Patra wrote:
> > > > + if (isa[0] != '\0') {
> > > > + /* Add remainging isa strings */
> > > > + for (e = isa; *e != '\0'; ++e) {
> > > > +#if
On Mon, Aug 19, 2019 at 3:29 PM Wei Xu wrote:
> Invoke acpi_gpiochip_request_interrupts after the acpi data has been
> attached to the pl061 acpi node to register interruption.
>
> Otherwise it will be failed to register interruption for the ACPI case.
> Because in the
Hi Sakari, Hans,
st-mipid02 changes are already merged, thanks Sakari and sorry for
disturbance.
Still remain the V4L2_CID_LINK_FREQ for OV5640.
On 8/19/19 11:13 AM, Hugues FRUCHET wrote:
> Hi Hans, Sakari,
>
> OK to push separately the 80 char fix.
>
> There was pending related changes on
During a memcpy from a pmem device, if a machine check exception is
generated we end up in a panic. In case of fsdax read, this should
only result in a -EIO. Avoid MCE by implementing memcpy_mcsafe.
Before this patch series:
```
bash-4.4# mount -o dax /dev/pmem0 /mnt/pmem/
[ 7621.714094]
From: Balbir Singh
The current code would fail on huge pages addresses, since the shift would
be incorrect. Use the correct page shift value returned by
__find_linux_pte() to get the correct physical address. The code is more
generic and can handle both regular and compound pages.
Fixes:
From: Reza Arbab
The function doesn't get used outside this file, so make it static.
Signed-off-by: Reza Arbab
Signed-off-by: Santosh Sivaraj
Reviewed-by: Nicholas Piggin
---
arch/powerpc/kernel/mce.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Certain architecture specific operating modes (e.g., in powerpc machine
check handler that is unable to access vmalloc memory), the
search_exception_tables cannot be called because it also searches the
module exception tables if entry is not found in the kernel exception
table.
Cc: Thomas
schedule_work() cannot be called from MCE exception context as MCE can
interrupt even in interrupt disabled context.
fixes: 733e4a4c ("powerpc/mce: hookup memory_failure for UE errors")
Reviewed-by: Mahesh Salgaonkar
Reviewed-by: Nicholas Piggin
Acked-by: Balbir Singh
Signed-off-by: Santosh
From: Balbir Singh
If we take a UE on one of the instructions with a fixup entry, set nip
to continue execution at the fixup entry. Stop processing the event
further or print it.
Co-developed-by: Reza Arbab
Signed-off-by: Reza Arbab
Signed-off-by: Balbir Singh
Reviewed-by: Mahesh Salgaonkar
From: Balbir Singh
The pmem infrastructure uses memcpy_mcsafe in the pmem layer so as to
convert machine check exceptions into a return value on failure in case
a machine check exception is encountered during the memcpy. The return
value is the number of bytes remaining to be copied.
This patch
Use memcpy_mcsafe() implementation to define copy_to_user_mcsafe()
Signed-off-by: Santosh Sivaraj
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/uaccess.h | 14 ++
2 files changed, 15 insertions(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
On Mon, Aug 19, 2019 at 08:26:18PM +0200, Maxime Ripard wrote:
> From: Maxime Ripard
>
> The RC controllers have a bunch of generic properties that are needed in a
> device tree. Add a YAML schemas for those.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Maxime Ripard
For the series (both
Hi,
On Mon, Aug 19, 2019 at 10:23:06PM -0500, Samuel Holland wrote:
> The A80 SoC contains a message box that can be used to send messages and
> interrupts back and forth between the ARM application CPUs and the ARISC
> coprocessor. Add a device tree node for it.
>
> Signed-off-by: Samuel Holland
On Thu 2019-08-08 00:32:26, John Ogness wrote:
> --- /dev/null
> +++ b/kernel/printk/numlist.c
> +/**
> + * numlist_pop() - Remove the oldest node from the list.
> + *
> + * @nl: The numbered list from which to remove the tail node.
> + *
> + * The tail node can only be removed if two conditions
On Mon 19-08-19 12:30:18, John Hubbard wrote:
> On 8/19/19 12:06 PM, Bharath Vedartham wrote:
> > On Mon, Aug 19, 2019 at 07:56:11AM -0500, Dimitri Sivanich wrote:
> > > Reviewed-by: Dimitri Sivanich
> > Thanks!
> >
> > John, would you like to take this patch into your miscellaneous
> >
On Thu 2019-08-08 00:32:26, John Ogness wrote:
> --- /dev/null
> +++ b/kernel/printk/ringbuffer.c
> +/**
> + * assign_desc() - Assign a descriptor to the caller.
> + *
> + * @e: The entry structure to store the assigned descriptor to.
> + *
> + * Find an available descriptor to assign to the
On Tue, Aug 20, 2019 at 2:14 PM wrote:
>
> From: Long Li
>
> This patch set tries to fix interrupt swamp in NVMe devices.
>
> On large systems with many CPUs, a number of CPUs may share one NVMe hardware
> queue. It may have this situation where several CPUs are issuing I/Os, and
> all the I/Os
On Mon, Aug 19, 2019 at 2:21 AM Christoph Hellwig wrote:
>
> On Sun, Aug 18, 2019 at 10:20:18AM +0800, Guo Ren wrote:
> > > > Also change flag VM_ALLOC to VM_IOREMAP in get_vm_area_caller.
> > >
> > > Looks generally fine, but two comments:
> > >
> > > - do you have a need for ioremap_cache? We
Hi,
On Mon, Aug 19, 2019 at 10:23:05PM -0500, Samuel Holland wrote:
> Allwinner sun8i, sun9i, and sun50i SoCs contain a hardware message box
> used for communication between the ARM CPUs and the ARISC management
> coprocessor. The hardware contains 8 unidirectional 4-message FIFOs.
>
> Add a
On 2019-08-19 14:27:31 [+0200], Juri Lelli wrote:
> This v2 applies to v4.19.59-rt24.
Looks good, I suggest to apply this to v4.19 and earlier.
For v5.2 and later (including upstream) please send a patch to simply
replace get_cpu() with smp_processor_id(). The reason is that get_cpu()
will not
On Thu, Aug 01, 2019 at 05:25:41PM +0200, Stefano Garzarella wrote:
> +/* Wait for the remote to close the connection */
> +void vsock_wait_remote_close(int fd)
> +{
> + struct epoll_event ev;
> + int epollfd, nfds;
> +
> + epollfd = epoll_create1(0);
> + if (epollfd == -1) {
> +
There is a new product which reuses Lantiq serial controller IP. Patch 1 in this
series converts existing lantiq dt bindings to YAML schema and Patch 2 updates
it to support newer product.
These patches are baselined upon Linux 5.3-rc4 at below Git tree:
Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar
---
.../devicetree/bindings/serial/lantiq_asc.yaml | 17 +
1 file changed, 17 insertions(+)
diff --git
On 18/08/2019 09:21, Chris Clayton wrote:
>
>
> On 17/08/2019 08:19, Chris Clayton wrote:
>> Hi.
>>
>> I just found the following error in the output from dmesg.
>>
>> [ 4023.460058] iwlwifi :02:00.0: Microcode SW error detected. Restarting
>> 0x0.
>
> Since reporting, I've found that
Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.
Signed-off-by: Rahul Tanwar
---
.../devicetree/bindings/serial/lantiq_asc.txt | 31 --
.../devicetree/bindings/serial/lantiq_asc.yaml | 70 ++
2
On Tue, Aug 20, 2019 at 10:12 AM Linus Walleij wrote:
>
> On Mon, Aug 19, 2019 at 5:07 PM Andy Shevchenko
> wrote:
>
> > The proper fix is to revert the culprit since we call
> > acpi_gpiochip_request_interrupts() for all controllers.
> > Linus, please re-do the approach with IRQ handling,
>
>
Üdvözlöm!
Ahogyan az üzleti gyakorlat mutatja, a nem anyagi juttatások sajnos nem a
leghatékonyabb módjai annak, hogy növeljük az alkalmazottak motivációját vagy a
munka iránti elköteleződésüket!
Az alkalmazottakkal szemben tanúsított lojalitás jelenleg a legnagyobb kihívás
a vállalkozások
On Thu, Aug 01, 2019 at 05:25:40PM +0200, Stefano Garzarella wrote:
> When VMCI transport is used, if the guest closes a connection,
> all data is gone and EOF is returned, so we should skip the read
> of data written by the peer before closing the connection.
All transports should aim for
On Fri, Aug 16, 2019 at 10:13:43AM +0800, Jin Yao wrote:
SNIP
> static void
> hpp__entry_unpair(struct hist_entry *he, int idx, char *buf, size_t size)
> {
> @@ -1662,6 +1794,10 @@ static void data__hpp_register(struct data__file *d,
> int idx)
> fmt->color = hpp__color_cycles;
Add documentation for the mt8183 gce.
Add gce header file defined the gce hardware event,
subsys number and constant for mt8183.
Signed-off-by: Bibby Hsieh
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 6 +-
include/dt-bindings/gce/mt8183-gce.h | 175
GCE hardware stored event information in own internal sysram,
if the initial value in those sysram is not zero value
it will cause a situation that gce can wait the event immediately
after client ask gce to wait event but not really trigger the
corresponding hardware.
In order to make sure that
The order of gce instructions is [subsys offset value]
so reorder the parameter of cmdq_pkt_write_mask
and cmdq_pkt_write function.
Signed-off-by: Bibby Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 6 +++---
include/linux/soc/mediatek/mtk-cmdq.h | 10 +-
2
Define an instruction structure for gce driver to append command.
This structure can make the client's code more readability.
Signed-off-by: Bibby Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 106 +++
include/linux/mailbox/mtk-cmdq-mailbox.h | 2
"thread-num" is an unused property so we remove it from example.
Signed-off-by: Bibby Hsieh
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
add gce device node for mt8183
Signed-off-by: Bibby Hsieh
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 08274bfcebd8..a81c995bbea9 100644
---
The interrupt mask and thread number has positive correlation,
so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate
it by thread number.
Signed-off-by: Bibby Hsieh
Reviewed-by: CK Hu
---
drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++-
1 file changed, 7 insertions(+), 5
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