Hi
Am 24.11.20 um 17:27 schrieb David Laight:
From: David Laight
Sent: 20 November 2020 15:39
From: Thomas Zimmermann
Sent: 20 November 2020 13:42
...
I did a diff from v5.10-rc4 to drm-tip to look for suspicious changes.
Some candidates are
8e3784dfef8a ("drm/ast: Reload gamma LUT
On Wed, Nov 25, 2020 at 09:46:06AM +0200, Heikki Krogerus wrote:
> On Tue, Nov 24, 2020 at 12:32:35PM -0800, Prashant Malani wrote:
> > Hi,
> >
> > On Tue, Nov 24, 2020 at 12:10:31PM -0800, Prashant Malani wrote:
> > > Both partner and cable have identity VDOs. These are listed separately
> > >
This is one of sub-device driver for Advantech embedded controller
AHC1EC0. This driver provide watchdog functionality for Advantech
related applications to restart the system.
Signed-off-by: Shihlun Lin
---
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile | 1 +
AHC1EC0 is the embedded controller driver for Advantech industrial
products. This provides sub-devices such as hwmon and watchdog, and also
expose functions for sub-devices to read/write the value to embedded
controller.
Signed-off-by: Shihlun Lin
---
drivers/mfd/Kconfig | 10 +
Add DT binding schema for Advantech embedded controller AHC1EC0.
Signed-off-by: Shihlun Lin
---
.../devicetree/bindings/mfd/ahc1ec0.yaml | 70 +++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/ahc1ec0.yaml
diff --git
Add Advantech embedded controller entry
Signed-off-by: Shihlun Lin
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 94ac10a153c7..c1fe5233b469 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -562,6 +562,17 @@ S: Maintained
F:
I see that problem only on systems that use a R1305G APU
sudo cat /sys/kernel/debug/dri/0/amdgpu_firmware_info
shows
VCE feature version: 0, firmware version: 0x
UVD feature version: 0, firmware version: 0x
MC feature version: 0, firmware version: 0x
ME feature version:
allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a004-20201124
i386 randconfig-a003-20201124
i386 randconfig-a002-20201124
i386 randconfig
On Tue, Nov 24, 2020 at 12:32:35PM -0800, Prashant Malani wrote:
> Hi,
>
> On Tue, Nov 24, 2020 at 12:10:31PM -0800, Prashant Malani wrote:
> > Both partner and cable have identity VDOs. These are listed separately
> > in the Documentation/ABI/testing/sysfs-class-typec. Factor these out
> > into
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20201124
x86_64 randconfig-a003-20201124
x86_64 randconfig-a004-20201124
x86_64 randconfig-a005-20201124
x86_64
Gentle ping;
On Fri, Nov 06, 2020 at 11:26:59AM +0900, AKASHI Takahiro wrote:
> This is an interim snapshot of our next version, v4, for enabling
> UHS-II on MMC/SD.
>
> It is focused on 'sdhci' side to address Adrian's comments regarding
> "modularising" sdhci-uhs2.c.
> The whole aim of this
devm_ioremap_resource() will be not built in lib/devres.c if
CONFIG_HAS_IOMEM is not set, of_address_to_resource() will be
not built in drivers/of/address.c if CONFIG_OF_ADDRESS is not
set, and then there exists two build errors about undefined
reference to "devm_ioremap_resource" and
On Wed, 25 Nov 2020 at 04:08, Bongsu Jeon wrote:
>
> On 11/24/20, k...@kernel.org wrote:
> > On Tue, Nov 24, 2020 at 08:39:40PM +0900, Bongsu Jeon wrote:
> >> On Mon, Nov 23, 2020 at 5:02 PM k...@kernel.org wrote:
> >> >
> >> > On Mon, Nov 23, 2020 at 04:55:26PM +0900, Bongsu Jeon wrote:
> > >
On Tue, Nov 24, 2020 at 12:19:34AM -0800, Stephane Eranian wrote:
> Hi,
>
> Another remark on the PEBS drainage code, it seems to me like a test
> is not quite correct:
> intel_pmu_drain_pebs_nhm()
> {
> ...
>if (p->status != (1ULL << bit)) {
>
sparse is unhappy with us casting the __iomem address space pointer to
a type with no address space attribute specified:
"sparse warnings: (new ones prefixed by >>)"
>> drivers/mtd/maps/physmap-bt1-rom.c:78:18: sparse: sparse: cast removes
>> address space '__iomem' of expression
Indeed we
On Wed, 25 Nov 2020 at 01:44, Adam Ford wrote:
>
> On Mon, Nov 23, 2020 at 8:04 PM Alice Guo wrote:
> >
> > Directly reading ocotp register depends on that bootloader enables ocotp
> > clk, which is not always effective, so change to use nvmem API. Using
> > nvmem API requires to support driver
Hi Bingbu,
On Wed, Nov 25, 2020 at 1:15 PM Bingbu Cao wrote:
>
>
>
> On 11/24/20 6:20 PM, Robert Foss wrote:
> > On Tue, 24 Nov 2020 at 10:42, Bingbu Cao wrote:
> >>
> >> Hi, Robert
> >>
> >> I remember that the full size of ov8856 image sensor is 3296x2480 and we
> >> can get the 3280x2464
>
On 24/11/2020 23:19, Thomas Gleixner wrote:
> On Tue, Nov 24 2020 at 21:03, Laurent Vivier wrote:
>> This parameter is needed to pass it to irq_domain_alloc_descs().
>>
>> This seems to have been missed by
>> o06ee6d571f0e ("genirq: Add affinity hint to irq allocation")
>
> No, this has not been
NIAP PP_OS certification requests that the OS shall validate the
CodeSigning extended key usage extension field for integrity
verifiction of exectable code:
https://www.niap-ccevs.org/MMO/PP/-442-/
FIA_X509_EXT.1.1
This patchset adds the logic for parsing the codeSigning EKU
Add an openssl command option example for generating CodeSign extended
key usage in X.509 when CONFIG_CHECK_CODESIGN_EKU be enabled.
Signed-off-by: "Lee, Chun-Yi"
---
Documentation/admin-guide/module-signing.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git
Add codeSigning EKU to the X.509 key generation config for the build time
autogenerated kernel key.
Signed-off-by: "Lee, Chun-Yi"
---
certs/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/certs/Makefile b/certs/Makefile
index f4c25b67aad9..1ef4d6ca43b7 100644
--- a/certs/Makefile
This patch adds the logic for checking the CodeSigning extended
key usage when verifying signature of kernel module or
kexec PE binary in PKCS#7.
Signed-off-by: "Lee, Chun-Yi"
---
certs/system_keyring.c | 2 +-
crypto/asymmetric_keys/Kconfig | 9 +
This patch adds the logic for parsing the CodeSign extended key usage
extension in X.509. The parsing result will be set to the eku flag
which is carried by public key. It can be used in the PKCS#7
verification.
Signed-off-by: "Lee, Chun-Yi"
---
crypto/asymmetric_keys/x509_cert_parser.c | 24
After commit 8a94644b440e ("PCI: Fix pci_create_slot() reference count
leak"), kobject_put() is called instead of kfree() if
kobject_init_and_add() fails. However, we still need to free the slot
memory before overwriting it as ERR_PTR(err).
This partially reverts the commit 8a94644b440e.
Fixes:
On Tue, Nov 24, 2020 at 5:10 PM Peter Zijlstra wrote:
>
> On Tue, Nov 24, 2020 at 02:01:39PM +0900, Namhyung Kim wrote:
>
> > Yes, it's not about __intel_pmu_pebs_event(). I'm looking at
> > intel_pmu_drain_pebs_nhm() specifically. There's code like
> >
> > /* log dropped samples number
Allow Luton and Jaguar2 SoCs to use reset feature by adding the reset
node.
Signed-off-by: Gregory CLEMENT
---
arch/mips/boot/dts/mscc/jaguar2.dtsi | 5 +
arch/mips/boot/dts/mscc/luton.dtsi | 5 +
2 files changed, 10 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi
Hello,
This series extends reset support for 2 other MIPS based SoCs: Luton
and Jaguar 2.
Patches 1 and 2 should be merged through the reset subsystem, while
the device tree changes in patches 3 should go through the mips
subsystem.
In this second series I removed the
This adds the support for 2 others MIPS based VCore III SoCs: Luton
and Jaguar2.
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
This adds reset support for Luton and Jaguar2 in the ocelot-reset
driver. They are both MIPS based belonging to the Vcore III family.
Acked-by: Alexandre Belloni
Signed-off-by: Gregory CLEMENT
---
drivers/power/reset/ocelot-reset.c | 30 +++---
1 file changed, 27
On Mon, Nov 23, 2020 at 11:00:35AM +0200, Laurentiu Tudor wrote:
> From: Ionut-robert Aron
>
> Convert fsl,qoriq-mc to YAML in order to automate the verification
> process of dts files. In addition, update MAINTAINERS accordingly
> and, while at it, add some missing files.
>
> Signed-off-by:
This is one of sub-device driver for Advantech embedded controller
AHC1EC0. This driver provides sysfs ABI for Advantech related
applications to monitor the system status.
Signed-off-by: Shihlun Lin
---
drivers/hwmon/Kconfig |8 +
drivers/hwmon/Makefile|1 +
On Tue, Nov 24, 2020 at 08:24:15PM -0800, Joe Perches wrote:
> On Wed, 2020-11-25 at 12:08 +0800, Tiezhu Yang wrote:
> > On 11/25/2020 11:51 AM, Joe Perches wrote:
> > > On Wed, 2020-11-25 at 11:35 +0800, Tiezhu Yang wrote:
> > > > When backport the upstream commit to the internal LTS kernel
Ok, I think I can make a patch to keep them at "include/crypto" .
-邮件原件-
发件人: Stephan Mueller [mailto:smuel...@chronox.de]
发送时间: 2020年11月19日 4:25
收件人: yumeng (J) ; herb...@gondor.apana.org.au;
da...@davemloft.net
抄送: linux-cry...@vger.kernel.org; Xu Zaibo ; Wangzhou (B)
;
Permit the user to specify the erase page size as a parameter.
This solves two problems:
- phram can access images made by mkfs.jffs2. mkfs.jffs2 won't
create images with erase sizes less than 8KiB; many architectures
define PAGE_SIZE as 4KiB.
- Allows more effective use of small capacity
Use SPRN_SPRG_SCRATCH2 as an alternative scratch register in
the early part of DSI prolog in order to avoid clobbering
SPRN_SPRG_SCRATCH0/1 used by other prologs.
The 603 doesn't like a jump from DataLoadTLBMiss to the 10 nops
that are now in the beginning of DSI exception as a result of
the
Use SPRN_SPRG_SCRATCH2 as a third scratch register in
exception prologs in order to simplify them and avoid
data going back and forth from/to CR.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h | 22 +++---
1 file changed, 7 insertions(+), 15 deletions(-)
diff
An FTR_SECTION_ELSE is in the middle of
BEGIN_MMU_FTR_SECTION/ALT_MMU_FTR_SECTION_END_IFSET
Change it to MMU_FTR_SECTION_ELSE
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_book3s_32.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On the 603, SDR1 is not used.
In order to free SPRN_SPRG2, use SPRN_SDR1 to store the pgdir
phys addr.
But only some bits of SDR1 can be used (0x01ff).
As the pgdir is 4k aligned, rotate it by 4 bits to the left.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h |
Make code more readable with a clear CONFIG_VMAP_STACK
section and a clear non CONFIG_VMAP_STACK section.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.h
SPRN_SPRG_PGDIR is there mainly to speedup SW TLB miss handlers
for powerpc 603.
We need to free SPRN_SPRG2 to reduce the mess with CONFIG_VMAP_STACK.
In hash_page(), reading PGDIR from thread_struct will be in the noise
performance wise.
Signed-off-by: Christophe Leroy
---
Since commit 2b279c0348af ("powerpc/32s: Allow mapping with BATs with
DEBUG_PAGEALLOC"), there is no real situation where mapping without
BATs is required.
In order to simplify memory handling, always map kernel text
and rodata with BATs even when "nobats" kernel parameter is set.
Also fix the
We now always map kernel text with BATs. Neither need to preload
hash with kernel text addresses nor ensure they are never evicted.
This is more or less a revert of commit ee4f2ea48674 ("[POWERPC] Fix
32-bit mm operations when not using BATs")
Signed-off-by: Christophe Leroy
---
Hi Jiaxun,
It's my fault, I didn't know to send mail to the mailing list.
We will discuss your suggestions and correct the errors in the code.
I will send a new patch to the mailing list.
Thanks.
-Lizhi
On 11/23/2020 06:31 PM, Jiaxun Yang wrote:
Hi Lizhi,
You didn't send the patch to any
This files defines the sud-device types and hwmon profiles support by
Advantech embedded controller.
Signed-off-by: Shihlun Lin
---
include/dt-bindings/mfd/ahc1ec0.h | 25 +
1 file changed, 25 insertions(+)
create mode 100644 include/dt-bindings/mfd/ahc1ec0.h
diff
On Tue, Nov 24, 2020 at 09:58:45PM +0100, Thorsten Scherer wrote:
> Hello,
>
> On Tue, Nov 24, 2020 at 03:18:34PM +0100, Uwe Kleine-König wrote:
> > The driver core ignores the return value of the remove callback, so
> > don't give siox drivers the chance to provide a value.
> >
> > All siox
On Tue, 2020-11-24 at 13:32 -0800, Kees Cook wrote:
> On Mon, Nov 23, 2020 at 08:31:30AM -0800, James Bottomley wrote:
> > Really, no ... something which produces no improvement has no value
> > at all ... we really shouldn't be wasting maintainer time with it
> > because it has a cost to merge.
From: Jordan Crouse
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if an MMU-500 is attached and modify the programming sequence
accordingly.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 15 +--
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire
Add support for domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
to get/set pagetable configuration data which initially will
be used to set quirks and later can be extended to include
other pagetable configuration data.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c |
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
On Tue, Nov 24, 2020 at 01:12:00PM +0200, laurentiu.tu...@nxp.com wrote:
> From: Laurentiu Tudor
>
> 'type' and 'flags' fields were missing from dprc_rsp_get_obj_region
> structure therefore the MC Bus driver was not receiving proper flags
> from MC like DPRC_REGION_CACHEABLE.
>
>
Add a new iommu domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
for pagetable configuration which initially will be used to
set quirks like for system cache aka last level cache to be
used by client drivers like GPU to set right attributes for
caching the hardware pagetables into the system cache and
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai
On 2020-11-25 03:11, Will Deacon wrote:
On Mon, Nov 23, 2020 at 10:35:55PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
Hi Lukas,
On Tue, Nov 24, 2020 at 06:19:57PM +0100, Lukas F. Hartmann wrote:
> The sn56dsi86 DSI to eDP bridge driver does not support attaching
> without a drm connector.
I think the SN65DSI86 driver is exactly what you should focus on, so
that it works when connector is optional. The
> >>>
> >>> The device side of USBSS DRD controller is compliant with XHCI.
> >>> The architecture for device side is almost the same as for host
> >>> side, and most of the XHCI specification can be used to understand
> >>> how this controller operates.
> >>>
> >>> This controller and driver
Thanks for magnus very much.
V2:
#2 patch made some changes following magnus' opinions.
Xuan Zhuo (2):
xsk: replace datagram_poll by sock_poll_wait
xsk: change the tx writeable condition
net/xdp/xsk.c | 20
net/xdp/xsk_queue.h | 6 ++
2 files changed, 22
Modify the tx writeable condition from the queue is not full to the
number of present tx queues is less than the half of the total number
of queues. Because the tx queue not full is a very short time, this will
cause a large number of EPOLLOUT events, and cause a large number of
process wake up.
datagram_poll will judge the current socket status (EPOLLIN, EPOLLOUT)
based on the traditional socket information (eg: sk_wmem_alloc), but
this does not apply to xsk. So this patch uses sock_poll_wait instead of
datagram_poll, and the mask is calculated by xsk_poll.
Signed-off-by: Xuan Zhuo
---
On Wed, Nov 18, 2020 at 09:37:56AM -0400, Jason Gunthorpe wrote:
> On Wed, Nov 18, 2020 at 03:10:21AM -0800, syzbot wrote:
>
> > HEAD commit:20529233 Add linux-next specific files for 20201118
> > git tree: linux-next
> > console output:
Fix to return the error code -EREMOTEIO from pdr_register_listener
rather than 0.
Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/soc/qcom/pdr_interface.c | 1 +
1 file changed, 1 insertion(+)
diff
Fix to return the error code -EINVAL in sdw_compute_port_params
instead of 0.
Fixes: 9026118f20e2 ("soundwire: Add generic bandwidth allocation algorithm")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/soundwire/generic_bandwidth_allocation.c | 4 +++-
1 file changed, 3
Fix to return the error code -ENODEV when fails to init wmi and
smm.
Fixes: 41e36f2f85af ("platform/x86: dell-smbios: Link all dell-smbios-* modules
together")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/platform/x86/dell-smbios-base.c | 1 +
1 file changed, 1
platform_device_put is missing when it fails to set fdev->id. Set
a temp value to do sanity check.
Fixes: 543be3d8c999 ("fpga: add device feature list support")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/fpga/dfl.c | 9 ++---
1 file changed, 6 insertions(+), 3
krealloc() may fail to expand the memory space. Add sanity checks to it,
and WARN() if that really happened.
Fixes: 771915c4f688 ("xfs: remove kmem_realloc()")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
fs/xfs/xfs_mount.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Fix to return the error code -EINVAL when size == 0 after
asd_find_flash_de instead of zero.
Fixes: 2908d778ab3e ("[SCSI] aic94xx: new driver")
Reported-by: Hulk Robot
Signed-off-by: Qinglang Miao
---
drivers/scsi/aic94xx/aic94xx_sds.c | 8 ++--
1 file changed, 6 insertions(+), 2
> Am 25.11.2020 um 06:34 schrieb Andrea Arcangeli :
>
> Hello,
>
>> On Mon, Nov 23, 2020 at 02:01:16PM +0100, Vlastimil Babka wrote:
>>> On 11/21/20 8:45 PM, Andrea Arcangeli wrote:
>>> A corollary issue was fixed in
>>> 39639000-39814fff : Unknown E820 type
>>>
>>> pfn 0x7a200 -> 0x7a20
Hi all,
Today's linux-next merge of the seccomp tree got a conflict in:
arch/csky/include/asm/Kbuild
between commit:
fed76f8679a6 ("csky: Add QUEUED_SPINLOCKS supported")
from the csky tree and commit:
6e9ae6f98809 ("csky: Enable seccomp architecture tracking")
from the seccomp tree.
Le 21/05/2020 à 12:38, Christophe Leroy a écrit :
Le 21/05/2020 à 09:02, Michael Ellerman a écrit :
Arnd Bergmann writes:
+On Wed, Apr 8, 2020 at 2:04 PM Michael Ellerman wrote:
Benjamin Herrenschmidt writes:
On Fri, 2020-04-03 at 15:59 +1100, Michael Ellerman wrote:
Benjamin
On 11/25/2020 02:27 PM, Chunfeng Yun wrote:
On Tue, 2020-11-24 at 19:31 -0800, Randy Dunlap wrote:
On 11/24/20 6:24 PM, Chunfeng Yun wrote:
Hi Tiezhu,
On Tue, 2020-11-24 at 17:47 +0800, Tiezhu Yang wrote:
devm_ioremap_resource() will be not built in lib/devres.c if
CONFIG_HAS_IOMEM is not
On Tue, 2020-11-24 at 19:31 -0800, Randy Dunlap wrote:
> On 11/24/20 6:24 PM, Chunfeng Yun wrote:
> > Hi Tiezhu,
> >
> > On Tue, 2020-11-24 at 17:47 +0800, Tiezhu Yang wrote:
> >> devm_ioremap_resource() will be not built in lib/devres.c if
> >> CONFIG_HAS_IOMEM is not set,
On Fri, Nov 20, 2020 at 07:44:24PM +0800, Feng Tang wrote:
> On Fri, Nov 13, 2020 at 03:34:36PM +0800, Feng Tang wrote:
> > > I would rather focus on a more effective mem_cgroup layout. It is very
> > > likely that we are just stumbling over two counters here.
> > >
> > > Could you try to add
在 2020/11/25 上午1:59, Lorenzo Stoakes 写道:
> On Tue, 24 Nov 2020 at 07:54, syzbot
> wrote:
>> syzbot found the following issue on:
>>
>> HEAD commit:d9137320 Add linux-next specific files for 20201124
>
> This appears to be a product of 4b2904f3 (&
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 127c501a03d5db8b833e953728d3bcf53c8832a9
commit: 1b7efaa6154960396f414551841f1886d99b6872 Merge tag 'timers-v5.9' of
https://git.linaro.org/people/daniel.lezcano/linux into timers/core
date: 4 months ago
On 2020/11/25 3:57, Geert Uytterhoeven wrote:
> There is no need to enable Virtual Terminal support in the Canaan
> Kendryte K210 defconfigs, as no terminal devices are supported and
> enabled. Hence disable CONFIG_VT, and remove the no longer needed
> override for CONFIG_VGA_CONSOLE.
>
> This
The LID state can be read from GPIO 124 and the "tablet mode" from GPIO
95, expose these to the system using gpio-keys and mark the falling edge
of the LID state as a wakeup-source - to wake the system from suspend.
Signed-off-by: Bjorn Andersson
---
Peter,
>
>>On 20-11-19 15:12:57, Pawel Laszczak wrote:
>>> This patch introduce new Cadence USBSS DRD driver to linux kernel.
>>>
>>> The Cadence USBSS DRD Controller is a highly configurable IP Core which
>>> can be instantiated as Dual-Role Device (DRD), Peripheral Only and
>>> Host Only
Hi Steve,
On Fri, Oct 30, 2020 at 12:43:24AM -0500, Steve French wrote:
> I typically build cifs.ko for testing using the latest Ubuntu mainline
> build - but building a module in the 5.10-rc1 kernel - while booted to
> the 5.10-rc1 ubuntu mainlinekerel - e.g. "make C=1 -C
>
Jakub Kicinski writes:
> On Mon, 23 Nov 2020 00:40:30 +0100 Rikard Falkeborn wrote:
>> These are only used as input arguments to qmi_handle_init() which
>> accepts const pointers to both qmi_ops and qmi_msg_handler. Make them
>> const to allow the compiler to put them in read-only memory.
>>
>>
Hi Randy,
On 04-11-20, 19:32, Randy Dunlap wrote:
> On 11/2/20 11:47 AM, kernel test robot wrote:
> > All errors (new ones prefixed by >>):
> >
> >or1k-linux-ld: drivers/soundwire/qcom.o: in function `qcom_swrm_probe':
> >>> drivers/soundwire/qcom.c:767: undefined reference to `slimbus_bus'
Attempting to send a power request during PM operations, when the QMI
handle isn't initialized results in a NULL pointer dereference. So check
if the QMI handle has been initialized before attempting to post the
power requests.
Fixes: 917809e2280b ("slimbus: ngd: Add qcom SLIMBus NGD driver")
On 2020-11-25 03:09, Will Deacon wrote:
On Mon, Nov 23, 2020 at 10:35:56PM +0530, Sai Prakash Ranjan wrote:
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Hello,
On Mon, Nov 23, 2020 at 02:01:16PM +0100, Vlastimil Babka wrote:
> On 11/21/20 8:45 PM, Andrea Arcangeli wrote:
> > A corollary issue was fixed in
> > 39639000-39814fff : Unknown E820 type
> >
> > pfn 0x7a200 -> 0x7a20 min_pfn hit non-RAM:
> >
> > 7a17b000-7a216fff : Unknown E820
> -Original Message-
> From: Lars-Peter Clausen
> Sent: Tuesday, November 24, 2020 10:43 AM
> To: Ardelean, Alexandru ; linux-
> in...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: dmitry.torok...@gmail.com
> Subject: Re: [PATCH v2 3/3] Input: adp5589-keys - add basic devicetree
Update the VIM3/3L common dtsi to use the new function/color bindings.
Suggested-by: Artem Lapkin
Signed-off-by: Christian Hewitt
---
This supersedes a previous submission from Art [0] and uses the updated
LED bindings suggested by Neil.
[0]
On 11/12/20 3:43 PM, Suzuki K Poulose wrote:
> On 11/10/20 12:45 PM, Anshuman Khandual wrote:
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>> accessible via the system registers. The TRBE supports different addressing
>> modes including CPU virtual address and
Hi Wei,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tip/x86/core]
[also build test WARNING on asm-generic/master iommu/next tip/timers/core
pci/next linus/master v5.10-rc5]
[cannot apply to next-20201124]
[If your patch is applied to the wrong git tree, kindly
On Wed, Nov 25, 2020 at 04:48:05AM +0100, Sebastian Krzyszkowiak wrote:
> I've checked bq25890, bq25892, bq25895 and bq25896 datasheets and
> they all define IILIM to be between 100mA-3.25A with 50mA steps.
That's what DS says, indeed.
Reviewed-by: Michał Mirosław
The SBI SRST extension provides a standard way to poweroff and
reboot the system irrespective to whether Linux RISC-V S-mode
is running natively (HS-mode) or inside Guest/VM (VS-mode).
The SBI SRST extension is available in latest SBI v0.3-draft
specification at:
Add basic devicetree support for SDX55 platform and MTP board from
Qualcomm. The SDX55 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the
Hello,
This series adds devicetree support for Qualcomm SDX55 platform and MTP
board. This series functionally depends on Clock support series [1]
which is under review.
With the current devicetree support, the MTP can boot into initramfs
shell.
Thanks,
Mani
[1]
From: Vinod Koul
Document the SDX55 platform binding and also the boards using it.
Signed-off-by: Vinod Koul
Signed-off-by: Manivannan Sadhasivam
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git
On 24-11-20, 21:07, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> The 'master' device acts as a glue layer used during bus
> initialization only, and it needs to be 'transparent' for pm_runtime
> management. Its behavior should be that it becomes active when one of
> its children becomes
On 24-11-20, 09:33, Bard Liao wrote:
> We wrote 1 to the handled interrupts bits along with 0 to all other bits
> to the SoundWire DPx interrupt register. However, DP0 has reserved fields
> and the read-only SDCA_CASCADE bit. DPN also has reserved fields. We should
> not try to write values in
On Tue, Nov 24, 2020 at 07:38:55PM +0800, Suzuki K Poulose wrote:
> On 11/24/20 12:41 AM, Tingwei Zhang wrote:
> >On Mon, Nov 23, 2020 at 05:39:43PM +0800, Suzuki K Poulose wrote:
> >>On 11/23/20 7:58 AM, Tingwei Zhang wrote:
> >>>Hi Suzuki,
> >>>
> >>>On Fri, Nov 20, 2020 at 12:45:42AM +0800,
Hi,
I happened to hit a kdump hang issue in a Linux VM running on some
Hyper-V host. Please see the attached log: the kdump kernel always hangs,
even if I configure only 1 virtual CPU to the VM.
I firstly hit the issue in RHEL 8.3's 4.18.x kernel, but later I found that
the latest upstream
1 - 100 of 1495 matches
Mail list logo
