Re: [PATCH] powerpc, kexec: Fix Processor X is stuck issue during kexec from ST mode

Hi Srivatsa, On Sat, Jun 7, 2014 at 7:16 AM, Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com wrote: And with the following hunk added (which I had forgotten earlier), it worked just fine on powernv :-) How are the patches coming along? I just hung a machine here while attempting to kexec.

Re: [PATCH] cpuidle/powernv: Re-enable fastsleep at boot time

Hey Preeti, On Tue, Nov 18, 2014 at 5:26 PM, Preeti U Murthy pre...@linux.vnet.ibm.com wrote: Commit dcb18694 Fix ipi on palmeto disabled fastsleep at boot time. I couldn't find this commit in any tree; upstream, mpe's next, nor powerkvm. I remember testing this as a workaround for the

[PATCH 2/2] powerpc/powernv: Reboot when requested by firmware

Use orderly_reboot so userspace will to shut itself down via the reboot path. This is required for graceful reboot initiated by the BMC, such as when a user uses ipmitool to issue a 'chassis power cycle' command. Signed-off-by: Joel Stanley j...@jms.id.au --- arch/powerpc/platforms/powernv/opal

[PATCH 1/2] kernel/reboot.c: Add orderly_reboot for graceful reboot

on platforms that do not use ACPI. Signed-off-by: Joel Stanley j...@jms.id.au --- include/linux/reboot.h | 1 + kernel/reboot.c| 51 +++--- 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/include/linux/reboot.h b/include/linux/reboot.h

Re: [PATCH 1/2] kernel/reboot.c: Add orderly_reboot for graceful reboot

Hi Andrew, On Wed, Apr 1, 2015 at 9:09 AM, Andrew Morton a...@linux-foundation.org wrote: On Mon, 30 Mar 2015 12:45:32 +1030 Joel Stanley j...@jms.id.au wrote: The kernel has orderly_poweroff which allows the kernel to initiate a graceful shutdown of userspace, by running /sbin/poweroff

Re: [PATCH 1/2] kernel/reboot.c: Add orderly_reboot for graceful reboot

On Wed, Apr 1, 2015 at 3:22 PM, Anshuman Khandual khand...@linux.vnet.ibm.com wrote: +static int __orderly_poweroff(bool force) +{ + int ret; + + ret = run_cmd(reboot_cmd); Would it be poweroff_cmd instead of reboot_cmd ? Dont see poweroff_cmd getting used. Yes, good catch.

[PATCH v2 2/3] kernel/reboot.c: Add orderly_reboot for graceful reboot

-by: Joel Stanley j...@jms.id.au --- V2: - remove unused return value from orderly_* - use correct command in orderly_poweroff - the reboot command will not have a proc knob to control it, so it can be made const and static include/linux/reboot.h | 3 ++- kernel/reboot.c| 53

[PATCH v2 3/3] powerpc/powernv: Reboot when requested by firmware

Use orderly_reboot so userspace will to shut itself down via the reboot path. This is required for graceful reboot initiated by the BMC, such as when a user uses ipmitool to issue a 'chassis power cycle' command. Signed-off-by: Joel Stanley j...@jms.id.au Acked-by: Michael Ellerman m

[PATCH v2 1/3] envctrl: Ignore orderly_poweroff return value

orderly_poweroff() unconditionally returns 0, so remove the dead code that checks the return value. A future patch will change the return type to void. Signed-off-by: Joel Stanley j...@jms.id.au --- drivers/sbus/char/bbc_envctrl.c | 3 +-- drivers/sbus/char/envctrl.c | 7 +-- 2 files

Re: [PATCH v4 3/6] cpufreq: powernv: Register for OCC related opal_message notification

Hello, On Mon, 2015-07-13 at 19:39 +0530, Shilpasri G Bhat wrote: diff --git a/drivers/cpufreq/powernv-cpufreq.c b/drivers/cpufreq/powernv-cpufreq.c index d0c18c9..1f59958 100644 --- a/drivers/cpufreq/powernv-cpufreq.c +++ b/drivers/cpufreq/powernv-cpufreq.c @@ -414,6 +415,71 @@ static

Re: [PATCH] MAINTAINERS: Add powerpc drivers to the powerpc section

On Wed, Mar 2, 2016 at 12:06 PM, Michael Ellerman wrote: > We'd like folks working on drivers for powerpc to also Cc linuxppc-dev, > so we can be aware of what's going on in drivers and/or review the > changes. > > So add patterns to the powerpc MAINTAINERS section to catch

Re: [PATCH] ARM: aspeed: adapt defconfigs for new CONFIG_PRINTK_TIME

igned-off-by: Arnd Bergmann <a...@arndb.de> > --- > I've applied this one to avoid introducing warnings in linux-next. > I could have sorted out the ordering as well to avoid warnings > in arm-soc/for-next, but it doesn't seem worth it as we are not > regressing here.

Re: [PATCH 02/12] pinctrl: Add core pinctrl support for Aspeed SoCs

cular SoC, just adds the framework for defining mux configurations > for any available functions. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Joel Stanley <j...@jms.id.au> > --- > MAINTAINERS | 1 + > arch/arm/mach

Re: [PATCH] ARM: dont specify STACKPROTECTOR in defconfigs

ears ago. > Since there are only three of them, and there is nothing about these > settings that are board/platform specific, I propose we just eliminate > the three existing instances and take the default. This makes sense to me. Acked-by: Joel Stanley <j...@jms.id.au>

Re: [PATCH] gpio: aspeed: Remove dependence on GPIOF_* macros

ff > between v2 and v3[2]). > > [1] https://lkml.org/lkml/2017/1/26/337 > [2] https://lkml.org/lkml/2017/1/26/786 > > Fixes: 1736f75d35e4 ("gpio: aspeed: Add banks Y, Z, AA, AB and AC") > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Sta

Re: [PATCH v2] drivers/mailbox: Add Aspeed mailbox driver

On Wed, Feb 8, 2017 at 10:06 AM, Cyril Bur wrote: > This provides access to the mbox registers on the ast2400 and ast2500 > SoCs. > > This driver allows arbitrary reads and writes to the 16 data registers as > the other end may have configured the mbox hardware to provide an >

Re: [PATCH v3] gpio: aspeed: Add banks Y, Z, AA, AB and AC

4 SoC bank > AC doesn't exist. > > Add some structs to describe the varying properties of different banks > and integrate mechanisms to deny requests for unsupported > configurations. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Stanley <j...@

Re: [PATCH] gpio: aspeed: Add debounce support

On Tue, Feb 21, 2017 at 1:10 AM, Andrew Jeffery wrote: > Each GPIO in the Aspeed GPIO controller can choose one of four input > debounce states: to not debounce an input or to select from one of three > programmable debounce timer values. Each GPIO in a four-bank-set is >

Re: [PATCH] pinctrl: aspeed: Add initial pinconf support

On Tue, Feb 21, 2017 at 1:08 AM, Andrew Jeffery wrote: > Several pinconf parameters have a fairly straight-forward mapping onto > the Aspeed pin controller. These include management of pull-down bias, > drive-strength, and some debounce configuration. > > Pin biasing largely is

Re: [PATCH] gpio: aspeed: Add debounce support

On Wed, Feb 22, 2017 at 2:46 PM, Joel Stanley <j...@jms.id.au> wrote: >> + /* >> +* Check if a timer is already configured for the requested >> +* debounce period. If so, just add @offset as a user of this >

Re: [PATCH v2] ipmi: bt-bmc: Use a regmap for register access

-syscon- based devicetree descriptions by always using a regmap for > register access, either retrieved from the parent syscon device or > instantiated if none exists. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> > Reviewed-by: Cédric Le Goater <c...@kaod.org> Revi

Re: [PATCH v5] drivers/misc: Add Aspeed LPC control driver

On Tue, Feb 14, 2017 at 5:00 PM, Cyril Bur wrote: > diff --git a/drivers/misc/aspeed-lpc-ctrl.c b/drivers/misc/aspeed-lpc-ctrl.c > new file mode 100644 > index ..9b51548e9d81 > --- /dev/null > +++ b/drivers/misc/aspeed-lpc-ctrl.c > +static long

Re: [PATCH linux v7 5/6] hwmon: occ: Add hwmon implementation for the P8 OCC

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > From: "Edward A. James" > > Add code to tie the hwmon sysfs code and the POWER8 OCC code together, as > well as probe the entire driver from the I2C bus. I2C is the communication > method between the BMC

Re: [PATCH linux v7 4/6] hwmon: occ: Add callbacks for parsing P8 OCC datastructures

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > From: "Edward A. James" > > Add functions to parse the data structures that are specific to the OCC on > the POWER8 processor. These are the sensor data structures, including > temperature, frequency,

Re: [PATCH linux v7 1/6] hwmon: Add core On-Chip Controller support for POWER CPUs

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > diff --git a/Documentation/hwmon/occ b/Documentation/hwmon/occ > new file mode 100644 > index 000..79d1642 > --- /dev/null > +++ b/Documentation/hwmon/occ The kernel is using reStructuredText these days. You should

Re: [PATCH linux v7 2/6] hwmon: occ: Add sysfs interface

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > From: "Edward A. James" > > Add a generic mechanism to expose the sensors provided by the OCC in > sysfs. > > Signed-off-by: Edward A. James > Signed-off-by: Andrew Jeffery

Re: [PATCH linux v7 6/6] hwmon: occ: Add callbacks for parsing P9 OCC datastructures

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > From: "Edward A. James" > > Add functions to parse the data structures that are specific to the OCC on > the POWER9 processor. These are the sensor data structures, including > temperature, frequency,

Re: [PATCH linux v7 3/6] hwmon: occ: Add I2C transport implementation for SCOM operations

On Wed, Feb 8, 2017 at 9:40 AM, wrote: > From: "Edward A. James" > > Add functions to send SCOM operations over I2C bus. The BMC can > communicate with the Power8 host processor over I2C, but needs to use SCOM > operations in order to access the

Re: [PATCH v4] drivers/misc: Add Aspeed LPC control driver

Hey Greg, On Sat, Feb 11, 2017 at 1:00 AM, Greg KH wrote: > On Wed, Feb 08, 2017 at 10:42:47AM +1100, Cyril Bur wrote: >> In order to manage server systems, there is typically another processor >> known as a BMC (Baseboard Management Controller) which is responsible

Re: [PATCH 3/3] DT: add Faraday Tec. as vendor

s Ulli Kroll <ulli.kr...@googlemail.com> > > Reviewed-by: Linus Walleij <linus.wall...@linaro.org> > > I think I should use this for the PCI block as well, looking over some > code and the root hub is using Faraday's PCI ID. Acked-by: Joel Stanley <j...@jms.id.au&g

Re: [RESEND PATCH linux] aspeed: pinctrl: Allow disabling Port D and Port E loopback mode

nge the strap. Hence the patch. > Signed-off-by: Rick Altherr <ralth...@google.com> Acked-by: Joel Stanley <j...@jms.id.au> Cheers, Joel > --- > drivers/pinctrl/aspeed/pinctrl-aspeed.c | 14 -- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff

Re: [PATCH v6] drivers/misc: Add Aspeed LPC control driver

t;Removed unused functions >Removed use of access_ok() >All input is evil >Reworked the interface as per Benjamin Herrenschmidts vision > v3: >Removed 'default y' from Kconfig >Reordered ioctl() struct fields >Reworeded some comments > v4: > Reorder

Re: [GIT PULL] ARM: aspeed: devicetree for 4.11

On Thu, Jan 19, 2017 at 11:27 AM, Olof Johansson <o...@lixom.net> wrote: > On Wed, Jan 18, 2017 at 09:50:02AM +1100, Joel Stanley wrote: >> These commits also add newly upstreamed drivers to the Palmetto BMC and >> ast2500 >> eval board. We now have working networ

[GIT PULL] ARM: aspeed: defconfig for 4.11

that updates our defconfigs with network (ftgmac100 and ncsi), bt ipmi, gpio and ncsi. ARM: configs: Update Aspeed with new drivers Joel Stanley (1): ARM: configs: Update Aspeed with new drivers arch/arm/configs

[GIT PULL] ARM: aspeed: devicetree for 4.11

-g5: Add gpio controller to devicetree Cyril Bur (2): ARM: dts: aspeed: Reserve framebuffer memory ARM: dts: aspeed: Correct palmetto device tree Joel Stanley (2): ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platforms ARM: dts: aspeed: Add Romulus BMC platform arch/arm

[GIT PULL] ARM: aspeed: soc for 4.11

Hello Arnd and Olof, Please pull the Aspeed soc tree for 4.11. The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77: Linux 4.10-rc1 (2016-12-25 16:13:08 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git

Re: [PATCH 2/2] hwmon: Aspeed AST2400/AST2500 ADC

On Wed, Mar 1, 2017 at 6:44 AM, Rick Altherr wrote: > Aspeed AST2400/AST2500 BMC SoCs include a 16 channel, 10-bit ADC. This > driver implements reading the ADC values, enabling channels via device > tree, and optionally providing channel labels via device tree. Low and >

Re: [PATCH 1/2] Documentation: dt-bindings: Document bindings for Aspeed AST2400/AST2500 ADC

On Wed, Mar 1, 2017 at 6:44 AM, Rick Altherr <ralth...@google.com> wrote: > Signed-off-by: Rick Altherr <ralth...@google.com> Acked-by: Joel Stanley <j...@jms.id.au> > --- > .../devicetree/bindings/hwmon/aspeed_adc.txt | 48 > ++ &g

Re: [PATCH v2 1/8] MAINTAINERS: Add glob for Aspeed devicetree bindings

On Fri, Aug 19, 2016 at 10:14 PM, Andrew Jeffery <and...@aj.id.au> wrote: > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Stanley <j...@jms.id.au> > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINER

Re: [PATCH v2 6/8] pinctrl: Add pinctrl-aspeed-g4 driver

o > development machine. Looks good to me. I've given them a run on a few different machines. You've addressed all of issues I had from v1. > > [1] https://github.com/openbmc/docs > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Joel Stanley <j...@jms.id.au>

Re: [PATCH v2 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers

> > Signed-off-by: Andrew Jeffery <and...@aj.id.au> With the changes suggested by Rob (and don't forget to update the actual dts!) Acked-by: Joel Stanley <j...@jms.id.au> > --- > > Since v1: > > * Add SoC-specific compatible strings > * Document available fun

Re: [PATCH v2 7/8] pinctrl: Add pinctrl-aspeed-g5 driver

. > > [1] https://github.com/openbmc/docs > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> As with the g4 driver, this looks good and works fine on the ast2500evb and witherspoon boards. Reviewed-by: Joel Stanley <j...@jms.id.au> > --- > > Since v1: > > * Fix the R

Re: [PATCH v2 5/8] pinctrl: Add core support for Aspeed SoCs

oint, I will look at rearranging it. As discussed, lets go with Linus' suggestion. >> >> The expression core engine is still a complete mystery >> for me, I will just trust you that it works as intended. > > Gah! However, thanks! Does what it says on the box. Good work! Reviewed-by: Joel Stanley <j...@jms.id.au>

Re: [PATCH v2 2/8] syscon: dt-bindings: Add documentation for Aspeed system control units

On Fri, Aug 19, 2016 at 10:14 PM, Andrew Jeffery <and...@aj.id.au> wrote: Nothing to say here? > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Stanley <j...@jms.id.au> > --- > > Since v1: > > * Add SoC-specific compatible strings > &

Re: [PATCH v2 4/8] gpio: dt-bindings: Add documentation for Aspeed GPIO controllers

interrupts, then it should be marked as an >> interrupt-controller. It never should have been optional. The OS can >> ignore the interrupt properties if it chooses. > > Right, clearly there was some confusion on my part. I will fix that up. > Thanks for clarifying. > Thanks for clarifying this Rob. With this cleared up, Acked-by: Joel Stanley <j...@jms.id.au>

Re: [PATCH 2/2] clocksource/drivers/moxart: Replace panic by pr_err

iel Lezcano <daniel.lezc...@linaro.org> Acked-by: Joel Stanley <j...@jms.id.au> > --- > drivers/clocksource/moxart_timer.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/clocksource/moxart_timer.c > b/drivers/clocksource/moxart_t

Re: [PATCH 1/2] clocksource/drivers/moxart: Replace setup_irq by request_irq

On Thu, Sep 8, 2016 at 11:28 PM, Daniel Lezcano <daniel.lezc...@linaro.org> wrote: > Save memory space and line of code by replacing setup_irq by request_irq. Thanks. I also gave it a spin on our hardware to be sure. > Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org&g

Re: [PATCH] pinctrl: aspeed: fix regmap error handling

assigning to the temporary variable. Thanks for finding this Arnd. Colin also found the issue. Thanks Colin! I think we should take this version of the fix. Linus, can you put this in your tree please? > Signed-off-by: Arnd Bergmann <a...@arndb.de> Acked-by: Joel Stanley <j...@jms

Re: [PATCH v3 4/7] palmetto: Request relevant mux functions in devicetree

On Wed, Sep 14, 2016 at 6:28 AM, Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote: > On Tue, 2016-09-13 at 22:11 +0930, Joel Stanley wrote: >> It's not clear that all systems use these pins in that way. I will >> not >> include this one for now. > > Well, i

[PATCH] gpio: aspeed: Fix missing licence warning in modpost

gt; 361b79119a4b ("gpio: Add Aspeed driver") Fix it by adding the correct licence. Fixes: 361b79119a4b ("gpio: Add Aspeed driver") Reported-by: Stephen Rothwell <s...@canb.auug.org.au> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/gpio/gpio-aspeed.c | 1 +

Re: [PATCH v3 4/7] palmetto: Request relevant mux functions in devicetree

On Tue, Aug 30, 2016 at 5:25 PM, Andrew Jeffery wrote: > + { > + pinctrl-names = "default"; > + pinctrl-0 = <_flbusy_default _flwp_default > + _vgahs_default _vgavs_default > + _ddcclk_default _ddcdat_default > + > +

Re: [PATCH v3 0/7] aspeed: Integrate pinctrl and gpio drivers

On Tue, Aug 30, 2016 at 5:25 PM, Andrew Jeffery wrote: > Here's v3 of the Aspeed pinctrl and gpio driver integration patches. v2 of the > integration series can be found at: > > https://lkml.org/lkml/2016/8/19/403 Looks good to me. I commented on the two patches that I don't

Re: [PATCH v3 2/7] mach-aspeed: Select GPIO driver

On Tue, Aug 30, 2016 at 5:25 PM, Andrew Jeffery wrote: > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index f3f8c5c658db..5aba9598f821 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -7,6 +7,8 @@ menuconfig

[PATCH] ipmi: Fix ioremap error handling in bt-bmc

devm_ioremap_resource returns ERR_PTR so we can't check for NULL. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/char/ipmi/bt-bmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c index 2e880b

Re: [PATCH net-next 6/7] net/faraday: Fix phy link irq on Aspeed G5 SoCs

On Wed, Sep 21, 2016 at 6:33 PM, Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote: > On Wed, 2016-09-21 at 11:32 +0930, Joel Stanley wrote: >> I had a look at the eval board schematic and it appears that the line >> has pull down resistors on it, explaining why th

[RFC PATCH] xhci: do not halt the secondary HCD

, and when we kexec the devices don't come back until a system power cycle. I'd like some advice on an acceptable way to upstream the fix, so that the xhci device survives kexec. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/usb/host/xhci.c | 20 +++- 1 file chang

[PATCH net-next 0/7] ftgmac100 support for ast2500

with the NCSI stack and with a directly attached PHY. Cheers, Joel Andrew Jeffery (2): net/ftgmac100: Separate rx page storage from rxdesc net/ftgmac100: Make EDO{R,T}R bits configurable Gavin Shan (2): net/faraday: Avoid PHYSTS_CHG interrupt net/faraday: Clear stale interrupts Joel Stanley (3

[PATCH net-next 2/7] net/faraday: Make EDO{R,T}R bits configurable

From: Andrew Jeffery <and...@aj.id.au> These bits are #defined at a fixed location. In order to support future hardware that has chosen to move these bits around move the bits into a member of the struct ftgmac100. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Signed-off-by: Joe

[PATCH net-next 1/7] net/faraday: Separate rx page storage from rxdesc

mac100. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/dr

[PATCH net-next 7/7] net/faraday: Configure old MDIO interface on Aspeed SoCs

The Aspeed SoCs have a new MDIO interface as an option in the G4 and G5 SoCs. The old one is still available, so select it in order to remain compatible with the ftgmac100 driver. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 9 + drive

[PATCH net-next 4/7] net/faraday: Avoid PHYSTS_CHG interrupt

effect is CPU cycles wasted to process the false alarm. This sets bit#11 in MACCR (0x50) to avoid the bogus interrupt. Signed-off-by: Gavin Shan <gws...@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 1 + drivers/ne

[PATCH net-next 3/7] net/faraday: Adapt for Aspeed SoCs

marked as reserved but still functional. In the ast2500 this bit is reused for another function, so we need a work around. This was confirmed with engineers from Aspeed that using bit 30 is correct for both the ast2400 and ast2500 SoCs. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drive

[PATCH net-next 6/7] net/faraday: Fix phy link irq on Aspeed G5 SoCs

: [ISR] = 0x200: PHYSTS_CHG [ 20.30] ftgmac100 1e66.ethernet eth0: [ISR] = 0x200: PHYSTS_CHG This is because the driver was enabling low-level sensitive interrupt generation where the systems are wired for high-level. All CPU cycles are spent servicing this interrupt. Signed-off-by: Joel

[PATCH net-next 5/7] net/faraday: Clear stale interrupts

he MAC. Signed-off-by: Gavin Shan <gws...@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday

Re: [RFC PATCH] xhci: do not halt the secondary HCD

Hi Mathias, On Mon, Sep 19, 2016 at 4:33 PM, Greg KH <gre...@linuxfoundation.org> wrote: > On Mon, Sep 19, 2016 at 04:05:45PM +0930, Joel Stanley wrote: >> We can't halt the secondary HCD, because it's also the primary HCD, >> which will cause problems if we have devices at

Re: [PATCH v2 2/2] i2c: aspeed: added documentation for Aspeed I2C driver

Hi Brendan, On Wed, Sep 21, 2016 at 3:35 AM, Brendan Higgins wrote: > First off, someone pointed out to me that the mapping that I used between > addresses and bus numbers is not actually valid for busses 8-14. > > This could be fixed by checking the offset, but I am

[PATCH net-next v2 4/6] net/faraday: Clear stale interrupts

he MAC. Signed-off-by: Gavin Shan <gws...@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday

[PATCH net-next v2 5/6] net/faraday: Configure old MDIO interface on Aspeed SoCs

The Aspeed SoCs have a new MDIO interface as an option in the G4 and G5 SoCs. The old one is still available, so select it in order to remain compatible with the ftgmac100 driver. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 9 + drive

[PATCH net-next v2 6/6] net/faraday: Mask out PHYSTS_CHG interrupt

discussion. Signed-off-by: Joel Stanley <j...@jms.id.au> --- v2: - Reworked to mask out PHYSTS_CHG instead of trying to determine the IRQ line level drivers/net/ethernet/faraday/ftgmac100.c | 10 +++--- drivers/net/ethernet/faraday/ftgmac100.h | 1 + 2 files changed, 4 insertions

[PATCH net-next 0/7] ftgmac100 support for ast2500

with the NCSI stack and with a directly attached PHY. Cheers, Joel Andrew Jeffery (2): net/ftgmac100: Separate rx page storage from rxdesc net/ftgmac100: Make EDO{R,T}R bits configurable Gavin Shan (2): net/faraday: Avoid PHYSTS_CHG interrupt net/faraday: Clear stale interrupts Joel Stanley (3

[PATCH net-next v2 3/6] net/faraday: Adapt for Aspeed SoCs

marked as reserved but still functional. In the ast2500 this bit is reused for another function, so we need a work around. This was confirmed with engineers from Aspeed that using bit 30 is correct for both the ast2400 and ast2500 SoCs. Signed-off-by: Joel Stanley <j...@jms.id.au> --- drive

[PATCH net-next v2 0/6] ftgmac100 support for ast2500

interrupt, as it helps keep us safe from unhygienic (vendor) bootloaders. Cheers, Joel Andrew Jeffery (2): net/faraday: Separate rx page storage from rxdesc net/faraday: Make EDO{R,T}R bits configurable Gavin Shan (1): net/faraday: Clear stale interrupts Joel Stanley (3): net/faraday

[PATCH net-next v2 1/6] net/faraday: Separate rx page storage from rxdesc

mac100. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Signed-off-by: Joel Stanley <j...@jms.id.au> --- drivers/net/ethernet/faraday/ftgmac100.c | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/dr

[PATCH net-next v2 2/6] net/faraday: Make EDO{R,T}R bits configurable

From: Andrew Jeffery <and...@aj.id.au> These bits are #defined at a fixed location. In order to support future hardware that has chosen to move these bits around move the bits into a member of the struct ftgmac100. Signed-off-by: Andrew Jeffery <and...@aj.id.au> Signed-off-by: Joe

Re: [PATCH net-next 0/7] ftgmac100 support for ast2500

Please ignore this one. On Thu, Sep 22, 2016 at 8:33 AM, Joel Stanley <j...@jms.id.au> wrote: > Hello Dave, > > This series adds support to the ftgmac100 driver for the Aspeed ast2400 and > ast2500 SoCs. In particular, they ensure the driver works correctly on the > ast250

Re: [PATCH net-next 6/7] net/faraday: Fix phy link irq on Aspeed G5 SoCs

On Wed, Sep 21, 2016 at 12:59 AM, Andrew Lunn <and...@lunn.ch> wrote: > On Tue, Sep 20, 2016 at 10:13:14PM +1000, Benjamin Herrenschmidt wrote: >> On Tue, 2016-09-20 at 16:00 +0930, Joel Stanley wrote: >> > On Aspeed SoC with a direct PHY connection (non-NSCI), we recei

Re: [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state

On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery wrote: > The System Control Unit IP in the Aspeed SoCs is typically where the > pinmux configuration is found. > > But not always. > > On the AST2400 and AST2500 a number of pins depend on state in one of > the SIO, LPC or GFX IP

Re: [PATCH 8/8] pinctrl: aspeed-g5: Add mux configuration for all pins

valuation board. > Now, update the bindings document to reflect the complete functionality > and implement the necessary pin configuration tables in the driver. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Stanley <j...@jms.id.au> > --- > Docu

Re: [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins

Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Joel Stanley <j...@jms.id.au> > --- > drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.

Re: [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function

ich is nothing unusual on its own, but in this case the bit was also > participating in a multi-bit bitfield and therefore represented multiple > functions. This fact was overlooked in the original patch. > > Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) > Signed-off-by: Andrew Jeff

Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins

ndings document > to reflect the complete functionality and implement the necessary pin > configuration tables in the driver. > > Cc: Timothy Pearson <tpear...@raptorengineering.com> > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Acked-by: Joel Stanley <j...@jms.id.au>

Re: [PATCH 3/8] pinctrl: aspeed-g5: Fix GPIOE1 typo

On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <and...@aj.id.au> wrote: > This prevented C20 from successfully being muxed as GPIO. > > Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Joel

Re: [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state

e mux function evaluation logic to > use approach 2. above, however the existing code was using approach 3. > The problem was brought to light on the Palmetto machines where the > strap register value is 0x120ce416, and prevented GPIO requests in bank > H from succeeding despit

Re: [RFC PATCH] xhci: do not halt the secondary HCD

On Tue, Sep 20, 2016 at 5:56 PM, Mathias Nyman wrote: > Quick Googling shows that that TI TUSB 73x0 USB3.0 xHCI host has an issue > with halting. > > Errata says host needs 125us to 1ms between the last control transfer and > clearing the run/stop bit. (halting the

Re: [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)

On Thu, Nov 10, 2016 at 4:56 AM, Rob Herring wrote: > On Thu, Nov 03, 2016 at 01:07:57AM +1030, Andrew Jeffery wrote: >> The Aspeed SoC Display Controller is presented as a syscon device to >> arbitrate access by display and pinmux drivers. Video pinmux >> configuration on fifth

[PATCH] hwmon: (adm1275) Enable adm1278 VOUT sampling

From: Yi Li <adaml...@msn.com> The adm1278 can optionally monitor the VOUT pin. This functionality is not enabled at reset, so PMON_CONFIG needs to be modified in order to enable it. Signed-off-by: Yi Li <adaml...@msn.com> Signed-off-by: Joel Stanley <j...@jms.id.au> --- Gue

[PATCH v2] hwmon: (adm1275) Enable adm1278 VOUT sampling

From: Yi Li <adaml...@msn.com> The adm1278 can optionally monitor the VOUT pin. This functioanltiy is not enabled at reset, so PMON_CONFIG needs to be modified in order to enable it. Signed-off-by: Yi Li <adaml...@msn.com> Signed-off-by: Joel Stanley <j...@jms.id.au> --- v2

Re: [PATCH v2] hwmon: (adm1275) Enable adm1278 VOUT sampling

On Tue, Oct 18, 2016 at 3:50 AM, Guenter Roeck <li...@roeck-us.net> wrote: > On Mon, Oct 17, 2016 at 06:38:53PM +1030, Joel Stanley wrote: >> From: Yi Li <adaml...@msn.com> >> >> The adm1278 can optionally monitor the VOUT pin. This functioanltiy is >> not

Re: [PATCH 1/2] net: phy: broadcom: Update Auxiliary Control Register macros

igned-off-by: Xo Wang <x...@google.com> Reviewed-by: Joel Stanley <j...@jms.id.au> Cheers, Joel > --- > include/linux/brcmphy.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-)

Re: [PATCH 2/2] net: phy: broadcom: Add support for BCM54612E

On Sat, Oct 22, 2016 at 3:50 AM, Xo Wang <x...@google.com> wrote: > This PHY has internal delays enabled after reset. This clears the > internal delay enables unless the interface specifically requests them. > > Signed-off-by: Xo Wang <x...@google.com> Reviewed-by: Joel

Re: [RFC PATCH] mfd: dt: Add Aspeed LPC binding

On Thu, Nov 17, 2016 at 7:46 PM, Arnd Bergmann wrote: > On Thursday, November 17, 2016 4:36:33 PM CET Andrew Jeffery wrote: >> Signed-off-by: Andrew Jeffery >> --- >> >> I'd like to start a discussion about how to handle the LPC register space in >> the Aspeed

Re: [RFC PATCH] mfd: dt: Add Aspeed LPC binding

Hey Linus, On Thu, Nov 17, 2016 at 8:00 PM, Linus Walleij wrote: > On Thu, Nov 17, 2016 at 7:06 AM, Andrew Jeffery wrote: > >> +* Device tree bindings for the Aspeed LPC Controller > > We are going overboard with the lingo sometimes, to the point that

[PATCH] dt-bindings/gpio: Add Aspeed GPIO bindings header

This provides constants for using GPIOs in the device tree on Aspeed SoCs. Signed-off-by: Joel Stanley <j...@jms.id.au> --- The Apseed GPIO driver and binding document went upstream in 4.9, but we forgot to send this patch as part of the series. include/dt-bindings/gpio/aspeed-gpio.

Re: [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]

ch has been tested on an AST2500 EVB. > > Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) > Reported-by: Uma Yadlapati <yadla...@us.ibm.com> > Signed-off-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Joel Stanley <j...@jms.id.au> And tested-by. > This p

Re: [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)

On Thu, Nov 3, 2016 at 1:07 AM, Andrew Jeffery wrote: > The Aspeed LPC Host Controller is presented as a syscon device to > arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on > fifth generation SoCs depends on bits in both the System Control Unit > and the

Re: [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers

On Thu, Nov 3, 2016 at 1:07 AM, Andrew Jeffery wrote: > The System Control Unit IP block in the Aspeed SoCs is typically where > the pinmux configuration is found, but not always. A number of pins > depend on state in one of LPC Host Control (LPCHC) or SoC Display > Controller

Re: [PATCH linux v1 4/4] arm: dts: Add dt-binding to support seven segment display on zaius

Hello Jagha, On Wed, Dec 14, 2016 at 6:25 PM, Jaghathiswari Rankappagounder Natarajan wrote: > Add clock, data and clear signal GPIO lines to control seven segment display > on > zaius platform. > > Signed-off-by: Jaghathiswari Rankappagounder Natarajan The

Re: [PATCH] ipmi: bt-bmc: Use a regmap for register access

On Tue, Dec 6, 2016 at 1:27 PM, Andrew Jeffery wrote: > The registers for the bt-bmc device live under the Aspeed LPC > controller. Devicetree bindings have recently been introduced for the > LPC controller where the "host" portion of the LPC register space is > described as a

Please include Aspeed ARM SoC tree in linux-next

Hello Stephen, I'm the maintainer for the Aspeed ARM SoC tree and I would like it added to linux-next. The tree is a sub-maintainer tree for the Aspeed family of 32-bit ARM SoCs that went upstream earlier last year. Tree: git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git Branch:

Re: [PATCH 02/62] watchdog: aspeed_wdt: Convert to use device managed functions

; - Drop platform_set_drvdata() > - Use devm_watchdog_register_driver() to register watchdog device > > Cc: Joel Stanley <j...@jms.id.au> > Signed-off-by: Guenter Roeck <li...@roeck-us.net> Acked-by: Joel Stanley <j...@jms.id.au> Cheers, Joel > --- > drivers/watchdog/aspeed_wdt.c | 14

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