Re: [PATCH] staging: mt7621-pci: stop using of_pci_range_to_resource

m planning to move it and maintain it. There is minor stuff that must be changed before that but I hope to give that all a try after the next merge window. Best regards, Sergio Paracuellos > Ilya > > On Sat, Apr 10, 2021 at 12:23 PM Sergio Paracuellos > wrote: > > > > Hi Ilya, &g

[PATCH] staging: mt7621-pci: dt-bindings: update bindings to yaml format

Update bindings for this pci controller according to the current device tree and driver code and prepare them to be mainlined porting it to the YAML format. Signed-off-by: Sergio Paracuellos --- Hi Rob, Some concerns here. I was not be able to found any case similar to this binding where sub

Re: [PATCH] staging: mt7621-pci: stop using of_pci_range_to_resource

itly, as > done in aeba3731b150 ("powerpc/pci: Fix IO space breakage after > of_pci_range_to_resource() change"). > > Signed-off-by: Ilya Lipnitskiy > Cc: Sergio Paracuellos > --- > drivers/staging/mt7621-pci/pci-mt7621.c | 11 ++- > 1 file changed, 6 insertion

[PATCH v13 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index 6b3db98894cb..f82ad2a621f6 100644

[PATCH v13 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4d68184d3f76..02986055fdbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11484,6 +11484,12 @@ L

[PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v13 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v13 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

clocks as parents for different gates and deriving from 'xtal' using frequencies in[1]. - Adapt dts file and bindings header and documentation for new changes. - Change MAINTAINERS file to only contains clk-mt7621.c code and mediatek,mt7621-clk.yaml file. [0]: https://www.lkml.org/lkml/201

[PATCH v12 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..ecad5d972122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v12 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v12 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index ca0ac607b0f3..5d74fc1c96ac 100644

[PATCH v12 1/4] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v12 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

unique driver and binding 'mt7621-clk'. - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up the timer for the GIC. - Use new fixed clocks as parents for different gates and deriving from

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi, On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2021-03-08 21:22:23) > > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > > new file mode 100644 > > index ..3e3f5cb9ad88 > > --- /dev/nul

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi Stephen, On Fri, Apr 9, 2021 at 8:17 PM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2021-03-23 01:13:22) > > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos > > wrote: > > > > > > Changes in v11: > > > - Collect Rob's Reviewed-by

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi Stephen, On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

[PATCH v11 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Reviewed-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v11 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v11 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..ecad5d972122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

tform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up the timer for the GIC. - Use new fixed clocks as parents for different gates and deriving from 'xtal' using frequencies in[1]. - Adapt dts file and bindings header and documentati

[PATCH v10 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v10 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v10 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v10 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v10 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v10 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v10 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

fixed clocks as parents for different gates and deriving from 'xtal' using frequencies in[1]. - Adapt dts file and bindings header and documentation for new changes. - Change MAINTAINERS file to only contains clk-mt7621.c code and mediatek,mt7621-clk.yaml file. [0]: https://www.lkml.org/lkml/2

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi, On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos wrote: > > Hi again, > > On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos > wrote: > > > > Hi Rob, > > > > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote: > > [snip] > > > >

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi again, On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos wrote: > > Hi Rob, > > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote: > [snip] > > > + > > > + ralink,sysctl: > > > +$ref: /schemas/types.yaml#/definitions/phandle > > > +

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

s patch, please guide me in the correct thing to do. Stephen, Rob, I will be really happy with your help :) Best regards, Sergio Paracuellos > > > + > > + clock-output-names: > > +maxItems: 8 > > + > > +required: > > + - compatible

Re: [PATCH -next] phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()

: Hulk Robot > Signed-off-by: Wei Yongjun > --- > drivers/phy/ralink/phy-mt7621-pci.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Sergio Paracuellos

[PATCH] phy: ralink: phy-mt7621-pci: fix XTAL bitmask

When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-

[PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

tform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up the timer for the GIC. - Use new fixed clocks as parents for different gates and deriving from 'xtal' using frequencies in[1]. - Adapt dts file and bindings header and documentation for new ch

[PATCH v8 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v8 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v8 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v8 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

ious 'mt7621-pll' and 'mt7621-clk' into a unique driver and binding 'mt7621-clk'. - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up the timer for the GIC. - Use new fixed clocks as par

[PATCH v8 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v8 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v8 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v7 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v7 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v7 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v7 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v7 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

tform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up the timer for the GIC. - Use new fixed clocks as parents for different gates and deriving from 'xtal' using frequencies in[1]. - Adapt dts file and bindings header

[PATCH v7 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

Re: [PATCH v2] Staging: mt7621-pci: fixed a blank line coding style issue

(-) Reviewed-by: Sergio Paracuellos Best regards, Sergio Paracuellos

Re: [PATCH] Staging: mt7621-pci: pci-mt7621: fixed a blank line coding style issue

t; } > } > -- > 2.17.1 > Please, also change commit short message to: staging: mt7621-pci: fixed a blank line coding style issue With that changes: Reviewed-by: Sergio Paracuellos Best regards, Sergio Paracuellos

[PATCH v6 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v6 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v6 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v6 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v6 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v6 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v6 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

'drivers/clk/ralink/clk-mt7621.c' and unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver and binding 'mt7621-clk'. - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_time_init' before setting up t

Re: [PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

Re: [PATCH] staging: mt7621-dts: remove obsolete switch node

> 1 file changed, 7 deletions(-) Reviewed-by: Sergio Paracuellos

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Fri, Jan 1, 2021 at 12:51 AM Sergio Paracuellos wrote: > > Hi Rob, > > Thanks for the review. Hi again, > > On Thu, Dec 31, 2020 at 11:38 PM Rob Herring wrote: > > > > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > > > Adds devic

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Rob, Thanks for the review. On Thu, Dec 31, 2020 at 11:38 PM Rob Herring wrote: > > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Sig

Re: drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous prototype for function 'rt2880_pinmux_init'

ted. > > > vim +/rt2880_pinmux_init +365 drivers/pinctrl/ralink/pinctrl-rt2880.c > > 0317d60de869786 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c John Crispin > 2018-03-15 364 > 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio > Paracuellos

[PATCH] pinctrl: ralink: rt2880: fix '-Wmissing-prototypes' in init function

-by: kernel test robot Signed-off-by: Sergio Paracuellos --- Hi Linus, Just a note to let you know that this patch is rebased on the top of this series which are pending to be applied: http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2020-December/149353.html Thanks in advance

[PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f5eafee83bc6..f0c51d9760ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11247,6 +11247,12 @@ L

[PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc'. Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c

[PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts

[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

. - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver and binding 'mt7621-clk'. - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE' because we need clocks available in 'plat_

[PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&q

[PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Rob, On Thu, Dec 17, 2020 at 4:05 PM Rob Herring wrote: > > On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd wrote: > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > > Adds device tree binding documentation for clocks in the > > > MT7621 SO

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:50 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-12-17 02:38:37) > > On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd wrote: > > > > > > Quoting Sergio Paracuellos (2020-12-17 02:14:10) > > > > node is to use arc

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-12-17 02:14:10) > > On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd wrote: > > > > > > Quoting Sergio Paracuellos (2020-12-17 02:01:39) > > > > > > > &g

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

On Thu, Dec 17, 2020 at 11:12 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-12-17 01:54:18) > > > > On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote: > > > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:53) > > > > diff -

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-12-17 02:01:39) > > > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote: > > > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > > > > > >

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Stephen, Thanks for the review! On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos &

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi Stephen, Thanks for the review. On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:53) > > The documentation for this SOC only talks about two > > registers regarding to the clocks: > > * SYSC_REG_CPLL_CLKCFG0 - p

Re: drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous prototype for 'rt2880_pinmux_init'

/staging/mt7621-pinctrl/pinctrl-rt2880.c John Crispin > 2018-03-15 364 > 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio > Paracuellos 2018-07-09 @365 int __init rt2880_pinmux_init(void) > 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c

Re: [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Nov 22, 2020 at 10:55 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

Re: linux-next: manual merge of the staging tree with the phy-next tree

arly > complex conflicts. Thanks for doing this. Removing both in staging is the correct thing to do. > > -- > Cheers, > Stephen Rothwell Best regards, Sergio Paracuellos > > diff --cc drivers/staging/Kconfig > index 4d7a5ddf9992,c42708e60afc.. > ---

Re: [PATCH v3 0/2] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

On Tue, Dec 1, 2020 at 12:44 PM Vinod Koul wrote: > > On 01-12-20, 12:20, Sergio Paracuellos wrote: > > Hi Vinod, > > > > After merging the phy-next tree, today's linux-next build (x86_64 > > allmodconfig) failed like this: > > > > drivers/phy/ralink/phy

[PATCH v3 2/2] phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro

Correct name passed into 'MODULE_DEVICE_TABLE' which was wrong and was showing a warning when the driver is enabled for 'COMPILE_TEST'. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy

[PATCH v3 0/2] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

3 completely changed: - Makefile is not touched. - Drop 'COMPILE_TEST' in Kconfig. - Drop PATCH 2/3 in previous series because COMPILE_TEST does not apply anymore. Changes in v2: - Added 'Reported-by' tag in PATCH 1/3. Best regards, Sergio Paracuellos Sergio Paracuellos (2): phy

[PATCH v3 1/2] phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig

to avoid the problem. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by: Stephen Rothwell Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ralink/Kconfig b/d

Re: [PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

Hi Vinod, On Tue, Dec 1, 2020 at 12:02 PM Vinod Koul wrote: > > On 01-12-20, 11:47, Sergio Paracuellos wrote: > > Hi Vinod, > > > > On Tue, Dec 1, 2020 at 11:42 AM Vinod Koul wrote: > > > > > > On 01-12-20, 11:16, Sergio Paracuellos wrote: > >

[PATCH v2 2/3] phy: ralink: phy-mt7621-pci: avoid warning if COMPILE_TEST is enabled

for 'dev_info' macro. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c index db79088d5362..befa282e2447 100644 --- a/drivers/phy

[PATCH v2 0/3] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

nfig' in x86_64 also showed two warnings for this driver because of pointer size and not valid name for MODULE_DEVICE_TABLE ids. This two have been also fixed and included in this series. Changes in v2: - Added 'Reported-by' tag in PATCH 1/3. Best regards, Sergio Paracuellos Sergio Pa

[PATCH v2 3/3] phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro

Correct name passed into 'MODULE_DEVICE_TABLE' which was wrong and was showing a warning when the driver is enabled for 'COMPILE_TEST'. Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/phy-mt7621-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy

[PATCH v2 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

ll Signed-off-by: Sergio Paracuellos --- drivers/phy/ralink/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile index cda2a4a7ca5e..c8f9adba0d82 100644 --- a/drivers/phy/ralink/Makefile +++ b/drivers/phy/ralink/Makefile @@

Re: [PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

Hi Vinod, On Tue, Dec 1, 2020 at 11:42 AM Vinod Koul wrote: > > On 01-12-20, 11:16, Sergio Paracuellos wrote: > > This driver includes the following two files directly: > > - mt7621.h > > - ralink_regs.h > > > > Compilation for its related platform prop

[PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

its platform is known and this directly included files are not found at all breaking compilation. Fix this problem adding include search path for ralink in ralink phy directory Makefile. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-by: Sergio P

[PATCH 0/3] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

nfig' in x86_64 also showed two warnings for this driver because of pointer size and not valid name for MODULE_DEVICE_TABLE ids. This two have been also fixed and included in this series. Best regards, Sergio Paracuellos Sergio Paracuellos (3): phy: ralink: phy-mt7621-pci: add include sea

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