On Mon, 2020-11-30 at 19:16 +0800, Weiyi Lu wrote:
> On Fri, 2020-11-27 at 13:42 +0100, Matthias Brugger wrote:
> >
> > On 19/11/2020 15:13, Enric Balletbo Serra wrote:
> > > Hi Weiyi,
> > >
> > > Missatge de Weiyi Lu del dia dj., 19 de nov.
> > &
On Wed, 2021-02-10 at 13:46 +0100, Matthias Brugger wrote:
>
> On 22/12/2020 14:09, Weiyi Lu wrote:
> > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > infracfg and pericfg.
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > drivers/clk/m
On Wed, 2021-02-10 at 13:19 +0100, Matthias Brugger wrote:
>
> On 22/12/2020 14:09, Weiyi Lu wrote:
> > This patch adds the new binding documentation of imp i2c wrapper controller
> > for Mediatek MT8192.
>
> The wrapper controller has only clock parts, or are t
On Mon, 2021-02-08 at 17:00 -0800, Stephen Boyd wrote:
> Quoting Weiyi Lu (2020-12-22 05:09:25)
> > This series is based on v5.10-rc1.
> >
>
> The DT bindings fail, can you fix and resend?
>
OK, I'll fix and resend. Thank you for reviewing.
> Documentation/devic
On Sun, 2021-01-31 at 14:27 +0100, Matthias Brugger wrote:
>
> On 22/12/2020 14:40, Weiyi Lu wrote:
> > This series is based on v5.10-rc1, MT8192 dts v6[1] and
> > MT8192 clock v6 series[2].
> >
> > [1] https://patchwork.kernel.org/project/linux-mediatek/lis
On Wed, 2021-01-06 at 18:52 +0800, Ikjoon Jang wrote:
> On Wed, Jan 6, 2021 at 6:42 PM Weiyi Lu wrote:
> >
> > On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> > > On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote:
> > > >
> > > > Ad
On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu wrote:
> >
> > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > infracfg and pericfg.
> >
> > Signed-off-by: Weiyi Lu
> > ---
> &
SUBSYS_CG
(may be dependent clocks)
It will lead some unexpected clock states during system suspend.
This patch will fix by doing prepare_enable/disable_unprepare on
dependent clocks at the same time while we are going to power on/off
any power domain.
Signed-off-by:
This patch is base on v5.10-rc1 and
series "Add new driver for SCPSYS power domains controller"[1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
Weiyi Lu (2):
soc: mediatek: Add regulator control for MT8192 MFG power domain
soc: mediatek: Fix the cloc
the regulator,
if we just want to fix the debugfs warning log by adding names to
power domains. Considering this case, lookup regulator by
regulator_get_optional() instead of getting a dummy regulator from
regulator_get() to operate.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mt8192-pm-domains.h
Add power domains controller node for SoC mt8192
Signed-off-by: Weiyi Lu
---
This patch is base on v5.10-rc1,
series "Add new driver for SCPSYS power domains controller"[1]
and series "Add MediaTek MT8192 clock provider device nodes"[2]
[1] https://patchwork.kernel.org/pr
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index
This series is based on v5.10-rc1, MT8192 dts v6[1] and
MT8192 clock v6 series[2].
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899
[2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295
Weiyi Lu (2):
arm64: dts: mediatek: Add mt8192 clock
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index
Add MT8192 basic clock providers, include topckgen, apmixedsys,
infracfg and pericfg.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig |8 +
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8192.c | 1326 +
drivers/clk
Add MT8192 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt8192-clk.h | 585 +
1 file changed, 585 insertions(+)
create mode 100644 include/dt-bindings/clock/mt8192
Add MT8192 camsys and camsys raw clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-cam.c | 107 ++
3 files changed, 114 insertions(+)
create
This patch adds the new binding documentation of mdpsys controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,mdpsys.yaml | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm
Add MT8192 mdpsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-mdp.c | 82 +++
3 files changed, 89 insertions(+)
create mode 100644
Add MT8192 scp adsp clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 50 ++
3 files changed, 57 insertions(+)
create mode
Add MT8192 mmsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile| 1 +
drivers/clk/mediatek/clk-mt8192-mm.c | 108 +++
3 files changed, 115 insertions(+)
create mode 100644 drivers
This patch adds the new binding documentation of scp adsp controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,scp-adsp.yaml | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm
This patch adds the binding documentation of topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm
.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mtk.h | 2 ++
drivers/clk/mediatek/clk-pll.c | 15 ++-
2 files changed
error checking in probe() function
- fix incorrect clock relation and add critical clocks
- update license identifier and minor fix of coding style
changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC
Weiyi Lu (22):
dt-bindings: ARM
Add MT8192 imp i2c wrapper clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 119 +
3 files changed, 126 insertions
patch series.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-pll.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f440f2cd..11ed5d1 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b
This patch adds the new binding documentation of imp i2c wrapper controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../arm/mediatek/mediatek,imp_iic_wrap.yaml| 78 ++
1 file changed, 78 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Add MT8192 vencsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-venc.c | 53 ++
3 files changed, 60 insertions(+)
create mode 100644
Add MT8192 vdecsys and vdecsys soc clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++
3 files changed, 101 insertions
This patch adds the new binding documentation of msdc controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,msdc.yaml | 46 ++
1 file changed, 46 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/mediatek
Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-ipe.c | 57 +++
3 files changed, 64 insertions(+)
create mode 100644
Add MT8192 audio clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-aud.c | 118 ++
3 files changed, 125 insertions(+)
create mode 100644
Add MT8192 msdc and msdc top clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-msdc.c | 85 ++
3 files changed, 92 insertions(+)
create mode
Add MT8192 mfgcfg clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-mfg.c | 50 +++
3 files changed, 57 insertions(+)
create mode 100644
Add MT8192 imgsys and imgsys2 clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-img.c | 70 +++
3 files changed, 77 insertions(+)
create mode
Most of subsystem clock providers only need to register clock gates
in their probe() function.
To reduce the duplicated code by add a generic function.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mtk.c | 23 +++
drivers/clk/mediatek/clk-mtk.h | 8
2 files
On Fri, 2020-11-27 at 13:42 +0100, Matthias Brugger wrote:
>
> On 19/11/2020 15:13, Enric Balletbo Serra wrote:
> > Hi Weiyi,
> >
> > Missatge de Weiyi Lu del dia dj., 19 de nov.
> > 2020 a les 14:10:
> >>
> >> On Thu, 2020-11-19 at 13:13 +
GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Power Domains Controller
> +
> +maintainers:
> + - Weiyi Lu
> + - Mat
On Thu, 2020-11-19 at 13:13 +0100, Enric Balletbo Serra wrote:
> Hi Weiyi,
>
> Thank you for the patch
>
> Missatge de Weiyi Lu del dia dj., 19 de nov.
> 2020 a les 11:48:
> >
> > Add power domains controller node for SoC mt8192
> >
> > Signed-off-
On Fri, 2020-10-30 at 12:36 +0100, Enric Balletbo i Serra wrote:
> From: Weiyi Lu
>
> Add the needed board data to support mt8192 SoC.
>
> Signed-off-by: Weiyi Lu
> Signed-off-by: Enric Balletbo i Serra
> ---
>
Hi Enric,
I've verified with my dts v3[1] on MT8192 E
Add power domains controller node for SoC mt8192
Signed-off-by: Weiyi Lu
---
Change in v3: None, just rebase dts onto v5.10-rc1 and
V4 of series "Add new driver for SCPSYS power domains controller"[1]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=374
On Wed, 2020-11-18 at 11:55 +0800, Ikjoon Jang wrote:
> On Mon, Nov 09, 2020 at 10:03:32AM +0800, Weiyi Lu wrote:
> > In fact, the en_mask is a combination of divider enable mask
> > and pll enable bit(bit0).
> > Before this patch, we enabled both divider mask and bit0 in pr
On Wed, 2020-11-18 at 10:41 +0800, Yingjoe Chen wrote:
> On Mon, 2020-11-09 at 10:03 +0800, Weiyi Lu wrote:
> > Add MT8192 imp i2c wrapper clock provider
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > drivers/clk/mediatek/Kconfig | 6 ++
&
mtk_clk_register_mux() should be a static function
Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mux.c | 2 +-
drivers/clk/mediatek/clk-mux.h | 4
2 files changed, 1 insertion(+), 5 deletions(-)
mtk_clk_register_mux() should be a static function
Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mux.c | 2 +-
drivers/clk/mediatek/clk-mux.h | 4
2 files changed, 1 insertion(+), 5 deletions(-)
On Mon, 2020-11-09 at 11:20 +0100, Greg KH wrote:
> On Mon, Nov 09, 2020 at 05:37:07PM +0800, Weiyi Lu wrote:
> > mtk_clk_register_mux() should be a static function
> >
> > Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
> > Cc:
>
mtk_clk_register_mux() should be a static function
Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
Cc:
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mux.c | 2 +-
drivers/clk/mediatek/clk-mux.h | 4
2 files changed, 1 insertion(+), 5 deletions(-)
On Wed, 2020-10-28 at 11:27 +0100, Fabien Parent wrote:
> Hi Weiyi,
>
> The clock driver for MT8167 has been merged in v5.10-rc1. Can you also
> apply the change to that driver.
> Thank you
>
> Fabien
>
Hi Fabien,
Done. update in v2.
Many thanks.
> On Fri, Oct 2
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt7622.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2701.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701.c
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6797.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6779.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt7629.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8135.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8135.c
b
:
- add patch for MT8167
Weiyi Lu (13):
clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701
clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712
clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765
clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779
clk
Because all pll data has been updated. We no longer allow
en_mask to be a combination of pll_en_bit and div_en_mask.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-pll.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6765.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6765.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8183.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8183.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8167.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8167.c
b/drivers
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8516.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8516.c
b/drivers/clk
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8173.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2712
patch series.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-pll.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f440f2cd..11ed5d1 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b
Add MT8192 audio clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-aud.c | 118 ++
3 files changed, 125 insertions(+)
create mode 100644
Add MT8192 imp i2c wrapper clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 119 +
3 files changed, 126 insertions
This patch adds the new binding documentation of imp i2c wrapper controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../arm/mediatek/mediatek,imp_iic_wrap.yaml| 78 ++
1 file changed, 78 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Add MT8192 mfgcfg clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-mfg.c | 50 +++
3 files changed, 57 insertions(+)
create mode 100644
Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-ipe.c | 57 +++
3 files changed, 64 insertions(+)
create mode 100644
Add MT8192 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt8192-clk.h | 592 +
1 file changed, 592 insertions(+)
create mode 100644 include/dt-bindings/clock/mt8192
This patch adds the new binding documentation of msdc controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,msdc.yaml | 46 ++
1 file changed, 46 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/mediatek
Add MT8192 mmsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile| 1 +
drivers/clk/mediatek/clk-mt8192-mm.c | 108 +++
3 files changed, 115 insertions(+)
create mode 100644 drivers
This patch adds the new binding documentation of mdpsys controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,mdpsys.yaml | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm
Add MT8192 vdecsys and vdecsys soc clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++
3 files changed, 101 insertions
Add MT8192 mdpsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-mdp.c | 82 +++
3 files changed, 89 insertions(+)
create mode 100644
Add MT8192 scp adsp clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 50 ++
3 files changed, 57 insertions(+)
create mode
This patch adds the new binding documentation of scp adsp controller
for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,scp-adsp.yaml | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm
Add MT8192 msdc and msdc top clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-msdc.c | 85 ++
3 files changed, 92 insertions(+)
create mode
changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC
Weiyi Lu (24):
dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c
wrapper controller
dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys
controller
Add MT8192 basic clock providers, include topckgen, apmixedsys,
infracfg and pericfg.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig |8 +
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8192.c | 1350 +
drivers/clk
Add MT8192 vencsys clock provider
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-venc.c | 53 ++
3 files changed, 60 insertions(+)
create mode 100644
infra_uart0 clock is the real one what uart0 uses as bus clock.
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index
Most of subsystem clock providers only need to register clock gates
in their probe() function.
To reduce the duplicated code by add a generic function.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mtk.c | 23 +++
drivers/clk/mediatek/clk-mtk.h | 8
2 files
Add MT8192 imgsys and imgsys2 clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-img.c | 70 +++
3 files changed, 77 insertions(+)
create mode
Add clock controller nodes for SoC mt8192
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++
1 file changed, 163 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index
This patch adds the binding documentation of topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks for Mediatek MT8192.
Signed-off-by: Weiyi Lu
---
.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm
Add MT8192 camsys and camsys raw clock providers
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8192-cam.c | 107 ++
3 files changed, 114 insertions(+)
create
.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mtk.h | 2 ++
drivers/clk/mediatek/clk-pll.c | 15 ++-
2 files changed
On Tue, 2020-10-27 at 11:53 +0100, Matthias Brugger wrote:
>
> On 26/10/2020 18:55, Enric Balletbo i Serra wrote:
> > From: Weiyi Lu
> >
> > For some power domain, like conn on MT8192, it should be default OFF.
> > Because the power on/off control relies the
On Mon, 2020-10-26 at 18:55 +0100, Enric Balletbo i Serra wrote:
> From: Matthias Brugger
>
> Bus protection will need to update more then one register
> in infracfg. Add support for several operations.
>
> Signed-off-by: Matthias Brugger
> Signed-off-by: Enric Balletbo i Serra
> ---
>
>
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6779.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6779.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2712
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6765.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6765.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8516.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8516.c
b/drivers/clk
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt6797.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c
b
This series is based on v5.9-rc1 and
[v4,09/34] clk: mediatek: Fix asymmetrical PLL enable and disable control[1]
in Mediatek MT8192 clock support series
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/1603370247-30437-10-git-send-email-weiyi...@mediatek.com/
Weiyi Lu (12):
clk
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt8135.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8135.c
b
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt7622.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c
b/drivers
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt7629.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk
Because all pll data has been updated. We no longer allow
en_mask is a combination of pll_en_bit and div_en_mask.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-pll.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers
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