* Kirill A. Shutemov wrote:
> > One other detail I noticed:
> >
> > /* Bound size of trampoline code */
> > .orglvl5_trampoline_src + LVL5_TRAMPOLINE_CODE_SIZE
> >
> > will this generate a build error if the trampoline code exceeds 0x40?
>
> Yes,
* Kirill A. Shutemov wrote:
> > One other detail I noticed:
> >
> > /* Bound size of trampoline code */
> > .orglvl5_trampoline_src + LVL5_TRAMPOLINE_CODE_SIZE
> >
> > will this generate a build error if the trampoline code exceeds 0x40?
>
> Yes, this is the point. Just a
On Fri, Nov 10, 2017 at 10:29:33AM +0100, Ingo Molnar wrote:
>
> * Kirill A. Shutemov wrote:
>
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > * The first step is go
On Fri, Nov 10, 2017 at 10:29:33AM +0100, Ingo Molnar wrote:
>
> * Kirill A. Shutemov wrote:
>
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > * The first step is go into compatibility mode.
> >
On Fri, Nov 10, 2017 at 10:28:12AM +0100, Ingo Molnar wrote:
>
> * Ingo Molnar wrote:
>
> > > --- a/arch/x86/boot/compressed/head_64.S
> > > +++ b/arch/x86/boot/compressed/head_64.S
> > > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > >* The first step is go into compatibility
On Fri, Nov 10, 2017 at 10:28:12AM +0100, Ingo Molnar wrote:
>
> * Ingo Molnar wrote:
>
> > > --- a/arch/x86/boot/compressed/head_64.S
> > > +++ b/arch/x86/boot/compressed/head_64.S
> > > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > >* The first step is go into compatibility mode.
> > >*/
On Fri, Nov 10, 2017 at 10:14:53AM +0100, Ingo Molnar wrote:
> I'm wondering, how did you test it if no current bootloader puts the kernel
> to
> above addresses of 4G?
I didn't test it directly.
I've checked with debugger that there's no memory accesses above 1M
between disabling paging in
On Fri, Nov 10, 2017 at 10:14:53AM +0100, Ingo Molnar wrote:
> I'm wondering, how did you test it if no current bootloader puts the kernel
> to
> above addresses of 4G?
I didn't test it directly.
I've checked with debugger that there's no memory accesses above 1M
between disabling paging in
* Kirill A. Shutemov wrote:
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -315,6 +315,18 @@ ENTRY(startup_64)
>* The first step is go into compatibility mode.
>*/
>
> + /*
> + * Find
* Kirill A. Shutemov wrote:
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -315,6 +315,18 @@ ENTRY(startup_64)
>* The first step is go into compatibility mode.
>*/
>
> + /*
> + * Find suitable place for trampoline and
* Ingo Molnar wrote:
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > * The first step is go into compatibility mode.
> > */
> >
> > + /*
> > +* Find suitable place for
* Ingo Molnar wrote:
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -315,6 +315,18 @@ ENTRY(startup_64)
> > * The first step is go into compatibility mode.
> > */
> >
> > + /*
> > +* Find suitable place for trampoline and
* Kirill A. Shutemov wrote:
> If bootloader enables 64-bit mode with 4-level paging, we need to
> switch over to 5-level paging. The switching requires disabling paging.
> It works fine if kernel itself is loaded below 4G.
>
> If bootloader put the kernel above
* Kirill A. Shutemov wrote:
> If bootloader enables 64-bit mode with 4-level paging, we need to
> switch over to 5-level paging. The switching requires disabling paging.
> It works fine if kernel itself is loaded below 4G.
>
> If bootloader put the kernel above 4G (not sure if anybody does
* Kirill A. Shutemov wrote:
> If bootloader enables 64-bit mode with 4-level paging, we need to
> switch over to 5-level paging. The switching requires disabling paging.
> It works fine if kernel itself is loaded below 4G.
>
> If bootloader put the kernel above
* Kirill A. Shutemov wrote:
> If bootloader enables 64-bit mode with 4-level paging, we need to
> switch over to 5-level paging. The switching requires disabling paging.
> It works fine if kernel itself is loaded below 4G.
>
> If bootloader put the kernel above 4G (not sure if anybody does
If bootloader enables 64-bit mode with 4-level paging, we need to
switch over to 5-level paging. The switching requires disabling paging.
It works fine if kernel itself is loaded below 4G.
If bootloader put the kernel above 4G (not sure if anybody does this),
we would loose control as soon as
If bootloader enables 64-bit mode with 4-level paging, we need to
switch over to 5-level paging. The switching requires disabling paging.
It works fine if kernel itself is loaded below 4G.
If bootloader put the kernel above 4G (not sure if anybody does this),
we would loose control as soon as
If bootloader enables 64-bit mode with 4-level paging, we need to
switch over to 5-level paging. The switching requires disabling paging.
It works fine if kernel itself is loaded below 4G.
If bootloader put the kernel above 4G (not sure if anybody does this),
we would loose control as soon as
If bootloader enables 64-bit mode with 4-level paging, we need to
switch over to 5-level paging. The switching requires disabling paging.
It works fine if kernel itself is loaded below 4G.
If bootloader put the kernel above 4G (not sure if anybody does this),
we would loose control as soon as
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