Re: [PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

Quoting Sergio Paracuellos (2021-04-09 22:50:56) > The documentation for this SOC only talks about two > registers regarding to the clocks: > * SYSC_REG_CPLL_CLKCFG0 - provides some information about > boostrapped refclock. PLL and dividers used for CPU and some > sort of BUS. > *

[PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or