[PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests

KVM enables perf for guest via counter virtualization. However, the sampling can not be supported as there is no mechanism to enabled trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot to provide the counter overflow data via the shared memory. In case of sampling event, the host

[PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature

PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is enabled, the hypervisor updates the shared memory with counter data and state of overflown counters. The guest can just read the shared memory instead of

[PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed

Currently, we return a linux error code if creating a perf event failed in kvm. That shouldn't be necessary as guest can continue to operate without perf profiling or profiling with firmware counters. Return appropriate SBI error code to indicate that PMU configuration failed. An error message in

[PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset

The virtual counter value is updated during pmu_ctr_read. There is no need to update it in reset case. Otherwise, it will be counted twice which is incorrect. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Reviewed-by: Andrew Jones

[PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name

SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kernel/paravirt.c | 6

[PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value

The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32

For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Signed-off-by: Atish Patra ---

[PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function

SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial values with one SBI call. These functionalities optimizes the number of traps to the higher

[PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions

SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel Acked-by: Palmer Dabbelt Signed-off-by: Atish Patra ---

[PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations

It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 20 ++-- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git

[PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter

SBI v2.0 introduced a explicit function to read the upper 32 bits for any firmware counter width that is longer than 32bits. This is only applicable for RV32 where firmware counter can be 64 bit. Reviewed-by: Andrew Jones Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley Reviewed-by: Anup

[PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition

SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Clément Léger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h |

[PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name

The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 2 +-

[PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest

This series implements SBI PMU improvements done in SBI v2.0[1] i.e. PMU snapshot and fw_read_hi() functions. SBI v2.0 introduced PMU snapshot feature which allows the SBI implementation to provide counter information (i.e. values/overflow status) via a shared memory between the SBI

Re: [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature

On 4/1/24 15:36, Atish Patra wrote: On Sat, Mar 2, 2024 at 1:49 AM Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:23PM -0800, Atish Patra wrote: PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is

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