[PATCH v8 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

set of tests if they want to. Suggested-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/riscv/sbi_pmu_test.c| 73 --- 1 file changed, 64 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing

[PATCH v8 23/24] KVM: riscv: selftests: Add a test for counter overflow

will fail on platform with virtualization but doesn't support overflow on these two events. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/riscv/sbi_pmu_test.c| 113 ++ 1 file changed, 113 insertions(+) diff --git a/tools

[PATCH v8 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality

Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 25

[PATCH v8 21/24] KVM: riscv: selftests: Add SBI PMU selftest

This test implements basic sanity test and cycle/instret event counting tests. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/riscv/sbi_pmu_test.c| 369 ++ 2

[PATCH v8 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions

The SBI PMU extension definition is required for upcoming SBI PMU selftests. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++ 1 file changed, 66 insertions(+) diff --git a/tools/testing

[PATCH v8 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test

The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v8 18/24] KVM: riscv: selftests: Add helper functions for extension checks

. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++ tools/testing/selftests/kvm/riscv/arch_timer.c| 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv

[PATCH v8 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file

The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/include/riscv/processor.h | 39 --- .../testing/selftests/kvm

[PATCH v8 16/24] RISC-V: KVM: Improve firmware counter read function

Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++- arch/riscv

[PATCH v8 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32

The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm

[PATCH v8 14/24] RISC-V: KVM: Add perf sampling support for guests

Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 3 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/aia.c | 5 ++ arch/riscv/kvm/vcpu.c | 15 -- arch/riscv/kvm

[PATCH v8 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature

of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c |

[PATCH v8 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed

in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files c

[PATCH v8 11/24] RISC-V: KVM: No need to update the counter value during reset

es Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cee1b9ca4ec4..b5159ce4592d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39

[PATCH v8 10/24] RISC-V: KVM: Fix the initial sample period value

The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1

[PATCH v8 09/24] drivers/perf: riscv: Implement SBI PMU snapshot function

ones Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu.c | 1 + drivers/perf/riscv_pmu_sbi.c | 265 ++--- include/linux/perf/riscv_pmu.h | 6 + 3 files changed, 255 insertions(+), 17 deletions(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_p

[PATCH v8 08/24] drivers/perf: riscv: Fix counter mask iteration for RV32

For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Reviewed-by: Andrew Jones Signed-off-by: Atish

[PATCH v8 07/24] RISC-V: Use the minor version mask while computing sbi version

. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index f31650b10899..112a0a0d9f46 100644 --- a/arch/riscv/include/asm/sbi.h

[PATCH v8 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name

SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 2 +- arch

[PATCH v8 05/24] RISC-V: Add SBI PMU snapshot definitions

-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6

[PATCH v8 04/24] drivers/perf: riscv: Use BIT macro for shifting operations

It is a good practice to use BIT() instead of (1 << x). Replace the current usages with BIT(). Take this opportunity to replace few (1UL << x) with BIT() as well for consistency. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/as

[PATCH v8 03/24] drivers/perf: riscv: Read upper bits of a firmware counter

Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3e44d2fb8bf8..1823ffb25d35 100644 --- a/drivers/perf/riscv_pmu_sbi.c

[PATCH v8 02/24] RISC-V: Add FIRMWARE_READ_HI definition

SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Andrew Jones Reviewed-by: Clément Léger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra

[PATCH v8 01/24] RISC-V: Fix the typo in Scountovf CSR name

The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by

[PATCH v8 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest

m RFC->v1: 1. Addressed all the comments on RFC series. 2. Removed PATCH2 and merged into later patches. 3. Added 2 more patches for minor fixes. 4. Fixed KVM boot issue without Ssaia and made sscofpmf in guest dependent on Ssaia in the host. Atish Patra (24): RISC-V: Fix the typo in Scountovf

Re: [PATCH v7 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function

On 4/16/24 21:02, Samuel Holland wrote: Hi Atish, On 2024-04-16 1:44 PM, Atish Patra wrote: SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial

[PATCH v7 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest

. 2. Removed PATCH2 and merged into later patches. 3. Added 2 more patches for minor fixes. 4. Fixed KVM boot issue without Ssaia and made sscofpmf in guest dependent on Ssaia in the host. Atish Patra (24): RISC-V: Fix the typo in Scountovf CSR name RISC-V: Add FIRMWARE_READ_HI definition drive

Re: [PATCH v6 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

On 4/15/24 06:43, Andrew Jones wrote: On Wed, Apr 10, 2024 at 05:07:52PM -0700, Atish Patra wrote: SBI PMU test comprises of multiple tests and user may want to run only a subset depending on the platform. The most common case would be to run all to validate all the tests. However, some

Re: [PATCH v6 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function

On 4/15/24 06:15, Andrew Jones wrote: On Wed, Apr 10, 2024 at 05:07:36PM -0700, Atish Patra wrote: SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial

Re: [PATCH v6 07/24] RISC-V: Use the minor version mask while computing sbi version

On 4/15/24 06:06, Andrew Jones wrote: On Wed, Apr 10, 2024 at 05:07:35PM -0700, Atish Patra wrote: As per the SBI specification, minor version is encoded in the lower 24 bits only. Make sure that the SBI version is computed with the appropriate mask. Currently, there is no minor version in use

[PATCH v6 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test

particular test if they want to. Suggested-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/riscv/sbi_pmu_test.c| 77 --- 1 file changed, 68 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing

[PATCH v6 23/24] KVM: riscv: selftests: Add a test for counter overflow

will fail on platform with virtualization but doesn't support overflow on these two events. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../selftests/kvm/riscv/sbi_pmu_test.c| 113 ++ 1 file changed, 113 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv

[PATCH v6 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality

Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 25

[PATCH v6 21/24] KVM: riscv: selftests: Add SBI PMU selftest

This test implements basic sanity test and cycle/instret event counting tests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/riscv/sbi_pmu_test.c| 369 ++ 2 files changed, 370 insertions

[PATCH v6 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions

The SBI PMU extension definition is required for upcoming SBI PMU selftests. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++ 1 file changed, 66 insertions(+) diff --git a/tools/testing

[PATCH v6 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test

The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v6 18/24] KVM: riscv: selftests: Add helper functions for extension checks

. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++ tools/testing/selftests/kvm/riscv/arch_timer.c| 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv

[PATCH v6 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file

The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/include/riscv/processor.h | 39 --- .../testing/selftests/kvm

[PATCH v6 16/24] RISC-V: KVM: Improve firmware counter read function

Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++- arch/riscv

[PATCH v6 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32

The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm

[PATCH v6 14/24] RISC-V: KVM: Add perf sampling support for guests

first sets the guest's LCOFI interrupt and injects to the guest via irq filtering mechanism defined in AIA specification. Thus, ssaia must be enabled in the host in order to use perf sampling in the guest. No other AIA dependency w.r.t kernel is required. Reviewed-by: Anup Patel Signed-off-by: Atish

[PATCH v6 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature

of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 121 +- arch/riscv

[PATCH v6 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed

in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files c

[PATCH v6 11/24] RISC-V: KVM: No need to update the counter value during reset

es Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cee1b9ca4ec4..b5159ce4592d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39

[PATCH v6 10/24] RISC-V: KVM: Fix the initial sample period value

The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1

[PATCH v6 09/24] drivers/perf: riscv: Fix counter mask iteration for RV32

For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Reviewed-by: Andrew Jones Signed-off-by: Atish

[PATCH v6 08/24] drivers/perf: riscv: Implement SBI PMU snapshot function

CSRs. In both modes, it does saves the number of ecalls while starting multiple counter together with an initial values. This is a likely scenario if multiple counters overflow at the same time. Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Signed-off-by: Atish P

[PATCH v6 07/24] RISC-V: Use the minor version mask while computing sbi version

. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index f31650b10899..935b082d6a6c 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm

[PATCH v6 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name

SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 2 +- arch

[PATCH v6 05/24] RISC-V: Add SBI PMU snapshot definitions

-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6

[PATCH v6 04/24] drivers/perf: riscv: Use BIT macro for shifting operations

It is a good practice to use BIT() instead of (1 << x). Replace the current usages with BIT(). Take this opportunity to replace few (1UL << x) with BIT() as well for consistency. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/as

[PATCH v6 03/24] drivers/perf: riscv: Read upper bits of a firmware counter

Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3e44d2fb8bf8..1823ffb25d35 100644 --- a/drivers/perf/riscv_pmu_sbi.c

[PATCH v6 02/24] RISC-V: Add FIRMWARE_READ_HI definition

SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Andrew Jones Reviewed-by: Clément Léger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra

[PATCH v6 01/24] RISC-V: Fix the typo in Scountovf CSR name

The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- ar

[PATCH v6 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest

patchwork CI. 2. Rebased on top of kvm-next. 3. Added Acked-by tags. Changes from RFC->v1: 1. Addressed all the comments on RFC series. 2. Removed PATCH2 and merged into later patches. 3. Added 2 more patches for minor fixes. 4. Fixed KVM boot issue without Ssaia and made sscofpmf in guest de

Re: [PATCH v4 07/15] RISC-V: KVM: No need to exit to the user space if perf event failed

On 4/4/24 05:16, Andrew Jones wrote: On Mon, Apr 01, 2024 at 03:37:01PM -0700, Atish Patra wrote: On Sat, Mar 2, 2024 at 12:16 AM Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:22PM -0800, Atish Patra wrote: Currently, we return a linux error code if creating a perf event failed in kvm

Re: [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function

On 4/4/24 04:52, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:35AM -0700, Atish Patra wrote: SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial

Re: [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality

On 4/10/24 00:10, Andrew Jones wrote: On Tue, Apr 09, 2024 at 03:52:40PM -0700, Atish Patra wrote: On 4/5/24 06:11, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:50AM -0700, Atish Patra wrote: ... + probe = guest_sbi_probe_extension(SBI_EXT_PMU, _val); + GUEST_ASSERT(probe

Re: [PATCH v4 09/15] RISC-V: KVM: Add perf sampling support for guests

On 4/5/24 05:05, Andrew Jones wrote: On Tue, Apr 02, 2024 at 01:33:10AM -0700, Atish Patra wrote: ... but it should be possible for the VMM to disable this extension in the guest. We just need to change all the checks in KVM of the host's ISA for RISCV_ISA_EXT_SSCOFPMF to checking the guest's

Re: [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow

On 4/5/24 06:23, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:51AM -0700, Atish Patra wrote: Add a test for verifying overflow interrupt. Currently, it relies on overflow support on cycle/instret events. This test works for cycle/ instret events which support sampling via hpmcounters

Re: [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality

On 4/5/24 06:11, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:50AM -0700, Atish Patra wrote: Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Anup Patel Signed-off-by: Atish

Re: [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest

On 4/5/24 05:50, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:49AM -0700, Atish Patra wrote: ... +static void test_pmu_basic_sanity(void) +{ + long out_val = 0; + bool probe; + struct sbiret ret; + int num_counters = 0, i; + union sbi_pmu_ctr_info ctrinfo

Re: [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature

On 4/5/24 04:23, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:41AM -0700, Atish Patra wrote: PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is enabled, the hypervisor updates the shared memory

Re: [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function

On 4/4/24 05:01, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:35AM -0700, Atish Patra wrote: ... +static int pmu_sbi_snapshot_disable(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1, + -1, 0, 0, 0, 0

Re: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations

On 4/4/24 04:08, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:33AM -0700, Atish Patra wrote: It is a good practice to use BIT() instead of (1UL << x). (1UL << x) isn't generally a problem. The problem is with (1 << x). Yes. That's why, the commit message said it's

Re: [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter

On 4/4/24 04:02, Andrew Jones wrote: On Wed, Apr 03, 2024 at 01:04:32AM -0700, Atish Patra wrote: SBI v2.0 introduced a explicit function to read the upper 32 bits for any firmware counter width that is longer than 32bits. This is only applicable for RV32 where firmware counter can be 64 bit

[PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow

will fail on platform with virtualization but doesn't support overflow on these two events. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../selftests/kvm/riscv/sbi_pmu_test.c| 114 ++ 1 file changed, 114 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv

[PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality

Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 25 .../selftests/kvm/lib/riscv

[PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest

This test implements basic sanity test and cycle/instret event counting tests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/riscv/sbi_pmu_test.c| 340 ++ 2 files changed, 341 insertions

[PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions

The SBI PMU extension definition is required for upcoming SBI PMU selftests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++ 1 file changed, 66 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv

[PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test

The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks

. Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++ tools/testing/selftests/kvm/riscv/arch_timer.c| 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing

[PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file

The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Signed-off-by: Atish Patra --- .../selftests/kvm/include/riscv/processor.h | 39 --- .../testing/selftests/kvm/include/riscv/sbi.h | 50

[PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function

Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++- arch/riscv/kvm/vcpu_sbi_pmu.c

[PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32

The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm/vcpu_pmu.c | 44

[PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests

first sets the guest's LCOFI interrupt and injects to the guest via irq filtering mechanism defined in AIA specification. Thus, ssaia must be enabled in the host in order to use perf sampling in the guest. No other AIA dependency w.r.t kernel is required. Reviewed-by: Anup Patel Signed-off-by: Atish

[PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature

of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 121 +- arch/riscv

[PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed

in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files c

[PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset

es Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cee1b9ca4ec4..b5159ce4592d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39

[PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name

SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kernel/paravirt.c | 6

[PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value

The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32

For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Signed-off-by: Atish Patra --- drivers/perf

[PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function

CSRs. In both modes, it does saves the number of ecalls while starting multiple counter together with an initial values. This is a likely scenario if multiple counters overflow at the same time. Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Signed-off-by: Atish P

[PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions

SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel Acked-by: Palmer Dabbelt Signed-off-by: Atish Patra

[PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations

It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 20 ++-- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git

[PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter

Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 - 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3e44d2fb8bf8..babf1b9a4dbe 100644 --- a/drivers/perf/riscv_pmu_sbi.c

[PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition

SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Clément Léger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h

[PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name

The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- ar

[PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest

thout Ssaia and made sscofpmf in guest dependent on Ssaia in the host. Atish Patra (22): RISC-V: Fix the typo in Scountovf CSR name RISC-V: Add FIRMWARE_READ_HI definition drivers/perf: riscv: Read upper bits of a firmware counter drivers/perf: riscv: Use BIT macro for shifting operations

Re: [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature

On 4/1/24 15:36, Atish Patra wrote: On Sat, Mar 2, 2024 at 1:49 AM Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:23PM -0800, Atish Patra wrote: PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature

Re: [PATCH v4 12/15] KVM: riscv: selftests: Add SBI PMU extension definitions

On 3/2/24 03:00, Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:27PM -0800, Atish Patra wrote: The SBI PMU extension definition is required for upcoming SBI PMU selftests. Signed-off-by: Atish Patra --- .../selftests/kvm/include/riscv/processor.h | 67 +++ 1 file

Re: [PATCH v4 15/15] KVM: riscv: selftests: Add a test for counter overflow

On 3/2/24 04:35, Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:30PM -0800, Atish Patra wrote: Add a test for verifying overflow interrupt. Currently, it relies on overflow support on cycle/instret events. This test works for cycle/ instret events which support sampling via hpmcounters

Re: [PATCH v4 14/15] KVM: riscv: selftests: Add a test for PMU snapshot functionality

On 3/2/24 04:13, Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:29PM -0800, Atish Patra wrote: Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Signed-off-by: Atish Patra

Re: [PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest

On Sat, Mar 2, 2024 at 3:52 AM Andrew Jones wrote: > > On Wed, Feb 28, 2024 at 05:01:28PM -0800, Atish Patra wrote: > > This test implements basic sanity test and cycle/instret event > > counting tests. > > > > Signed-off-by: Atish Patra > > --- >

Re: [PATCH v4 09/15] RISC-V: KVM: Add perf sampling support for guests

On 3/2/24 02:33, Andrew Jones wrote: On Wed, Feb 28, 2024 at 05:01:24PM -0800, Atish Patra wrote: KVM enables perf for guest via counter virtualization. However, the sampling can not be supported as there is no mechanism to enabled trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot

Re: [PATCH v4 10/15] RISC-V: KVM: Support 64 bit firmware counters on RV32

On Sat, Mar 2, 2024 at 2:52 AM Andrew Jones wrote: > > On Wed, Feb 28, 2024 at 05:01:25PM -0800, Atish Patra wrote: > > The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware > > counters for RV32 based systems. > > > > Add infrastructure to support t

Re: [PATCH v4 07/15] RISC-V: KVM: No need to exit to the user space if perf event failed

On Sat, Mar 2, 2024 at 12:16 AM Andrew Jones wrote: > > On Wed, Feb 28, 2024 at 05:01:22PM -0800, Atish Patra wrote: > > Currently, we return a linux error code if creating a perf event failed > > in kvm. That shouldn't be necessary as guest can continue to operate > >

Re: [PATCH v4 08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature

On Sat, Mar 2, 2024 at 1:49 AM Andrew Jones wrote: > > On Wed, Feb 28, 2024 at 05:01:23PM -0800, Atish Patra wrote: > > PMU Snapshot function allows to minimize the number of traps when the > > guest access configures/access the hpmcounters. If the snapshot feature > > is

[PATCH v4 15/15] KVM: riscv: selftests: Add a test for counter overflow

will fail on platform with virtualization but doesn't support overflow on these two events. Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/sbi_pmu.c | 126 +++- 1 file changed, 125 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu.c

[PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest

This test implements basic sanity test and cycle/instret event counting tests. Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile| 1 + tools/testing/selftests/kvm/riscv/sbi_pmu.c | 340 2 files changed, 341 insertions(+) create mode 100644 tools

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