Re: [PATCH v3 06/29] riscv: zicfiss / zicfilp extension csr and bit definitions

On Wed, Apr 03, 2024 at 04:34:54PM -0700, Deepak Gupta wrote: > zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. > menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS > while senvcfg controls enabling for U/VU mode. > > zicfilp extension extends

[PATCH v3 06/29] riscv: zicfiss / zicfilp extension csr and bit definitions

zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur