On Thu, 19 May 2011 17:58:56 -0700
Steve Calfee stevecal...@gmail.com wrote:
I also tried to get as close as I could to the soc/omap/omap3pandora.c
machine driver with my omap3beaglexm.c machine driver. Specifically in
the *_hw_params init routines.
But when I start things up (even
On Friday 20 May 2011 02:58:30 Steve Calfee wrote:
On 05/19/11 04:28, Peter Ujfalusi wrote:
Correct, I can set bit clock to 64*lrclk, 48*lrclk, 128*lrclk, 17*lrclk,
and 18*lrclk.
Strange, that there is no option for 32*lrclk.
The audio folks here think that it is normal to send more
than
Hi,
On Friday 20 May 2011 09:29:11 Jarkko Nikula wrote:
This very likely sounds that in master mode the master clock to McBSP is
missing if there is no DMA running.
If the clock setup is correct for McBSP, than it runs the clocks, and shifts
out data.
Did you try to use internal 96 MHz
On Thu, May 19, 2011 at 21:41, Kevin Hilman khil...@ti.com wrote:
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
From: Charulatha V ch...@ti.com
Reset GPIO (OMAP_GPIO_152) for QUART in zoom2/zoom3 debug-board is
not requested at all. This would lead to problems if this GPIO is
wrongly
Kevin,
Thanks for the comments.
On Thu, May 19, 2011 at 22:09, Kevin Hilman khil...@ti.com wrote:
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
From: Charulatha V ch...@ti.com
gpio_bank_count is the count of number of GPIO devices
in a SoC. Remove this dependency from the driver. Also
Kevin,
On Thu, May 19, 2011 at 21:29, Kevin Hilman khil...@ti.com wrote:
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
From: Charulatha V ch...@ti.com
Use USHRT_MAX for revision offset instead of -1 if revision register
is not available for a given SoC since rev offset is a u16 value.
Tarun,
On Mon, May 16, 2011 at 17:11, Tarun Kanti DebBarma tarun.ka...@ti.com wrote:
Since wake_status, wake_clear, wake_set is common for all banks on a given
OMAP version it is enough to get their values once during probe().
Also, register offsets are already initialzed according to OMAP
Varadarajan, Charulatha ch...@ti.com writes:
Kevin,
On Thu, May 19, 2011 at 21:29, Kevin Hilman khil...@ti.com wrote:
Tarun Kanti DebBarma tarun.ka...@ti.com writes:
From: Charulatha V ch...@ti.com
Use USHRT_MAX for revision offset instead of -1 if revision register
is not available for
The USB enable GPIO has been inverted and the USER button moved.
Signed-off-by: Koen Kooi k...@dominion.thruhere.net
---
arch/arm/mach-omap2/board-omap3beagle.c | 26 +-
1 files changed, 21 insertions(+), 5 deletions(-)
diff --git
From: Koen Kooi k...@dominion.thruhere.net
The USB enable GPIO has been inverted and the USER button moved.
Signed-off-by: Koen Kooi k...@dominion.thruhere.net
---
Changes since v1:
Fixed more xM references
arch/arm/mach-omap2/board-omap3beagle.c | 32 +++---
Drat, I had a git add -i fail, ignore this one.
Op 20 mei 2011, om 12:50 heeft Koen Kooi het volgende geschreven:
The USB enable GPIO has been inverted and the USER button moved.
Signed-off-by: Koen Kooi k...@dominion.thruhere.net
---
arch/arm/mach-omap2/board-omap3beagle.c | 26
On Fri, May 13, 2011 at 01:27, Shweta Gulati shweta.gul...@ti.com wrote:
[...]
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3cd91ac..b1b11de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++
TWL6030: regulator is enabled/disabled via VREG_STATE
Resetting VREG_GRP is not needed to disable it.
TWL4030: regulator is enabled/disabled via VREG_GRP
Since there is nothing common, split twlreg_enable similar to other
regulator_ops
Balaji T K (2):
regulator: twl6030: do not write to _GRP
TWL6030: regulator is enabled via VREG_STATE
TWL4030: regulator is enabled via VREG_GRP
Since there is nothing common, split twlreg_enable similar to other
regulator_ops
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/regulator/twl-regulator.c | 39 +++-
TWL6030: regulator is disabled via VREG_STATE
TWL4030: regulator is disabled via VREG_GRP
Since there is nothing common, split twlreg_enable similar to other
regulator_ops
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/regulator/twl-regulator.c | 47 +---
Move OMAP GPIO driver to drivers/gpio, but leave OMAP-specific
register definitions in plat/gpio.h, where they will be used by
SoC-specific code and passed in via platform_data (in forthcoming
series.)
After the move, I have another series that cleans up this
driver, removing all the SoC-specific
Register offset defines are moved to plat/gpio.h so they can be used
by SoC-specific device init code to fill out platform_data register
offsets.
Signed-off-by: Kevin Hilman khil...@ti.com
---
arch/arm/plat-omap/gpio.c | 103
Hi Shweta,
On 5/13/2011 8:27 AM, Gulati, Shweta wrote:
To set sr ntarget values for all volt_domain,
volt_table is retrieved by doing a look_up of 'vdd_name'
field from omap_hwmod but voltage domain pointer does not
belong to omap_hwmod and is not used anywhere else.
As a part of voltage layer
From: Charulatha V ch...@ti.com
Reset GPIO (OMAP_GPIO_152) for QUART in zoom2/zoom3 debug-board is
not requested at all. This would lead to problems if this GPIO is
wrongly requested. Hence request OMAP GPIO 152 for QUART RESET but
do not apply a reset pulse as it would reset QUART and
disturb
On Thu, May 19, 2011 at 12:02 AM, Graeme Gregory g...@slimlogic.co.uk wrote:
Adding support for the twl6025. Major difference in the twl6025 is the
group functionality has been removed from the chip so this affects how
regulators are enabled and disabled.
The names of the regulators also
On Wed, May 18, 2011 at 09:55:42PM +0530, Avinash.H.M. wrote:
On Wed, May 18, 2011 at 10:22:28AM -0600, Paul Walmsley wrote:
On Mon, 9 May 2011, Avinash.H.M. wrote:
On Thu, May 05, 2011 at 03:58:56PM -0600, Paul Walmsley wrote:
The patch is based on
*
Start moving SoC-specific register handling out of the driver by passing
in register offsets in via platform data.
Also, move OMAP1 MPUIO IRQ handling over to genric IRQ chip.
Applies on top of Tony's for-next branch (which include's the generic
IRQ chip work from tglx) and the OMAP GPIO driver
Remove the OMAP1 #ifdef and MPUIO special case for _clear_gpio_irqbank()
The MPUIOs do not need a register access to ack/clear the IRQ status,
since reading the IRQ status clears it. In addition, the MPUIO
irq_chip has an empty ack method, so _clear_gpio_irqbank() is never
used for MPUIOs.
In commit 78a1a6d3411de1a8b0dc1cb92754b5f12f251912 (ARM: OMAP4: Update
the GPIO support) braces were mistakenly added to included the
register read-back inside the cpu_is_* checking.
Remove the braces, ensuring that a register read-back is done, even
when the IRQSTATUS2 register is not written.
Replace hard-coded mask values with bank-width which is already coming
from platform_data.
Signed-off-by: Kevin Hilman khil...@ti.com
---
drivers/gpio/gpio_omap.c |8 +---
1 files changed, 1 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio_omap.c b/drivers/gpio/gpio_omap.c
Rather than having a file-global bank_width variable, move it into
struct gpio_bank so it can be bank-specific. Note the bank width
is already passed per-bank via platform_data, so current code would
be incorrect if any banks had different width.
Signed-off-by: Kevin Hilman khil...@ti.com
---
The get_gpio_index() function, littered with cpu_is_* checks can be easily
replaced by using bitops based on the GPIO bank width. Do so.
Signed-off-by: Kevin Hilman khil...@ti.com
---
drivers/gpio/gpio_omap.c | 42 +-
1 files changed, 17 insertions(+),
From: Charulatha V ch...@ti.com
use chip info to get the pointer to the struct gpio_bank for a
given GPIO bank and remove get_gpio_bank().
Signed-off-by: Charulatha V ch...@ti.com
---
drivers/gpio/gpio_omap.c | 29 ++---
1 files changed, 2 insertions(+), 27
Add register offset fields to GPIO platform_data for registers.
This patch adds registers that control direction, input and output
data. Using these register offsets in the common driver allows
removal of #ifdefs and greatly improves readability.
Also create dedicated data out functions: one
Cleanup GPIO IRQ enable/disable handling by removing SoC-specific
Also split enable/disable IRQ into separate functions for better
readability and also facilitate potentially moving to generic irq_chip
in the future.
Signed-off-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap1/gpio15xx.c
MPUIO banks have their own dedicated IRQ chip interface, separate from
the normal GPIO banks. Convert the MPUIO IRQ chip over to using
the new generic IRQ chip interface.
Signed-off-by: Kevin Hilman khil...@ti.com
---
drivers/gpio/gpio_omap.c | 74
These functions are useless. They are only called in a few places,
and where they are called, the GPIO has already been converted from an
IRQ or masked, so these functions will never fail.
Signed-off-by: Kevin Hilman khil...@ti.com
---
drivers/gpio/gpio_omap.c | 45
Make _set_gpio_wakeup() generic by removing ifdefs. Code for the
various SoCs/bank-methods was already the same, except for the
non-wakeup GPIO checking. But that flag is set on a per-SoC basis, so
can be used for all SoCs.
While here, use dev_err() and remove GPIO bank calculation assumption
Use register offsets passed in from pdata for accessing debounce registers.
Signed-off-by: Kevin Hilman khil...@ti.com
---
arch/arm/mach-omap2/gpio.c |4
arch/arm/plat-omap/include/plat/gpio.h |2 ++
drivers/gpio/gpio_omap.c | 15 +++
3 files
Remove cpu_is_* checks from gpio_show_revision() by passing in the
revision address offset from platform data. SoCs with no revision
register (15xx, 7xx, and all MPUIOs) use -1 (actually, USHRT_MAX) to
signify no register.
While here, all GPIO banks are assumed to be the same revision, so fix
-Original Message-
From: Menon, Nishanth
Sent: Thursday, May 19, 2011 7:28 PM
To: Premi, Sanjeev
Cc: Hilman, Kevin; linux-omap@vger.kernel.org
Subject: Re: [PATCH] omap:pm: Fix boot-time errors with
debugfs disabled
On Thu, May 19, 2011 at 05:30, Premi, Sanjeev pr...@ti.com
Tony,
Please pull the following OMAP PM related cleanups for 2.6.40.
Thanks,
Kevin
The following changes since commit 61c4f2c81c61f73549928dfd9f3e8f26aa36a8cf:
Linux 2.6.39 (2011-05-18 21:06:34 -0700)
are available in the git repository at:
On Fri, May 20, 2011 at 08:32:17PM +0530, Avinash.H.M. wrote:
On Wed, May 18, 2011 at 09:55:42PM +0530, Avinash.H.M. wrote:
On Wed, May 18, 2011 at 10:22:28AM -0600, Paul Walmsley wrote:
On Mon, 9 May 2011, Avinash.H.M. wrote:
On Thu, May 05, 2011 at 03:58:56PM -0600, Paul Walmsley
The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
special sequence to reset the module. The sequence is
- Disable the I2C.
- Write to SOFTRESET bit.
- Enable the I2C.
- Poll on the RESETDONE bit.
The sequence is implemented as a function and the i2c_class is updated
As a result of c42321c (genirq: Make generic irq chip depend on
CONFIG_GENERIC_IRQ_CHIP), we now need those platforms using this in
my tree to select this symbol.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
--
Please send acks ASAP. Thanks to Mark for pointing this out with a patch
On Fri, 20 May 2011, Russell King - ARM Linux wrote:
As a result of c42321c (genirq: Make generic irq chip depend on
CONFIG_GENERIC_IRQ_CHIP), we now need those platforms using this in
my tree to select this symbol.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
--
Please send
On Fri, 20 May 2011, Russell King - ARM Linux wrote:
As a result of c42321c (genirq: Make generic irq chip depend on
CONFIG_GENERIC_IRQ_CHIP), we now need those platforms using this in
my tree to select this symbol.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
--
Please send
On 05/19/11 23:29, Jarkko Nikula wrote:
On Thu, 19 May 2011 17:58:56 -0700
Steve Calfee stevecal...@gmail.com wrote:
...
This very likely sounds that in master mode the master clock to McBSP is
missing if there is no DMA running. Did you try to use internal 96 MHz
from my example or did
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