ed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Changes in v5:
- no change
Changes in v4:
- Modify the codes according to the definition of this property.
Changes in v3:
- add new property for INCR burst in usb node to reset GSBUSC
e enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platforms:
around 3% improvement (from 364MB/s to 375MB/s).
Signed-off-by: Changming Huang <jerry.hu...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Changes
From: Changming Huang <jerry.hu...@nxp.com>
Add the macro definition for global soc bus configuration register 0/1
Signed-off-by: Changming Huang <jerry.hu...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Changes in v5:
- no change
Changes in v4:
- no ch
Enable USB3 HW LPM feature for ls1021a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff
Enable USB3 HW LPM feature for ls1043a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |6 ++
1 files changed, 6 insertions
Enable USB3 HW LPM feature for ls1046a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |6 ++
1 files changed, 6 insertions
.
3. After U3 entry, re-enable the U2 timer by programming PORTPMSC
with the value saved in Step 1.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
drivers/usb/host/xhci-hub.c | 22 ++
drivers/usb/host/xhci-plat.c |6 +-
drivers/usb/host/xhci.h |1 +
Hi Balbi,
> -Original Message-
> From: Felipe Balbi [mailto:ba...@kernel.org]
> Sent: Wednesday, November 15, 2017 4:52 PM
> To: Ran Wang <ran.wan...@nxp.com>
> Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>; open
> list:DESIGNWARE USB3 DRD IP DRIVER <
Add support for USB3 snooping by asserting bits
in register DWC3_GSBUSCFG0 for data and descriptor.
Signed-off-by: Changming Huang <jerry.hu...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
drivers/us
This patch adds entries in dts to enable USB 3.0 PHY driver.
Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v2:
- Rename node name from 'usb3-phy' to 'usb-phy'
- Adjust phy node position
arch/arm64/boot/d
Adds entry point at dwc3 core init function to enable
USB 3.0 PHY driver.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v2:
- New file
drivers/usb/dwc3/core.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/us
Adds qoriq usb 3.0 phy driver to implement erratum related workaround
for qoriq SoC.
Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v2:
- Replace funciont __raw_writel() by iowrite32be()
- Remove qoriq_u
Hi Oliver
> -Original Message-
> From: Oliver Neukum [mailto:oneu...@suse.com]
> Sent: Monday, October 23, 2017 6:56 PM
> To: Ran Wang <ran.wan...@nxp.com>
> Cc: David S . Miller <da...@davemloft.net>; hayeswang
> <hayesw...@realtek.com>; linu
This product is named 'TP-LINK USB 3.0 Gigabit Ethernet Network
Adapter (Model No.is UE300)'. It uses chip RTL8153 and works with
driver drivers/net/usb/r8152.c
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
drivers/net/usb/cdc_ether.c | 8
drivers/net/usb/r8152.c | 2 ++
2
requests from the host/hub and enter
low power.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core.c| 2 ++
drivers/usb/dwc3/core.h| 2 ++
drivers/usb/dwc3
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