[PATCH] xhci: Workaround to get Intel xHCI reset working more reliably

From: Rajmohan Mani <rajmohan.m...@intel.com> Existing Intel xHCI controllers require a delay of 1 mS, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this

[PATCH] xhci: Workaround to get D3 working in Intel xHCI

From: Rajmohan Mani rajmohan.m...@intel.com The xHCI in Intel CherryView / Braswell Platform requires a driver workaround to get xHCI D3 working. Without this workaround, xHCI might not enter D3. Workaround is to configure SSIC PORT as unused before D3 entry and used after D3 exit. This is done