Hi,
On Wed, 2013-07-24 at 15:22 +0300, Felipe Balbi wrote:
On Mon, Jun 24, 2013 at 06:27:44PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Cc: Felipe Balbi ba...@ti.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: linux-usb@vger.kernel.org
Cc
Hi,
On Wed, 2013-07-24 at 15:38 +0300, Felipe Balbi wrote:
Hi,
On Tue, Jul 09, 2013 at 06:47:08PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Use managed device resources to clean up the probe/remove
and get DT support for free.
Signed-off-by: Ivan T
On Wed, 2013-07-24 at 15:39 +0300, Felipe Balbi wrote:
On Tue, Jul 09, 2013 at 06:47:09PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch move global regulators variables to driver state
structire and move allocation of the regulators to be devm managed
From: Ivan T. Ivanov iiva...@mm-sol.com
When deferred probe happens driver will try to ioremap multiple times
and will fail. Memory resource.start variable is a global variable,
modifications in this field will be accumulated on every probe.
Fix this by moving the above operations after driver
On Thu, 2013-07-25 at 21:21 +0400, Sergei Shtylyov wrote:
On 07/25/2013 08:26 PM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
When deferred probe happens driver will try to ioremap multiple times
and will fail. Memory resource.start variable is a global variable
Hi,
On Fri, 2013-07-26 at 02:06 +, Paul Zimmerman wrote:
From: Felipe Balbi [mailto:ba...@ti.com]
Sent: Thursday, July 25, 2013 1:52 PM
On Thu, Jul 25, 2013 at 07:46:58PM +, Paul Zimmerman wrote:
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index
On Fri, 2013-07-26 at 23:28 +0300, Felipe Balbi wrote:
On Fri, Jul 26, 2013 at 03:31:34PM +0300, Ivan T. Ivanov wrote:
Hi Felipe,
On Thu, 2013-07-25 at 16:43 +0300, Ivan T. Ivanov wrote:
On Wed, 2013-07-24 at 15:39 +0300, Felipe Balbi wrote:
On Tue, Jul 09, 2013 at 06:47:09PM
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 82 -
include/linux/usb/msm_hsusb.h |3 ++
2 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/drivers/usb/phy
From: Ivan T. Ivanov iiva...@mm-sol.com
Whether regulators are available or not is checked at driver
probe. If they are not available driver will refuse to load,
so no need to check them again.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 10
From: Ivan T. Ivanov iiva...@mm-sol.com
v2
--
* Fix compilation issue in patch 1
* Separate regulator changes
* Merge devm_ related changes to one commit
* Drop Lindent patch
v1
--
Following patches make initial cleanup of usb phy found in the Qualcomm
chipsets. Changes include:
* Build time
From: Ivan T. Ivanov iiva...@mm-sol.com
This fixes checkpatch.pl warnings.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 33 +++--
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b
From: Ivan T. Ivanov iiva...@mm-sol.com
Move memory, regulators, clocks and irq allocation to
devm_* variants. Properly check for valid clk handles.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 188 -
1 file
From: Ivan T. Ivanov iiva...@mm-sol.com
This fixes checkpatch.pl warnings.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch fix compilation error and is an intermediate step
before the addition of DeviceTree support for newer targets.
Fix suggested here: https://lkml.org/lkml/2013/6/19/381
Cc: David Brown dav...@codeaurora.org
Cc: Daniel Walker dwal...@fifo99.com
Cc
From: Ivan T. Ivanov iiva...@mm-sol.com
When deferred probe happens driver will try to ioremap multiple times
and will fail. Memory resource.start variable is a global variable,
modifications in this field will be accumulated on every probe.
Fix this by moving the above operations after driver
Hi,
Cc: Bryan Huntsman bry...@codeaurora.org
Cc: Felipe Balbi ba...@ti.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
These patches add basic support for USB3.0 controllers found on
MSM platforms. First patch add 2 USB PHY drivers and second one
add support for Qualcomm wrapper IP over DWC3 controller. Patches
are just skeletons, no power management.
DWC3 IP
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 39 +
drivers/usb/dwc3/Kconfig |8 +
drivers/usb/dwc3/Makefile |1 +
drivers/usb/dwc3
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 49 +++
drivers/usb/phy/Kconfig| 11 +
drivers/usb/phy/Makefile |2 +
drivers/usb/phy
Hi,
On Tue, 2013-08-06 at 13:12 +0100, Pawel Moll wrote:
On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
I am sure that the information in the subject is more than enough for
you
On Tue, 2013-08-06 at 13:21 +0100, Pawel Moll wrote:
On Tue, 2013-08-06 at 12:53 +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
The same comment as for the RFC 1/2 here...
Will fix this.
.../devicetree
Hi,
On Tue, 2013-08-06 at 15:03 +0100, Mark Rutland wrote:
On Tue, Aug 06, 2013 at 12:53:10PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-ssusb.txt | 49
Hi,
On Tue, 2013-08-06 at 15:07 +0100, Mark Rutland wrote:
On Tue, Aug 06, 2013 at 12:53:11PM +0100, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
What does the glue layer do? Is it an actual piece of hardware, or
just some platform-specific code?
It is hardware layer
On Tue, 2013-08-06 at 16:15 +0100, Pawel Moll wrote:
On Tue, 2013-08-06 at 14:46 +0100, Ivan T. Ivanov wrote:
+ reg = 0xf920 0xcd00;
+ interrupts = 0 131 0;
+ interrupt-names = irq;
+ usb
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
Changes since first version:
* Split devicetree bindings description file to separate patch
* Address comments
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP (SNPS)
and HS, SS PHY's controll and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers
Hi,
On Fri, 2013-08-09 at 16:32 +0300, Felipe Balbi wrote:
On Fri, Aug 09, 2013 at 12:53:47PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
Hi,
On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
Hi,
On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
new file mode 100644
index 000..e509abc
--- /dev/null
+++ b/drivers/usb/dwc3
Hi,
On Mon, 2013-07-29 at 15:25 +0300, Felipe Balbi wrote:
Hi,
On Mon, Jul 29, 2013 at 10:04:21AM +0300, Ivan T. Ivanov wrote:
motg-irq = platform_get_irq(pdev, 0);
- if (!motg-irq) {
+ if (motg-irq 0) {
looks like this particular hunk isn't part of $subject.
Indeed
Hi,
On Mon, 2013-08-12 at 13:04 -0500, Felipe Balbi wrote:
On Fri, Aug 09, 2013 at 10:31:58AM -0500, Kumar Gala wrote:
On Aug 9, 2013, at 4:53 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP (SNPS)
probably
Hi,
On Tue, 2013-08-13 at 13:57 -0600, Stephen Warren wrote:
On 08/09/2013 03:53 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP (SNPS)
and HS, SS PHY's controll and configuration registers.
s/controll/control/
Thanks
Hi,
On Mon, 2013-08-12 at 13:24 -0500, Felipe Balbi wrote:
On Fri, Aug 09, 2013 at 07:09:18PM +0300, Ivan T. Ivanov wrote:
Hi,
On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
Hi,
On Tue, Aug 06, 2013 at 02:53:11PM +0300, Ivan T. Ivanov wrote:
diff --git a/drivers
Hi,
On Fri, 2013-08-09 at 16:23 +0300, Felipe Balbi wrote:
snip
+ /*
+* DWC3 Core requires its CORE CLK (aka master / bus clk) to
+* run at 125Mhz in SSUSB mode and 60MHZ for HSUSB mode.
+*/
+ clk_set_rate(mdwc-core_clk, 12500);
if this is dwc3's core clock,
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
These patches add basic support for USB3.0 controllers found
on MSM platforms. USB3.0 core is based on Synopsys DesignWare
SuperSpeed IP.
Changes since v2:
* Several improvements in devicetree bindings description
* Disable regulators in glue layer
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers
Hi,
On Wed, 2013-08-14 at 09:20 -0500, Josh Cartwright wrote:
On Wed, Aug 14, 2013 at 03:59:42PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
On Wed, 2013-08-14 at 09:06 -0700, Stephen Boyd wrote:
On 08/14/13 05:59, Ivan T. Ivanov wrote:
+}
+
+static const struct of_device_id of_dwc3_matach[] = {
match? Maybe you can make it all one line too { .compatible = qcom,dwc3 }
Thanks. Will do.
Ivan
Hi,
On Fri, 2013-08-16 at 16:44 -0600, Stephen Warren wrote:
On 08/14/2013 06:59 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
Here is fourth version of MSM USB3 drivers patches.
Changes since v3:
* Remove _clk suffix from clock names
* Clarify required child node for qcom,dwc3
* Fix comments in functions headers
* Use dbg instead err in drivers probe functions.
Changes
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers
Hi,
On Tue, 2013-08-20 at 07:29 -0500, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
Hi,
On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote:
On Tue, Aug 20, 2013 at 12:56:04PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control
Hi,
On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote:
On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-20 at 08:37 -0500, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 04:32:23PM +0300, Ivan T. Ivanov wrote:
On Tue, Aug 20, 2013
On Tue, 2013-08-20 at 10:01 -0500, Kumar Gala wrote:
On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote:
On Tue, Aug 20, 2013 at 05:09:11PM +0300, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-20 at 08:37 -0500, Felipe
On Tue, 2013-08-20 at 18:01 +0100, Pawel Moll wrote:
On Tue, 2013-08-20 at 16:06 +0100, Pawel Moll wrote:
On Tue, 2013-08-20 at 16:01 +0100, Kumar Gala wrote:
On Aug 20, 2013, at 9:54 AM, Ivan T. Ivanov wrote:
Hi,
On Tue, 2013-08-20 at 09:33 -0500, Felipe Balbi wrote
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
Here is fifth version of MSM USB3 drivers patches.
Changes since v4:
* Substitute references to wc3 with just dw in USB PHY drivers and
file names. This is to indicate that the PHY's are DesignWare, but
not necessarily related to DWC3 IP core
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers
On Thu, 2013-08-22 at 15:41 -0500, Felipe Balbi wrote:
On Wed, Aug 21, 2013 at 10:13:28AM -0500, Kumar Gala wrote:
On Aug 21, 2013, at 8:06 AM, Ivan T. Ivanov wrote:
On Tue, 2013-08-20 at 18:01 +0100, Pawel Moll wrote:
On Tue, 2013-08-20 at 16:06 +0100, Pawel Moll wrote:
On Tue
Hi, I am sorry for delay answer.
On Thu, 2013-09-26 at 10:46 +0100, Mark Rutland wrote:
On Mon, Sep 23, 2013 at 08:31:48PM +0100, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 12:56:03PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core
Hi,
On Mon, 2013-09-23 at 14:31 -0500, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 12:56:03PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
Hi,
On Mon, 2013-09-23 at 16:03 -0600, Stephen Warren wrote:
On 09/23/2013 01:32 PM, Felipe Balbi wrote:
Hi,
On Wed, Aug 21, 2013 at 04:29:44PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys (SNPS
Hi,
On Mon, 2013-09-23 at 14:32 -0500, Felipe Balbi wrote:
Hi,
On Wed, Aug 21, 2013 at 04:29:44PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Acked
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
This is sixth version of MSM USB3 drivers patches.
Changes since v5:
* devicetree bindings descriptions fixes
* Fixed NULL pointer dereferences in dev_prink's
* Removed extra space in sleep clock name
Changes since v4:
* Substitute references
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/dwc3
Hi Felipe,
On Fri, 2013-10-04 at 09:31 -0500, Felipe Balbi wrote:
On Wed, Aug 21, 2013 at 04:29:44PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
Hi Stan,
On Mon, 2013-10-07 at 12:22 +0300, Stanimir Varbanov wrote:
Hi Ivan,
Few comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers
Hi Stan,
On Mon, 2013-10-07 at 12:28 +0300, Stanimir Varbanov wrote:
Hi Ivan,
Minor comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows MSM EHCI controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-hsusb.txt | 17 +
drivers/usb/host/ehci-msm.c| 15
From: Ivan T. Ivanov iiva...@mm-sol.com
Use struct usb_hcd::phy to hold USB PHY instance.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/host/ehci-msm.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch fix compilation error and is an intermediate step
before the addition of DeviceTree support for newer targets.
Cc: David Brown dav...@codeaurora.org
Cc: Daniel Walker dwal...@fifo99.com
Cc: Felipe Balbi ba...@ti.com
Cc: Greg Kroah-Hartman gre
From: Ivan T. Ivanov iiva...@mm-sol.com
Whether regulators are available or not is checked at driver
probe. If they are not available driver will refuse to load,
so no need to check them again.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 10
From: Ivan T. Ivanov iiva...@mm-sol.com
There are no references to 'pclk_src_name' in plaform code,
so it is unused.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 26 +-
include/linux/usb/msm_hsusb.h |5 -
2 files changed
From: Ivan T. Ivanov iiva...@mm-sol.com
Prefix did not bring any useful information.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy
From: Ivan T. Ivanov iiva...@mm-sol.com
IRQ with number 0 is valid case, so check for negative
numbers instead.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c
From: Ivan T. Ivanov iiva...@mm-sol.com
Replace the USB specific clock names in driver
with the more standard 'core' and 'iface' ... names.
Cc: David Brown dav...@codeaurora.org
Cc: Stephen Boyd sb...@codeaurora.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
arch/arm/mach-msm/devices
From: Ivan T. Ivanov iiva...@mm-sol.com
USB DT bindings states: ...In case this attribute isn't
passed via DT, USB DRD controllers should default to OTG...,
so remove redundand field.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |7 ---
include
From: Ivan T. Ivanov iiva...@mm-sol.com
This fixes checkpatch.pl warnings.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm
From: Ivan T. Ivanov iiva...@mm-sol.com
Move memory, regulators, clocks and irq allocation to
devm_* variants. Properly check for valid clk handles.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 192 -
1 file
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
arch/arm/mach-msm/board-msm7x30.c |2 +-
arch/arm/mach-msm/board-qsd8x50.c |2 +-
drivers/usb/phy/phy-msm-usb.c | 40 ++---
include/linux/usb/msm_hsusb.h
From: Ivan T. Ivanov iiva...@mm-sol.com
This fixes checkpatch.pl warnings.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 33 +++--
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
This is third version of MSM OTG clean up patches.
v3
--
* In patch 1 - functions for reseting PHY and LINK controller just
call platform code if available.
* New stuff is: cleaning up unneeded/unused driver state variables
* Simplified regulator
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows MSM OTG controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-hsusb.txt | 58 +++
drivers/usb/phy/phy-msm-usb.c | 59
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 82 -
include/linux/usb/msm_hsusb.h |3 ++
2 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/drivers/usb/phy
On Mon, 2013-10-14 at 17:52 -0500, Felipe Balbi wrote:
Hi,
On Mon, Oct 14, 2013 at 06:24:28PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch fix compilation error and is an intermediate step
before the addition of DeviceTree support for newer targets
On Mon, 2013-10-14 at 17:59 -0500, Felipe Balbi wrote:
On Mon, Oct 14, 2013 at 06:24:39PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
IRQ with number 0 is valid case, so check for negative
not entirelly correct... IRQ 0 isn't supposed to be used as a linux IRQ
Hi,
On Tue, 2013-10-22 at 15:32 +0100, Mark Rutland wrote:
[...]
+ phy-sleep_a_clk = devm_clk_get(phy-dev, sleep_a);
What means the _a in clock name?
They are 2 PHY's on 8074 chip. This drivers is supposed to
operate on PHY 0, thus sleep_a. PHY 1 is using sleep_b. Take a
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: devicet...@vger.kernel.org
---
.../devicetree/bindings/usb/msm-hsusb.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/msm
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
This series intend to fixup driver, which was broken for a while. It is
used to create peripheral role device, which in coordination with
phy-usb-msm driver (still some cleanups pending) will provide again
USB2.0 gadget support for MSM targets
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c
b/drivers/usb/chipidea/ci_hdrc_msm.c
index 747d6c1..e9624f3 100644
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: devicet...@vger.kernel.org
---
drivers/usb/chipidea/ci_hdrc_msm.c | 23 ++-
1
From: Ivan T. Ivanov iiva...@mm-sol.com
PHY drivers keep track of the current state of the hardware,
so don't change PHY settings under it.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c |9 ++---
1 file changed, 2 insertions(+), 7 deletions
Hi Peter,
On Mon, 2013-11-11 at 21:59 +0800, Peter Chen wrote:
On Mon, Nov 11, 2013 at 03:35:37PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
PHY drivers keep track of the current state of the hardware,
so don't change PHY settings under it.
Signed-off
Hi Peter,
On Mon, 2013-11-11 at 22:02 +0800, Peter Chen wrote:
On Mon, Nov 11, 2013 at 03:35:33PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
This series intend to fixup driver, which was broken for a while. It is
used to create peripheral role
From: Ivan T. Ivanov iiva...@mm-sol.com
New platform uses RBCPR hardware feature, with that voting for
absolute voltage of VDD CX is not required. Hence vote for corner of
VDD CX which uses nominal corner voltage on VDD CX.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: Mayank Rana mr
From: Ivan T. Ivanov iiva...@mm-sol.com
Function return negative code on error.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
From: Ivan T. Ivanov iiva...@mm-sol.com
Allow support to use 2nd HSPHY with USB2 Core.
Some platforms may have configuration to allow USB controller
work with any of the two HSPHYs present. By default driver
configures USB core to use primary HSPHY. Add support to allow
user select 2nd HSPHY
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch fix compilation error when driver is compiled
in multi-platform builds.
drivers/built-in.o: In function `msm_otg_link_clk_reset':
./drivers/usb/phy/phy-msm-usb.c:314: undefined reference to `clk_reset'
./drivers/usb/phy/phy-msm-usb.c:318
From: Ivan T. Ivanov iiva...@mm-sol.com
This fixes following:
WARNING: quoted string split across lines
WARNING: Prefer seq_puts to seq_printf
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/phy/phy-msm-usb.c | 39 ++-
1 file changed, 14
From: Ivan T. Ivanov iiva...@mm-sol.com
Put the transceiver in non-driving mode. Otherwise host
may not detect soft-disconnection.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: Pavankumar Kondeti pkond...@codeaurora.org
---
drivers/usb/phy/phy-msm-usb.c | 18 ++
1 file
From: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Cc: devicet...@vger.kernel.org
---
.../devicetree/bindings/usb/msm-hsusb.txt |9 ++
drivers/usb/phy/phy-msm-usb.c | 30 ++--
include/linux/usb
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