enter_prom() used to save and restore registers such as CTR, XER etc..
which are volatile, or SRR0,1... which we don't care about. This
removes a bunch of useless code and while at it turns an mtmsrd into
an MTMSRD macro which will be useful to Book3E.
Signed-off-by: Benjamin Herrenschmidt
The current no hash MMU context management code is written with
the assumption that one CPU == one TLB. This is not the case on
implementations that support HW multithreading, where several
linux CPUs can share the same TLB.
This adds some basic support for this to our context management
and our
This adds the opcode definitions to ppc-opcode.h for the two instructions
tlbivax and tlbsrx. as defined by Book3E 2.06
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/ppc-opcode.h |6 ++
1 file changed, 6 insertions(+)
---
This adds various additional bit definitions for various MMU related
SPRs used on Book3E.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/mmu-book3e.h | 168 --
1 file changed, 119 insertions(+), 49 deletions(-)
---
This adds some code to do early ioremap's using page tables instead of
bolting entries in the hash table. This will be used by the upcoming
64-bits BookE port.
The patch also changes the test for early vs. late ioremap to use
slab_is_available() instead of our old hackish mem_init_done.
The way I intend to use tophys/tovirt on 64-bit BookE is different
from the trick that we currently play for 32-bit BookE so change
the condition of definition of these macros to make it so.
Also, make sure we only use rfid and mtmsrd instead of rfi and mtmsr
for 64-bit server processors, not all
We need to pass down whether the page is direct or indirect and we'll
need to pass the page size to _tlbil_va and _tlbivax_bcast
We also add a new low level _tlbil_pid_noind() which does a TLB flush
by PID but avoids flushing indirect entries if possible
This implements those new prototypes but
Our 64-bit hash context handling has no init function, but 64-bit Book3E
will use the common mmu_context_nohash.c code which does, so define an
empty inline mmu_context_init() for 64-bit server and call it from
our 64-bit setup_arch()
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Currently, a single ifdef covers SLB related bits and more generic ppc64
related bits, split this in two separate ifdef's since 64-bit BookE will
need one but not the other.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/kernel/process.c |2 ++
1 file
Those definitions are currently declared extern in the .c file where
they are used, move them to a header file instead.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
--
arch/powerpc/include/asm/smp.h |5 +
arch/powerpc/kernel/setup_64.c |3 ---
2 files changed, 5
64-bit BookE will use that hook to maintain the virtually linear
page tables or the indirect entries in the TLB when using the
HW loader.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/pgalloc.h | 13 -
1 file changed, 12 insertions(+),
This adds various SPRs defined on 64-bit BookE, along with changes
to the definition of the base MSR values to add the values needed
for 64-bit Book3E.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/reg.h | 10 +++---
This adds the PTE and pgtable format definitions, along with changes
to the kernel memory map and other definitions related to implementing
support for 64-bit Book3E. This also shields some asm-offset bits that
are currently only relevant on 32-bit
Signed-off-by: Benjamin Herrenschmidt
This adds various definitions and macros used by the exception and TLB
miss handling on 64-bit BookE
It also adds the definitions of the SPRGs used for various exception types
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/exception-64e.h | 200
This adds various fields in the PACA that are for use specifically
by Book3E processors, such as exception save areas, current pgd
pointer, special exceptions kernel stacks etc...
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/paca.h | 23
The definition for the global structure mmu_gathers, used by generic code,
is currently defined in multiple places not including anything used by
64-bit Book3E. This changes it by moving to one place common to all
processors.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
This adds the TLB miss handler assembly, the low level TLB flush routines
along with the necessary hook for dealing with our virtual page tables
or indirect TLB entries that need to be flushes when PTE pages are freed.
There is currently no support for hugetlbfs
Signed-off-by: Benjamin
The base TLB support didn't include support for SPARSEMEM_VMEMMAP, though
we did carve out some virtual space for it, the necessary support code
wasn't there. This implements it by using 16M pages for now, though the
page size could easily be changed at runtime if necessary.
Signed-off-by:
This contains all the bits that didn't fit in previous patches :-) This
includes the actual exception handlers assembly, the changes to the
kernel entry, other misc bits and wiring it all up in Kconfig.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/Kconfig
Here is a series of patches that implement some basic support
for 64-bit Book3E processors that comply to architecture 2.06.
There is no specific processor announced yet. The patches make
some shortcut which means they currently rely on an implementation
that supports MMU v2 with support for the
Hi Ben,
On Thu, 23 Jul 2009 15:59:44 +1000 Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Index: linux-work/arch/powerpc/mm/mmu_context_hash64.c
===
--- linux-work.orig/arch/powerpc/mm/mmu_context_hash64.c
On Sat, 2009-06-27 at 15:30 +1000, Paul Mackerras wrote:
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine on a 64-bit kernel. Such an
access can cause a SLB miss interrupt and/or a MMU hash table miss
interrupt.
An SLB miss
Hi Ben,
On Thu, 23 Jul 2009 15:59:46 +1000 Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
+#ifdef CONFIG_PPC_BOOK3E
+extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
+#else
+#define tlb_flush_pgtable(tlb, address) do { } while(0)
static inline void
Hi Ben,
On Thu, 23 Jul 2009 15:59:47 +1000 Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
@@ -480,3 +508,4 @@
#endif /* 403GCX */
#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
#endif /* __KERNEL__ */
+
I know I am being trivial here ... :-)
--
Cheers,
Stephen Rothwell
On Thu, 2009-07-23 at 16:22 +1000, Stephen Rothwell wrote:
Hi Ben,
On Thu, 23 Jul 2009 15:59:44 +1000 Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Index: linux-work/arch/powerpc/mm/mmu_context_hash64.c
===
---
On Thu, 2009-07-02 at 17:12 +0100, Martyn Welch wrote:
Remove the reliance on a staticly defined NVRAM size, allowing platforms to
support NVRAMs with sizes differing from the standard. A fall back value is
provided for platforms not supporting this extension.
Signed-off-by: Martyn Welch
On Thu, 2009-07-02 at 17:12 +0100, Martyn Welch wrote:
The following series allows the generic NVRAM driver to access MMIO
based NVRAMs. In addition it enables support for NVRAMs of sizes
differing from those found on PowerPC Macs (providing a safe
fallback). Patches are also included to
dtc was moved in 9fffb55f66127b52c937ede5196ebfa0c0d50bce from
arch/powerpc/boot/ to scripts/dtc/
This patch updates the wrapper script to point to the new location of dtc.
Signed-off-by: Lucian Adrian Grijincu lgriji...@ixiacom.com
---
arch/powerpc/boot/wrapper |3 ++-
1 files changed, 2
Changes to the fs_enet driver (aa73832c5a80d6c52c69b18af858d88fa595dd3c) cause
kernel crashes when using the mdio-ofgpio driver.
This patch replicates similar changes made to the fs_enet mii-bitbang drivers.
It has been tested on a custom mpc8280 based board using an NFS mounted root.
Benjamin Herrenschmidt wrote:
On Thu, 2009-07-02 at 17:12 +0100, Martyn Welch wrote:
Remove the reliance on a staticly defined NVRAM size, allowing platforms to
support NVRAMs with sizes differing from the standard. A fall back value is
provided for platforms not supporting this extension.
2009/7/16 Michael Ellerman mich...@ellerman.id.au:
On Thu, 2009-07-16 at 09:33 -0700, Mike Mason wrote:
Michael Ellerman wrote:
On Wed, 2009-07-15 at 14:43 -0700, Mike Mason wrote:
This patch increments the device_node reference counter when an EEH
error occurs and decrements the counter
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
The way I intend to use tophys/tovirt on 64-bit BookE is different
from the trick that we currently play for 32-bit BookE so change
the condition of definition of these macros to make it so.
Also, make sure we only use rfid and
On Jul 23, 2009, at 1:02 AM, Benjamin Herrenschmidt wrote:
Here is a series of patches that implement some basic support
for 64-bit Book3E processors that comply to architecture 2.06.
There is no specific processor announced yet. The patches make
some shortcut which means they currently rely
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
+/* Bit definitions for EPCR */
+#define SPRN_EPCR_EXTGS0x8000
+#define SPRN_EPCR_DTLBGS 0x4000
+#define SPRN_EPCR_ITLBGS 0x2000
+#define SPRN_EPCR_DSIGS0x1000
+#define
2009/7/15 Mike Mason mm...@us.ibm.com:
By default, EEH does what's known as a hot reset during error recovery of
a PCI Express device. We've found a case where the device needs a
fundamental reset to recover properly. The current PCI error recovery and
EEH frameworks do not support this
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
Our 64-bit hash context handling has no init function, but 64-bit
Book3E
will use the common mmu_context_nohash.c code which does, so define an
empty inline mmu_context_init() for 64-bit server and call it from
our 64-bit
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
Currently, a single ifdef covers SLB related bits and more generic
ppc64
related bits, split this in two separate ifdef's since 64-bit BookE
will
need one but not the other.
Signed-off-by: Benjamin Herrenschmidt
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
Those definitions are currently declared extern in the .c file where
they are used, move them to a header file instead.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
--
arch/powerpc/include/asm/smp.h |5 +
The truncate syscall has a signed long parameter, so when using a 32-
bit userspace with a 64-bit kernel the argument is zero-extended
instead of sign-extended. Adding the compat_sys_truncate function
fixes the issue.
This was noticed during an LSB truncate test failure. The test was
On Jul 23, 2009, at 2:09 AM, FUJITA Tomonori wrote:
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/
powerpc/platforms/86xx/mpc86xx_hpcn.c
index 6632702..d1878f3 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -187,5
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
This adds the opcode definitions to ppc-opcode.h for the two
instructions
tlbivax and tlbsrx. as defined by Book3E 2.06
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/include/asm/ppc-opcode.h |
From: Mark Ware mw...@elphinstone.net
Date: Thu, 23 Jul 2009 21:20:27 +1000
Changes to the fs_enet driver (aa73832c5a80d6c52c69b18af858d88fa595dd3c)
cause kernel crashes when using the mdio-ofgpio driver.
This patch replicates similar changes made to the fs_enet mii-bitbang
drivers. It
Signed-off-by: Frans Pop elen...@planet.nl
---
Change was suggested by Sam Ravnborg; see http://lkml.org/lkml/2009/7/18/15.
Untested.
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index bc35f4e..952a396 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -77,7 +77,7 @@
Hi,
I am working on Linux-2.6.29.5 on an MPC8360E, trying to make the FHCI USB
working.
the output of clocks in u-boot is as follows:
Output of u-boot clocks command
Clock configuration:
Core:533.333 MHz
Coherent System Bus: 266.667 MHz
QE: 400 MHz
On Thu, Jul 23, 2009 at 08:57:18PM +0200, Frans Pop wrote:
Signed-off-by: Frans Pop elen...@planet.nl
Acked-by: Sam Ravnborg s...@ravnborg.org
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
On Thu, 2009-07-23 at 09:42 -0500, Kumar Gala wrote:
The intend is to merge these in 2.6.32. They rely on pretty much
all the other patches I've been posting lately including the
generic changes to add the virtual address argument to pte_free_tlb.
Are these in a git tree/branch.
On Thu, 2009-07-23 at 09:51 -0500, Kumar Gala wrote:
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
Those definitions are currently declared extern in the .c file where
they are used, move them to a header file instead.
Signed-off-by: Benjamin Herrenschmidt
On Thu, 2009-07-23 at 10:55 -0500, Kumar Gala wrote:
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
This adds the opcode definitions to ppc-opcode.h for the two
instructions
tlbivax and tlbsrx. as defined by Book3E 2.06
Signed-off-by: Benjamin Herrenschmidt
On Thu, 2009-07-23 at 23:31 +0200, Sam Ravnborg wrote:
On Thu, Jul 23, 2009 at 08:57:18PM +0200, Frans Pop wrote:
Signed-off-by: Frans Pop elen...@planet.nl
Acked-by: Sam Ravnborg s...@ravnborg.org
Thanks, will include in my next batch.
Cheers,
Ben.
We're trying to use the SATA interface on our PowerPC460EX.
We've applied the following patch:
http://markmail.org/message/p5kdgzyneuxzdvjh
Our kernel is based on AMCC's Arches eval board distro kernel
(2.6.27-rc5),
and with this patch, we're able to get the SATA interface up and running,
On Thu, Jul 23, 2009 at 6:33 AM, Kumar Gala ga...@kernel.crashing.orgwrote:
On Jul 22, 2009, at 11:32 AM, srikanth krishnakar wrote:
On Wed, Jul 22, 2009 at 9:14 PM, Kumar Gala ga...@kernel.crashing.org
wrote:
On Jul 22, 2009, at 10:38 AM, srikanth krishnakar wrote:
On Wed, Jul 22,
This patch (against 2.6.30) adds support for the ESTeem 195E Hotfoot
SBC. We've been maintaining this out-of-tree for some time now for
older kernels, but recently I ported it to the new unified powerpc tree
with the intent of pushing it upstream.
The board uses an ancient version of u-boot and
This patch adds support for the ESTeem 195E Hotfoot SBC.
We've been maintaining this out-of-tree for some time now for
older kernels, but recently I ported it to the new unified powerpc tree
with the intent of pushing it upstream.
The board uses an ancient version of u-boot and a slightly
Hello list,
I'm running Gentoo Linux with kernel 2.6.29 on a PPC9600 with a G3
processor upgrade.
My boot drive is on the internal mesh SCSI-controller. Self-compiled
kernel 2.6.29 is running fine for quite some time.
However, after compiling 2.6.30 (with more or less the same
POWERPC needs this hook. SPARC could use it too.
Signed-off-by: FUJITA Tomonori fujita.tomon...@lab.ntt.co.jp
---
include/linux/dma-mapping.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index c0f6c3c..91b7618
Signed-off-by: FUJITA Tomonori fujita.tomon...@lab.ntt.co.jp
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/dma-mapping.h | 242 +---
2 files changed, 7 insertions(+), 237 deletions(-)
diff --git a/arch/powerpc/Kconfig
This patchset converts POWERPC to use asm-generic/dma-mapping-common.h.
The major change is removing addr_needs_map in struct dma_mapping_ops
(1/5):
http://marc.info/?t=12471906021r=1w=2
This is on the top of my swiotlb cleanup patchset:
This converts uses dma_map_ops struct (in include/linux/dma-mapping.h)
instead of POWERPC homegrown dma_mapping_ops.
Signed-off-by: FUJITA Tomonori fujita.tomon...@lab.ntt.co.jp
---
arch/powerpc/include/asm/device.h |4 +-
arch/powerpc/include/asm/dma-mapping.h | 84
On Jul 23, 2009, at 5:12 PM, Benjamin Herrenschmidt wrote:
On Thu, 2009-07-23 at 10:55 -0500, Kumar Gala wrote:
On Jul 23, 2009, at 12:59 AM, Benjamin Herrenschmidt wrote:
This adds the opcode definitions to ppc-opcode.h for the two
instructions
tlbivax and tlbsrx. as defined by Book3E 2.06
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