Johnny == Johnny Hung johnny.hack...@gmail.com writes:
Johnny Hi All:
Johnny Is there a alreday written GPIO dirver or example for
Johnny MPC8313/similar ppc platform. It looks like many people need GPIO
Johnny dirver to control LED, etc... I think is it possible to write a
Johnny
Sachin Sant wrote:
Sachin Sant wrote:
Tejun Heo wrote:
Ah... sorry about that. Sachin, is it possible for you to build the
kernel with debug info and ask gdb where the stalling NIP is in the c
file?
6NET: Registered protocol family 10
3BUG: soft lockup - CPU#2 stuck for 61s!
Sachin Sant wrote:
Sachin Sant wrote:
Sachin Sant wrote:
Tejun Heo wrote:
Ah... sorry about that. Sachin, is it possible for you to build the
kernel with debug info and ask gdb where the stalling NIP is in the c
file?
6NET: Registered protocol family 10
3BUG: soft lockup - CPU#2 stuck
Works perfectly here. Thank you for the patch, I was not feeling confident
enough to play around with the page bits :)
Bernhard WEIRICH
Software Development
Von: Benjamin Herrenschmidt [b...@kernel.crashing.org]
Gesendet: Mittwoch, 23. September 2009
Thanks, got it. BTW, how to trigger GPIO level in user space
application? I also found arch/powerpc/platforms/52xx/mpc52xx_gpio.c
is a good example. Any reply is appreciate.
BRs, H. Johnny
2009/9/23 Peter Korsgaard jac...@sunsite.dk:
Johnny == Johnny Hung johnny.hack...@gmail.com writes:
Johnny == Johnny Hung johnny.hack...@gmail.com writes:
Johnny Thanks, got it. BTW, how to trigger GPIO level in user space
Johnny application? I also found
Johnny arch/powerpc/platforms/52xx/mpc52xx_gpio.c is a good
Johnny example. Any reply is appreciate.
Through sysfs. See 'Sysfs
Hi Vivek,
The build errors have been fixed with commit
cd74c86bdf705f824d494a2bbda393d1d562b40a.
thanks and regards,
markus.
From: Mahajan Vivek-B08308 [mailto:vivek.maha...@freescale.com]
Sent: Wednesday, September 23, 2009 1:05 PM
To: linuxppc-...@ozlabs.org
Cc: Metzger, Markus T
Subject:
Adds documentation for the size parameter of Freescale's QorIQ
based cache-sram
Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
---
Documentation/kernel-parameters.txt |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/kernel-parameters.txt
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its base address
Signed-off-by: Vivek Mahajan
This patch enable cache snooping when the sdhc is initialized.
---
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |4
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 288e40b..cc6d45c 100644
---
---
arch/powerpc/boot/dts/p2020ds.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts
b/arch/powerpc/boot/dts/p2020ds.dts
index 8c1c954..be449ba 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++
The SDHC can not work on DMA mode because of the hardware bug,
so we set a broken dma flag and use PIO mode. This patch applies
to Rev1.0.
---
arch/powerpc/boot/dts/p2020ds.dts |1 +
drivers/mmc/host/sdhci-of.c |3 +++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git
This patch implemnet the workaround that the bit
DCR[DMA__AHB2MAG_IRQ_BYPASS] cannot be set automatically
when SoC reset.
---
arch/powerpc/boot/dts/p2020ds.dts |1 +
drivers/mmc/host/sdhci-of.c |5 -
drivers/mmc/host/sdhci.c |8
drivers/mmc/host/sdhci.h
When access the card, the following error is reported:
mmc0: Got data interrupt 0x0020 even though no data operation was in
progress.
mmc0: Got data interrupt 0x0020 even though no data operation was in
progress.
so we skip the calculation of timeout and use the max value.
---
The SDHC on P2020DS board use DMA mode by default.
This patch remove the properties used in PIO mode.
---
arch/powerpc/boot/dts/p2020ds.dts |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts
b/arch/powerpc/boot/dts/p2020ds.dts
index
Hello Markus,
Apparently this
http://git.kernel.org/?p=linux/kernel/git/benh/powerpc.git;a=commitdiff;
h=5622f295b53fb60dbf9bed3e2c89d182490a8b7f breaks the powerpc build as
under when built from
http://git.kernel.org/?p=linux/kernel/git/benh/powerpc.git;a=summary
with latest commit
On Wed, Sep 23, 2009 at 05:08:07PM +0800, Gao Guanhua wrote:
This patch enable cache snooping when the sdhc is initialized.
---
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |4
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c
On Wed, Sep 23, 2009 at 05:08:09PM +0800, Gao Guanhua wrote:
The SDHC can not work on DMA mode because of the hardware bug,
so we set a broken dma flag and use PIO mode. This patch applies
to Rev1.0.
Signed-off-by line is missing (in all patches).
---
arch/powerpc/boot/dts/p2020ds.dts |
Thank you for taking the time in confirming some of the
potential strategies I was already thinking about...:-)
I am going to try to pre-allocate some resources for
the specific port/slot/bridge device (because we know
at all times that port #6 (bus #5) is going to have
a FPGA end device
On Wed, Sep 23, 2009 at 05:08:12PM +0800, Gao Guanhua wrote:
The SDHC on P2020DS board use DMA mode by default.
This patch remove the properties used in PIO mode.
You just added the properties in 3/6 and 4/6, and now you instantly
remove them?
---
arch/powerpc/boot/dts/p2020ds.dts |2 --
* Michael Ellerman mich...@ellerman.id.au wrote:
On Tue, 2009-09-22 at 18:00 +1000, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-22 at 09:28 +0200, Ingo Molnar wrote:
Nevertheless you are right that i should have caught this particular
PowerPC build bug - i missed it - sorry about
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 22/09/2009
22:08:22:
Unfortunately, I am not sensitive to issues surrounding 1TB segments or
how
they are currently being used. However, as this clearly helps
performance
for large amounts of memory, is it worth providing an option to
Hi All,
A couple of simple fixes to improve xmon usage on 4xx boards. I have no idea
if anyone else even uses this, but I find it handy from time to time.
josh
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
The xmon code relies on MSR_RI being non-zero to indicate that an exception
is recoverable. If it is not, it prints a warning message. However, the
PowerPC 4xx cores do not have an MSR_RI bit and this warning is produced for
every xmon event.
This introduces an unrecoverable_excp function to
Prior to the arch/ppc - arch/powerpc transition, xmon had support for single
stepping on 4xx boards. The functionality was lost when arch/ppc was removed.
This patch restores single step support for 44x boards.
Signed-off-by: Josh Boyer jwbo...@linux.vnet.ibm.com
---
arch/powerpc/xmon/xmon.c |
Tejun Heo wrote:
One workaround i have found for this problem is to disable IPv6.
With IPv6 disabled the machine boots OK. Till a reliable solution
is available for this issue, i will keep IPv6 disabled in my configs.
I'm think it's most likely caused by some code accessing invalid
percpu
I am trying to port linux on IBM powerpc-440x5. I have this board
which has this processor, a 16MB SRAM sits on location 0x0, uart and a
flash.I have a simple bootloader which does the following.
1. Initialize the processor (as part of it, we Generates the tlbs
for UART,16MB flash,16MB SRAM)
Many thanks for your help. I will try it.
2009/9/23 Peter Korsgaard jac...@sunsite.dk:
Johnny == Johnny Hung johnny.hack...@gmail.com writes:
Johnny Thanks, got it. BTW, how to trigger GPIO level in user space
Johnny application? I also found
Johnny
On Tue, Sep 22, 2009 at 11:18:09AM -0400, Tim Abbott wrote:
Signed-off-by: Tim Abbott tabb...@ksplice.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-...@ozlabs.org
Cc: Sam Ravnborg s...@ravnborg.org
Look good.
Acked-by: Sam Ravnborg
On Wed, Sep 16, 2009 at 09:19:43AM -0400, Josh Boyer wrote:
On Wed, Sep 16, 2009 at 07:44:07AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-15 at 11:32 -0400, Josh Boyer wrote:
Ok, so I think that is related to what I originally hit.
I played around with removing the current-speed
Hi all,
A few patches needed to support FSL EHCI resuming after deep sleep.
Without these patches MPC8315E-RDB boards hang on resume (USB PHY
settings aren't preserved after deep sleep so USB controller becomes
confused on resume, and hangs).
Thanks,
--
Anton Vorontsov
email:
Export is needed for modular builds, and a static inline stub is needed
for non-MPC83xx builds.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
arch/powerpc/platforms/83xx/suspend.c |1 +
include/linux/fsl_devices.h |4
2 files changed, 5 insertions(+), 0
This patch fixes following warnings:
ehci-fsl.c:43:5: warning: symbol 'usb_hcd_fsl_probe' was not declared. Should
it be static?
ehci-fsl.c:150:6: warning: symbol 'usb_hcd_fsl_remove' was not declared. Should
it be static?
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
EHCI FSL controller preserve its state during sleep mode, so nothing
fancy needs to be done.
Though, during 'deep sleep' mode (as found in MPC831x CPUs) the
controller turns off and needs to be reinitialized upon resume.
This patch adds support for resuming after deep sleep. Based on Dave
Liu
Hi all,
Here are some patches to make suspend/resume work on MPC8315E-RDB...
Thanks,
--
Anton Vorontsov
email: cbouatmai...@gmail.com
irc://irc.freenode.net/bd2
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
Currently 83xx PMC driver clears deep_sleeping variable very early,
before devices are resumed. This makes fsl_deep_sleep() unusable in
drivers' resume() callback.
Sure, drivers can store fsl_deep_sleep() value on suspend and use
the stored value on resume. But a better solution is to postpone
We need to save SICRL, SICRH and SCCR registers on suspend, and restore
them on resume. Otherwise, we lose IO and clocks setup on MPC8315E-RDB
boards when ULPI USB PHY is used (non-POR setup).
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
arch/powerpc/platforms/83xx/suspend.c |
- Add nodes for PMC and GTM controllers. GTM4 can be used as a wakeup
source;
- Add fsl,magic-packet properties to eTSEC nodes, i.e. wake-on-lan
support. Unlike MPC8313 processors, MPC8315 can resume from deep
sleep upon magic packet reception;
- Add proper sleep = properties;
- DMA and
Hello,
This patch should export crtsavres.o, as suggested in comment# 4 by Olaf
Hering at
http://bugzilla.kernel.org/show_bug.cgi?id=11143.
Otherwise, it's the same as original work done by Bernhard Reutner-Fischer.
Please, consider to apply.
//
Fix linking modules against crtsavres.o
On Wed, 2009-09-23 at 09:51 -0400, Josh Boyer wrote:
Prior to the arch/ppc - arch/powerpc transition, xmon had support for single
stepping on 4xx boards. The functionality was lost when arch/ppc was removed.
This patch restores single step support for 44x boards.
Signed-off-by: Josh Boyer
On Wed, 2009-09-23 at 20:19 +0530, Vineeth _ wrote:
I am trying to port linux on IBM powerpc-440x5. I have this board
which has this processor, a 16MB SRAM sits on location 0x0, uart and a
flash.I have a simple bootloader which does the following.
1. Initialize the processor (as part of
On Thu, Sep 24, 2009 at 07:34:34AM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2009-09-23 at 09:51 -0400, Josh Boyer wrote:
Prior to the arch/ppc - arch/powerpc transition, xmon had support for single
stepping on 4xx boards. The functionality was lost when arch/ppc was
removed.
This patch
On Wed, 2009-09-23 at 18:35 -0400, Josh Boyer wrote:
Any reason why that couldn't be in CONFIG_BOOKE ?
Off the top of my head, no. I haven't tested on 40x yet though. Will try
and do that and revise.
Does 40x have CONFIG_BOOKE ? I was thinking more about FSL etc... but
yeah, 40x is worth
-Original Message-
From: Richard Röjfors [mailto:richard.rojf...@mocean-labs.com]
Sent: Tuesday, September 22, 2009 3:59 PM
To: John Linn
Cc: spi-devel-gene...@lists.sourceforge.net; linuxppc-...@ozlabs.org; Andrew
Morton;
dbrown...@users.sourceforge.net
Subject: Re: [PATCH v3]
On Wed, 2009-09-23 at 14:44 +0200, Ingo Molnar wrote:
* Michael Ellerman mich...@ellerman.id.au wrote:
On Tue, 2009-09-22 at 18:00 +1000, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-22 at 09:28 +0200, Ingo Molnar wrote:
Nevertheless you are right that i should have caught this
On Thu, Sep 24, 2009 at 07:34:34AM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2009-09-23 at 09:51 -0400, Josh Boyer wrote:
[snip]
+static int do_step(struct pt_regs *regs)
+{
+ regs-msr |= MSR_DE;
+ mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
I'm not sure about
On Wed, 2009-09-02 at 07:33 +0200, Peter Zijlstra wrote:
I'm still thinking this is a bad idea.
The OS should only know about online/offline.
Use the hypervisor interface to deal with the cpu once its offline.
That is, I think this interface you propose is a layering violation.
I
On Tue, 2009-09-15 at 14:11 +0200, Peter Zijlstra wrote:
I still think its a layering violation... its the hypervisor manager
that should be bothered in what state an off-lined cpu is in.
That's not how our hypervisor works.
If you ask through the management interface, to remove a CPU from a
On Wed, 2009-09-16 at 21:54 +0530, Dipankar Sarma wrote:
You aren't, I did :)
No, for this specific case, latency isn't an issue. The issue is -
how do we cede unused vcpus to hypervisor for better energy
management ?
Yes, it can be done by a hypervisor manager telling the kernel to
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
Bernhard, Rex, please let me know if that works for you.
it doesn't work for me, it crashes differently then before though!
This patch worked for me:
Signed-off-by: Bernhard Weirich bernhard.weir...@riedel.net
---
After upgrading to the latest kernel on my mpc875 userspace started
running incredibly slow (hours to get to a shell, even!).
I tracked it down to commit 8d30c14cab30d405a05f2aaceda1e9ad57800f36,
that patch removed a work-around for the 8xx. Adding it
back makes my problem go away.
Signed-off-by:
On Wed, 2009-09-23 at 17:53 -0700, Rex Feany wrote:
this is running on a MPC 875, and I'm happy to test any patches or
add any debugging code if it helps.
Hrm... smells like something screwy in the 8xx PTE handling.
Let me have another look.
Cheers,
Ben.
On Wed, 2009-09-23 at 17:53 -0700, Rex Feany wrote:
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
Bernhard, Rex, please let me know if that works for you.
it doesn't work for me, it crashes differently then before though!
Hrm. This is really strange...
trunk+benh
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
Hrm. This is really strange...
Is this a problem? in pte-8xx.h you added:
+#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
but there is already this:
#define _PAGE_EXEC 0x0008 /* software: i-cache
On Wed, 2009-09-23 at 19:38 -0700, Rex Feany wrote:
Thus spake Benjamin Herrenschmidt (b...@kernel.crashing.org):
Hrm. This is really strange...
Is this a problem? in pte-8xx.h you added:
+#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
but there is already
On Thu, 2009-09-10 at 16:54 -0700, David Daney wrote:
Starting with version 4.5, GCC has a new built-in function called
__builtin_unreachable(). The function tells the compiler that control
flow will never reach that point. Currently we trick the compiler by
putting in for(;;); but this has
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-09-22 16:55:27]:
Hi Len, (or other acpi folks),
I had a question regarding ACPI-cpuidle interaction in the current
implementation.
Currently, every cpu (i.e. acpi_processor) registers to cpuidle as
a cpuidle_device. So every cpu has to go through
Hi all,
Today's linux-next build (powerpc ppc44x_defconfig) failed like this:
In file included from arch/powerpc/kvm/booke.c:31:
arch/powerpc/kvm/timing.h: In function 'kvmppc_account_exit_stat':
arch/powerpc/kvm/timing.h:51: error: bit-field 'anonymous' width not an
integer constant
In file
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