Re: [PATCH v2 10/12] selftests/powerpc: Add more utility macros

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > * Include unistd.h for _exit() > * Include stdio.h for fprintf() > * Adds _MSG assertion variants to provide more context behind why a >   failure occurred. > * Move ARRAY_SIZE macro to utils.h > > The _MSG variants and ARRAY_SIZE will be

Re: [PATCH v2 09/12] Documentation: Document PowerPC kernel DEXCR interface

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > Describe the DEXCR and document how to configure it. > > Signed-off-by: Benjamin Gray > > --- > v2: * Document coredump & ptrace support > v1: * Remove the dynamic control docs, describe the static config >   option > >

Re: [PATCH v2 08/12] powerpc/ptrace: Expose HASHKEYR register to ptrace

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > The HASHKEYR register contains a secret per-process key to enable > unique > hashes per process. In general it should not be exposed to userspace > at all and a regular process has no need to know its key. > > However, checkpoint restore

Re: [PATCH v2 07/12] powerpc/ptrace: Expose DEXCR and HDEXCR registers to ptrace

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > The DEXCR register is of interest when ptracing processes. Currently > it > is static, but eventually will be dynamically controllable by a > process. > If a process can control its own, then it is useful for it to be > ptrace-able to

Re: [PATCH v2 06/12] powerpc/dexcr: Support custom default DEXCR value

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > Make the DEXCR value configurable at config time. Intentionally don't > limit possible values to support future aspects without needing > kernel > updates. > > The default config value enables hashst/hashchk in problem state. > This should

Re: [PATCH v2 05/12] powerpc/dexcr: Support userspace ROP protection

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > The ISA 3.1B hashst and hashchk instructions use a per-cpu SPR > HASHKEYR > to hold a key used in the hash calculation. This key should be > different > for each process to make it harder for a malicious process to > recreate > valid hash

Re: [PATCH v2 04/12] powerpc/dexcr: Handle hashchk exception

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > Recognise and pass the appropriate signal to the user program when a > hashchk instruction triggers. This is independent of allowing > configuration of DEXCR[NPHIE], as a hypervisor can enforce this > aspect > regardless of the kernel. > >

Re: [PATCH v2 01/12] powerpc/book3s: Add missing include

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > The functions here use struct thread_struct fields, so need to import > the full definition from . The header > that defines current only forward declares struct thread_struct. > > Failing to include this header leads to a compilation >

Re: [PATCH v2 03/12] powerpc/dexcr: Add initial Dynamic Execution Control Register (DEXCR) support

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > ISA 3.1B introduces the Dynamic Execution Control Register (DEXCR). > It > is a per-cpu register that allows control over various CPU behaviours > including branch hint usage, indirect branch speculation, and > hashst/hashchk support. > >

Re: [PATCH v2 02/12] powerpc/ptrace: Add missing include

On Thu, 2023-03-30 at 16:50 +1100, Benjamin Gray wrote: > ptrace-decl.h uses user_regset_get2_fn (among other things) from > regset.h. While all current users of ptrace-decl.h include regset.h > before it anyway, it adds an implicit ordering dependency and breaks > source tooling that tries to

Re: [PATCH v4 0/2] Copy-on-write poison recovery

Get Outlook for Android

[PATCH 10/12] powerpc: powernv: Annotate data races in opal events

The kopald thread handles opal events as they appear, but by polling a static bit-vector in last_outstanding_events. Annotate these data races accordingly. We are not at risk of missing events, but use of READ_ONCE, WRITE_ONCE will assist readers in seeing that kopald only consumes the events it

[PATCH 02/12] powerpc: qspinlock: Mark accesses to qnode lock checks

The powerpc implemenation of qspinlocks will both poll and spin on the bitlock guarding a qnode. Mark these accesses with READ_ONCE to convey to KCSAN that polling is intentional here. Signed-off-by: Rohan McLure --- arch/powerpc/lib/qspinlock.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 06/12] powerpc: Mark accesses to power_save callback in arch_cpu_idle

The power_save callback can be overwritten by another core at boot time. Specifically, null values will be replaced exactly once with the callback suitable for the particular platform (PowerNV / pseries lpars). Mark reads to this variable with READ_ONCE to signal to KCSAN that this race is

[PATCH 11/12] powerpc: powernv: Annotate asynchronous access to opal tokens

The opal-async.c unit contains code for polling event sources, which implies intentional data races. Ensure that the compiler will atomically access such variables by means of {READ,WRITE}_ONCE calls, which in turn inform KCSAN that polling behaviour is intended. Signed-off-by: Rohan McLure ---

[PATCH 05/12] powerpc: Mark [h]ssr_valid accesses in check_return_regs_valid

Checks to see if the [H]SRR registers have been clobbered by (soft) NMI interrupts imply the possibility for a data race on the [h]srr_valid entries in the PACA. Annotate accesses to these fields with READ_ONCE, removing the need for the barrier. The diagnostic can use plain-access reads and

[PATCH 12/12] powerpc: Mark asynchronous accesses to irq_data

KCSAN revealed that while irq_data entries are written to either from behind a mutex, or otherwise atomically, accesses to irq_data->hwirq can occur asynchronously, without volatile annotation. Mark these accesses with READ_ONCE to avoid unfortunate compiler reorderings and remove KCSAN warnings.

[PATCH 08/12] powerpc: Annotate accesses to ipi message flags

IPI message flags are observed and consequently consumed in the smp_ipi_demux_relaxed function, which handles these message sources until it observes none more arriving. Mark the checked loop guard with READ_ONCE, to signal to KCSAN that the read is known to be volatile, and that non-determinism

[PATCH 00/12] powerpc: KCSAN fix warnings and mark accesses

The KCSAN sanitiser notifies programmers of instances where unmarked accesses to shared state has lead to a data race, or when the compiler has liberty to reorder an unmarked access and so generate a data race. This patch series deals with benign data races, which nonetheless need annotation in

[PATCH 09/12] powerpc: Mark writes registering ipi to host cpu through kvm

Mark writes to hypervisor ipi state so that KCSAN recognises these asynchronous issue of kvmppc_{set,clear}_host_ipi to be intended, with atomic writes. Signed-off-by: Rohan McLure --- arch/powerpc/include/asm/kvm_ppc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 07/12] powerpc: powernv: Fix KCSAN datarace warnings on idle_state contention

The idle_state entry in the PACA on PowerNV features a bit which is atomically tested and set through ldarx/stdcx. to be used as a spinlock. This lock then guards access to other bit fields of idle_state. KCSAN cannot differentiate between any of these bitfield accesses as they all are implemented

[PATCH 03/12] powerpc: qspinlock: Enforce qnode writes prior to publishing to queue

Use a compiler barrier to enforce that all fields of a new struct qnode be written to (especially the lock value) before publishing the qnode to the waitqueue. Signed-off-by: Rohan McLure --- arch/powerpc/lib/qspinlock.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH 04/12] asm-generic/mmiowb: Mark accesses to fix KCSAN warnings

Prior to this patch, data races are detectable by KCSAN of the following forms: [1] Asynchronous calls to mmiowb_set_pending() from an interrupt context or otherwise outside of a critical section [2] Interrupted critical sections, where the interrupt will itself acquire a lock In case

[PATCH 01/12] powerpc: qspinlock: Fix qnode->locked value interpretation

A comment accompanying the locked attribute of a qnode assigns a value of 1 to mean that the lock has been acquired. The usages of this variable however assume opposite semantics. Update usages so that the assertions of this comment are reflected in this file. Signed-off-by: Rohan McLure ---

Re: [PATCH v4 05/17] watchdog/hardlockup: Rename touch_nmi_watchdog() to touch_hardlockup_watchdog()

On Sat May 6, 2023 at 2:37 AM AEST, Doug Anderson wrote: > Hi, > > On Thu, May 4, 2023 at 7:51 PM Nicholas Piggin wrote: > > > > On Fri May 5, 2023 at 8:13 AM AEST, Douglas Anderson wrote: > > > In preparation for the buddy hardlockup detector, rename > > > touch_nmi_watchdog() to

Re: [PATCH v4 13/17] watchdog/hardlockup: detect hard lockups using secondary (buddy) CPUs

On Sat May 6, 2023 at 2:35 AM AEST, Doug Anderson wrote: > Hi, > > On Thu, May 4, 2023 at 7:36 PM Nicholas Piggin wrote: > > > > On Fri May 5, 2023 at 8:13 AM AEST, Douglas Anderson wrote: > > > From: Colin Cross > > > > > > Implement a hardlockup detector that doesn't doesn't need any extra > >

Re: [PATCH v8 7/7] PCI: Work around PCIe link training failures

On Thu, 4 May 2023, Bjorn Helgaas wrote: > On Thu, Apr 06, 2023 at 01:21:31AM +0100, Maciej W. Rozycki wrote: > > Attempt to handle cases such as with a downstream port of the ASMedia > > ASM2824 PCIe switch where link training never completes and the link > > continues switching between speeds

Re: [PATCH] powerpc: isa-bridge: Fix ISA mmapping when "ranges" is not present

On 05 May 2023 at 07:18 pm, Rob Herring wrote: Commit e4ab08be5b49 ("powerpc/isa-bridge: Remove open coded "ranges" parsing") broke PASemi Nemo board booting. The issue is the ISA I/O range was not getting mapped as the logic to handle no "ranges" was inverted. If phb_io_base_phys is non-zero,