man.c
> @@ -2546,11 +2546,6 @@ int qman_delete_cgr(struct qman_cgr *cgr)
> }
> EXPORT_SYMBOL(qman_delete_cgr);
>
> -struct cgr_comp {
> - struct qman_cgr *cgr;
> - struct completion completion;
> -};
> -
> static void qman_delete_cgr_smp_call(void *p)
> {
> qman_delete_cgr((struct qman_cgr *)p);
Reviewed-by: Sean Anderson
_safe()")
CC: sta...@vger.kernel.org
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Resent from a non-mangling email.
(no changes since v3)
Changes in v3:
- Change blamed commit to something more appropriate
Changes in v2:
- Fix one addit
ltean
Closes: https://lore.kernel.org/all/20230323153935.nofnjucqjqnz34ej@skbuf/
Reported-by: Steffen Trumtrar
Closes: https://lore.kernel.org/linux-arm-kernel/87wmsyvclu@pengutronix.de/
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Changes in v5:
- Cl
On 3/5/24 17:18, Christophe Leroy wrote:
>
>
> Le 05/03/2024 à 19:14, Sean Anderson a écrit :
>> [Vous ne recevez pas souvent de courriers de sean.ander...@linux.dev.
>> Découvrez pourquoi ceci est important à
>> https://aka.ms/LearnAboutSenderIdentification ]
>
Hi,
On 2/23/24 11:02, Sean Anderson wrote:
> On 2/23/24 00:38, Christophe Leroy wrote:
>> Le 22/02/2024 à 18:07, Sean Anderson a écrit :
>>> [Vous ne recevez pas souvent de courriers de sean.ander...@linux.dev.
>>> Découvrez pourquoi ceci est impo
On 3/5/24 13:02, Rob Herring wrote:
>
> On Thu, 01 Feb 2024 13:29:30 -0600, Rob Herring wrote:
>> There is no reason to use RESERVEDMEM_OF_DECLARE() as the initialization
>> hook just saves off the base address and size. Use of
>> RESERVEDMEM_OF_DECLARE() is reserved for non-driver code and
>>
On 2/23/24 00:38, Christophe Leroy wrote:
> Le 22/02/2024 à 18:07, Sean Anderson a écrit :
>> [Vous ne recevez pas souvent de courriers de sean.ander...@linux.dev.
>> Découvrez pourquoi ceci est important à
>> https://aka.ms/LearnAboutSenderIdentification ]
>>
g/all/20230323153935.nofnjucqjqnz34ej@skbuf/
Reported-by: Steffen Trumtrar
Closes: https://lore.kernel.org/linux-arm-kernel/87wmsyvclu@pengutronix.de/
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Changes in v4:
- Add a note about how raw spinlocks aren't quite
_safe()")
CC: sta...@vger.kernel.org
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Resent from a non-mangling email.
(no changes since v3)
Changes in v3:
- Change blamed commit to something more appropriate
Changes in v2:
- Fix one addit
On 2/19/24 10:30, Vladimir Oltean wrote:
> Hi Sean,
>
> On Thu, Feb 15, 2024 at 11:23:26AM -0500, Sean Anderson wrote:
>> smp_call_function_single disables IRQs when executing the callback. To
>> prevent deadlocks, we must disable IRQs when taking cgr_lock elsewhere.
&g
_safe()")
CC: sta...@vger.kernel.org
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
I got no response the first time I sent this, so I am resending to net.
This issue was introduced in a series which went through net, so I hope
it makes sense to take
g/all/20230323153935.nofnjucqjqnz34ej@skbuf/
Reported-by: Steffen Trumtrar
Closes: https://lore.kernel.org/linux-arm-kernel/87wmsyvclu@pengutronix.de/
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Changes in v4:
- Add a note about how raw spinlocks aren't quite
On 1/8/24 11:19, Sean Anderson wrote:
> cgr_lock may be locked with interrupts already disabled by
> smp_call_function_single. As such, we must use a raw spinlock to avoid
> problems on PREEMPT_RT kernels. Although this bug has existed for a
> while, it was not apparent until commit
34ej@skbuf/
Reported-by: Steffen Trumtrar
Closes: https://lore.kernel.org/linux-arm-kernel/87wmsyvclu@pengutronix.de/
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Please backport these fixes when applied. This bug has been reported
multiple times (see links ab
_safe()")
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
(no changes since v3)
Changes in v3:
- Change blamed commit to something more appropriate
Changes in v2:
- Fix one additional call to spin_unlock
drivers/soc/fsl/qbman/qman.c | 10 +---
On 8/21/23 19:59, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 07:39:15PM -0400, Sean Anderson wrote:
>> Well, I think we should take the opportunity to think about the hardware
>> which exists and how we plan to model it. IMO grouping lanes into a
>> single phy simplifie
On 8/22/23 10:55, Ioana Ciornei wrote:
> On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> On 8/21/23 14:13, Ioana Ciornei wrote:
>> > On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
>> >> Well, we have two pieces of information we need
On 8/21/23 18:48, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 05:06:46PM -0400, Sean Anderson wrote:
>> On 8/21/23 15:58, Vladimir Oltean wrote:
>> > On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> >> After further review, it seems the r
On 8/21/23 15:58, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> After further review, it seems the reason 28g can get away without this
>> is because there's a one-to-one mapping between protocol controllers and
>> lanes. Unfortuna
On 8/21/23 14:13, Ioana Ciornei wrote:
> On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
>> Well, we have two pieces of information we need
>>
>> - What values do we need to program in the PCCRs to select a particular
>> mode? This includes whet
On 8/21/23 08:49, Vladimir Oltean wrote:
> Hi Sean,
>
> On Fri, Aug 11, 2023 at 07:36:37PM +0300, Vladimir Oltean wrote:
>> Let me explain that approach, because your mention of "swapping out the
>> bootloaders" makes it appear as if you are not visualising what I am
>> proposing.
>>
>> The Lynx
": "
>
> -/***/
> -
> -int fs_enet_platform_init(void);
> -void fs_enet_platform_cleanup(void);
> -
> /***/
> /* buffer descriptor access macros */
>
Reviewed-by: Sean Anderson
On 8/11/23 11:08, Vladimir Oltean wrote:
> Hi Sean,
>
> On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
>> > > At first sight you might appear to have a point related to the fact that
>> > > PLL register writes are necessary, and thus this whole shebang is
>> > > necessary.
>> >
Hi Vladimir,
On 8/10/23 06:26, Vladimir Oltean wrote:
> Hi Sean,
>
> On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
>> The way things are supposed to work (*if* this works at all) is that the
>> reset state machine starts with a supported PLL / refclk configuration
>> that
On 6/12/23 12:33, Vladimir Oltean wrote:
> On Mon, Jun 12, 2023 at 10:35:21AM -0400, Sean Anderson wrote:
>> > And if SERDES protocol switching was not physically possible, would this
>> > patch set still have value?
More to the point, did you make any progress in this area?
On 6/10/23 18:21, Vladimir Oltean wrote:
> Hello Sean,
>
> On Fri, Jun 09, 2023 at 03:19:22PM -0400, Sean Anderson wrote:
>> On 5/22/23 11:00, Vladimir Oltean wrote:
>> > On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
>> >> Have yo
On 5/22/23 11:00, Vladimir Oltean wrote:
> On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
>> Have you had a chance to review this driver?
>
> Partially / too little (and no, I don't have an answer yet). I am
> debugging a SERDES protocol change procedure from
Hi Vladmir,
On 5/1/23 11:03, Sean Anderson wrote:
> On 4/29/23 13:24, Vladimir Oltean wrote:
>> On Wed, Apr 26, 2023 at 10:50:17AM -0400, Sean Anderson wrote:
>>> > I need to catch up with 14 rounds of patches from you and with the
>>> > discussions that took plac
On 5/16/23 09:36, Vinod Koul wrote:
> On 08-05-23, 11:28, Sean Anderson wrote:
>> On 5/8/23 05:22, Vinod Koul wrote:
>> > On 13-04-23, 12:05, Sean Anderson wrote:
>
>> >> +static const struct lynx_cfg ls1088a_cfg = {
>> >> + .lane
On 5/16/23 09:22, Vinod Koul wrote:
> On 09-05-23, 11:26, Sean Anderson wrote:
>> On 5/9/23 09:00, Vinod Koul wrote:
>> > On 08-05-23, 11:31, Sean Anderson wrote:
>> >> On 5/8/23 05:15, Vinod Koul wrote:
>> >
>> >> >> +int
On 5/9/23 09:00, Vinod Koul wrote:
> On 08-05-23, 11:31, Sean Anderson wrote:
>> On 5/8/23 05:15, Vinod Koul wrote:
>
>> >> +int lynx_clks_init(struct device *dev, struct regmap *regmap,
>> >> +struct clk *plls[2], struct clk *ex_dlys[2],
On 5/8/23 05:15, Vinod Koul wrote:
> On 13-04-23, 12:05, Sean Anderson wrote:
>> This adds support for the PLLs found in Lynx 10G "SerDes" devices found on
>> various NXP QorIQ SoCs. There are two PLLs in each SerDes. This driver has
>> been split from the main
On 5/8/23 05:22, Vinod Koul wrote:
> On 13-04-23, 12:05, Sean Anderson wrote:
>> This adds support for the Lynx 10G "SerDes" devices found on various NXP
>> QorIQ SoCs. There may be up to four SerDes devices on each SoC, each
>> supporting up to eight lanes. P
On 4/29/23 13:24, Vladimir Oltean wrote:
> On Wed, Apr 26, 2023 at 10:50:17AM -0400, Sean Anderson wrote:
>> > I need to catch up with 14 rounds of patches from you and with the
>> > discussions that took place on each version, and understand how you
>> > responded
On 4/26/23 06:51, Vladimir Oltean wrote:
On Tue, Apr 25, 2023 at 04:22:32PM -0400, Sean Anderson wrote:
The features which do not work (major protocol changes) are disabled :)
If it would cause this series to be immediately merged, I would remove
KX/KR and 2.5G which are the only untested link
On 4/25/23 15:50, Vladimir Oltean wrote:
> Hello,
>
> On Thu, 13 Apr 2023 12:05:52 -0400, Sean Anderson wrote:
>> This series is ready for review by the phy maintainers. I have addressed
>> all known feedback and there are no outstanding issues.
>>
>> Major reco
On 4/18/23 02:29, Crystal Wood wrote:
> On Tue, 2023-04-11 at 11:09 -0400, Sean Anderson wrote:
>> Hi Crystal,
>>
>> On 4/4/23 12:04, Sean Anderson wrote:
>> > On 4/4/23 11:33, Crystal Wood wrote:
>> > > On Tue, 2023-04-04 at 10:55 -0400, Sean Anderson wr
The next few patches will break ethernet if the serdes is not enabled,
so enable the serdes driver by default on Layerscape.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- New
drivers/phy/freescale/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
to set the macs to
MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be
converted at once. Additionally, in order to change interface types, the
MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE.
Signed-off-by: Sean Anderson
---
(no changes since v13)
Changes in v13
dpmac1 defaults to a fixed link. However, it has an SFP cage, so we can
determine more about the link (such as whether it's up/down) by
describing it. The GPIOs are part of the "QIXIS" FPGA. For now, just
model them as individual registers.
Signed-off-by: Sean Anderson
---
(no changes
eld is determined by a
variable. In these cases, I have used traditional shift/mask techniques.
Signed-off-by: Sean Anderson
---
Changes in v14:
- Add note about (lack of) use of FIELD_GET/PREP
Changes in v10:
- Fix debugging print with incorrect error variable
Changes in v9:
- Split off clo
up/down delay (.5s on average).
Signed-off-by: Sean Anderson
---
(no changes since v13)
Changes in v13:
- Split interrupt changes off from serdes support
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
ations can be
blacklisted (or whitelisted). This may also be necessary for other SoCs
which have more stringent clock requirements.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Remove unnecessary inclusion of clk.h
- Don't gate clocks in compatibility mode
Changes in v9:
The internal PCSs are not always accessible during boot (such as if the
serdes has deselected the appropriate link mode). Give them appropriate
compatible strings so they don't automatically (fail to) probe as
genphys.
Signed-off-by: Sean Anderson
---
(no changes since v8)
Changes in v8
is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move
by the driver.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
(no changes since v6)
Changes in v6:
- frequence -> frequency
Changes in v5:
- Update commit description
- Dual id header
Changes in v4:
- New
include/dt-bindings/clock/fsl,lynx-10g.h | 14 ++
1 file changed,
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
, and some registers may be omitted. Because of this, reg-names
is mandatory, and no order is specified.
Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
has moved.
Signed-off-by: Sean Anderson
Reviewed-by: Linus Walleij
---
Linus or Bartosz, feel free to pick this up as the rest
NXP has a "QIXIS" FPGA on several of their reference design boards. On
the LS1088ARDB there are several registers which control GPIOs. These
can be modeled with the MMIO GPIO driver.
Signed-off-by: Sean Anderson
Reviewed-by: Rob Herring
---
(no changes since v10)
Changes in
earing group->pll after disabling it
- Support 1 and 2 phy-cells
- Power off lanes during probe
- Clear SGMIIaCR1_PCS_EN during probe
- Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
- Handle 1000BASE-KX in lynx_proto_mode_prep
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable S
. It is typically used to communicate directly with SFP+
modules, or with 10GBASE-T phys.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
PR increasing phy-type maximum [1].
If this commit could be applied sooner rather than later, I'd appreciate
it. This should help avoid another respin
re are two PLLs, each of which can be used as the master clock for
each lane. Each PLL has its own reference. For the moment they are
required, because it simplifies the driver implementation. Absent
reference clocks can be modeled by a fixed-clock with a rate of 0.
Signed-off-by: Sean Anderson
On 4/12/23 04:04, Krzysztof Kozlowski wrote:
> On 11/04/2023 20:43, Sean Anderson wrote:
>> This is a generic binding for simple MMIO GPIO controllers. Although we
>> have a single driver for these controllers, they were previously spread
>> over several files. Consolida
Hi Vinod,
On 4/12/23 12:10, Vinod Koul wrote:
On 11-04-23, 14:43, Sean Anderson wrote:
This adds support for the Lynx 10G "SerDes" devices found on various NXP
QorIQ SoCs. There may be up to four SerDes devices on each SoC, each
supporting up to eight lanes. Protocol support for e
Hi Vinod,
On 4/12/23 12:10, Vinod Koul wrote:
On 11-04-23, 14:43, Sean Anderson wrote:
This adds support for the Lynx 10G "SerDes" devices found on various NXP
QorIQ SoCs. There may be up to four SerDes devices on each SoC, each
supporting up to eight lanes. Protocol support for e
Hi Vinod,
On 4/12/23 12:10, Vinod Koul wrote:
On 11-04-23, 14:43, Sean Anderson wrote:
This adds support for the Lynx 10G "SerDes" devices found on various NXP
QorIQ SoCs. There may be up to four SerDes devices on each SoC, each
supporting up to eight lanes. Protocol support for e
dpmac1 defaults to a fixed link. However, it has an SFP cage, so we can
determine more about the link (such as whether it's up/down) by
describing it. The GPIOs are part of the "QIXIS" FPGA. For now, just
model them as individual registers.
Signed-off-by: Sean Anderson
---
Chan
to set the macs to
MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be
converted at once. Additionally, in order to change interface types, the
MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE.
Signed-off-by: Sean Anderson
---
Changes in v13:
- Split off interrupt and SFP
The internal PCSs are not always accessible during boot (such as if the
serdes has deselected the appropriate link mode). Give them appropriate
compatible strings so they don't automatically (fail to) probe as
genphys.
Signed-off-by: Sean Anderson
---
(no changes since v8)
Changes in v8
up/down delay (.5s on average).
Signed-off-by: Sean Anderson
---
Changes in v13:
- Split interrupt changes off from serdes support
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
b/arch
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
layout (using "banks" instead of
separate SerDes). Perhaps this those use a "5G Lynx SerDes."
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Fix debugging print with incorrect error variable
Changes in v9:
- Split off clock "driver" in
is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move
ations can be
blacklisted (or whitelisted). This may also be necessary for other SoCs
which have more stringent clock requirements.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Remove unnecessary inclusion of clk.h
- Don't gate clocks in compatibility mode
Changes in v9:
The next few patches will break ethernet if the serdes is not enabled,
so enable the serdes driver by default on Layerscape.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- New
drivers/phy/freescale/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
re are two PLLs, each of which can be used as the master clock for
each lane. Each PLL has its own reference. For the moment they are
required, because it simplifies the driver implementation. Absent
reference clocks can be modeled by a fixed-clock with a rate of 0.
Signed-off-by: Sean Anderson
, and some registers may be omitted. Because of this, reg-names
is mandatory, and no order is specified.
Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
has moved.
Signed-off-by: Sean Anderson
Reviewed-by: Linus Walleij
---
Linus or Bartosz, feel free to pick this up as the rest
. It is typically used to communicate directly with SFP+
modules, or with 10GBASE-T phys.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
PR increasing phy-type maximum [1].
If this commit could be applied sooner rather than later, I'd appreciate
it. This should help avoid another respin
by the driver.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
(no changes since v6)
Changes in v6:
- frequence -> frequency
Changes in v5:
- Update commit description
- Dual id header
Changes in v4:
- New
include/dt-bindings/clock/fsl,lynx-10g.h | 14 ++
1 file changed,
during probe
- Clear SGMIIaCR1_PCS_EN during probe
- Rename LYNX_PROTO_UNKNOWN to LYNX_PROTO_NONE
- Handle 1000BASE-KX in lynx_proto_mode_prep
- Use one phy cell for SerDes1, since no lanes can be grouped
- Disable SerDes by default to prevent breaking boards inadvertently.
Sean Anderson (15):
dt-bind
NXP has a "QIXIS" FPGA on several of their reference design boards. On
the LS1088ARDB there are several registers which control GPIOs. These
can be modeled with the MMIO GPIO driver.
Signed-off-by: Sean Anderson
Reviewed-by: Rob Herring
---
(no changes since v10)
Changes in
Hi Crystal,
On 4/4/23 12:04, Sean Anderson wrote:
> On 4/4/23 11:33, Crystal Wood wrote:
>> On Tue, 2023-04-04 at 10:55 -0400, Sean Anderson wrote:
>>
>>> @@ -1456,11 +1456,11 @@ static void tqm_congestion_task(struct work_struct
>>> *work)
>>> u
On 4/4/23 11:33, Crystal Wood wrote:
> On Tue, 2023-04-04 at 10:55 -0400, Sean Anderson wrote:
>
>> @@ -1456,11 +1456,11 @@ static void tqm_congestion_task(struct work_struct
>> *work)
>> union qm_mc_result *mcr;
>> struct qman_cgr *cgr;
>>
_safe()")
Signed-off-by: Sean Anderson
Reviewed-by: Camelia Groza
Tested-by: Vladimir Oltean
---
Changes in v3:
- Change blamed commit to something more appropriate
Changes in v2:
- Fix one additional call to spin_unlock
drivers/soc/fsl/qbman/qman.c | 10 +-
1 file changed, 5
hange") which invokes smp_call_function_single via
qman_update_cgr_safe every time a link goes up or down.
Fixes: 96f413f47677 ("soc/fsl/qbman: fix issue in qman_delete_cgr_safe()")
Reported-by: Vladimir Oltean
Link: https://lore.kernel.org/all/20230323153935.nofnjucqjqnz34ej@skbuf/
On 4/3/23 10:02, Vladimir Oltean wrote:
> On Fri, Mar 31, 2023 at 11:14:12AM -0400, Sean Anderson wrote:
>> smp_call_function_single disables IRQs when executing the callback. To
>> prevent deadlocks, we must disable IRQs when taking cgr_lock elsewhere.
>> This is already do
river")
Signed-off-by: Sean Anderson
---
Changes in v2:
- Fix one additional call to spin_unlock
drivers/soc/fsl/qbman/qman.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 739e4eee6b75..1b
hange") which invokes smp_call_function_single via
qman_update_cgr_safe every time a link goes up or down.
Fixes: c535e923bb97 ("soc/fsl: Introduce DPAA 1.x QMan device driver")
Reported-by: Vladimir Oltean
Link: https://lore.kernel.org/all/20230323153935.nofnjucqjqnz34ej@skbuf/
On 3/31/23 06:58, Camelia Alexandra Groza wrote:
>> -Original Message-
>> From: Sean Anderson
>> Sent: Monday, March 27, 2023 22:29
>> To: Leo Li ; linuxppc-dev@lists.ozlabs.org; linux-arm-
>> ker...@lists.infradead.org
>> Cc: Scott Wood ; linux-ker...@
On 3/28/23 05:25, Ioana Ciornei wrote:
> On Mon, Mar 27, 2023 at 02:15:47PM -0400, Sean Anderson wrote:
>> On 3/24/23 09:17, Ioana Ciornei wrote:
>> > On Tue, Mar 21, 2023 at 04:13:12PM -0400, Sean Anderson wrote:
>> >> This adds serdes support to the LS1088
On 3/27/23 14:15, Sean Anderson wrote:
> On 3/24/23 09:17, Ioana Ciornei wrote:
>> On Tue, Mar 21, 2023 at 04:13:12PM -0400, Sean Anderson wrote:
>>> This adds serdes support to the LS1088ARDB. I have tested the QSGMII
>>> ports as well as the two 10G ports. The SFP
hange") which invokes smp_call_function_single via
qman_update_cgr_safe every time a link goes up or down.
Fixes: c535e923bb97 ("soc/fsl: Introduce DPAA 1.x QMan device driver")
Reported-by: Vladimir Oltean
Link: https://lore.kernel.org/all/20230323153935.nofnjucqjqnz34ej@skbuf/
river")
Signed-off-by: Sean Anderson
---
drivers/soc/fsl/qbman/qman.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 739e4eee6b75..ff870ca07596 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drive
On 3/24/23 09:17, Ioana Ciornei wrote:
> On Tue, Mar 21, 2023 at 04:13:12PM -0400, Sean Anderson wrote:
>> This adds serdes support to the LS1088ARDB. I have tested the QSGMII
>> ports as well as the two 10G ports. The SFP slot is now fully supported,
>> instead of being mo
On 3/21/23 16:13, Sean Anderson wrote:
> This is a generic binding for simple MMIO GPIO controllers. Although we
> have a single driver for these controllers, they were previously spread
> over several files. Consolidate them. The register descriptions are
> adapted from the comments i
The internal PCSs are not always accessible during boot (such as if the
serdes has deselected the appropriate link mode). Give them appropriate
compatible strings so they don't automatically (fail to) probe as
genphys.
Signed-off-by: Sean Anderson
---
(no changes since v8)
Changes in v8
support, the DPC needs to set the macs to
MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be
converted at once. Additionally, in order to change interface types, the
MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE.
Signed-off-by: Sean Anderson
---
(no changes since v10
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
is gate them), so I have chosen to model it as a single
fixed clock.
Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move
This adds nodes for the SerDes devices. They are disabled by default
to prevent any breakage on existing boards.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Move serdes bindings to SoC dtsi
- Add support for all (ethernet) serdes modes
- Refer to "nodes&quo
The next few patches will break ethernet if the serdes is not enabled,
so enable the serdes driver by default on Layerscape.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- New
drivers/phy/freescale/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
ations can be
blacklisted (or whitelisted). This may also be necessary for other SoCs
which have more stringent clock requirements.
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Remove unnecessary inclusion of clk.h
- Don't gate clocks in compatibility mode
Changes in v9:
, and some registers may be omitted. Because of this, reg-names
is mandatory, and no order is specified.
Rename brcm,bcm6345-gpio to brcm,bcm63xx-gpio to reflect that bcm6345
has moved.
Signed-off-by: Sean Anderson
Reviewed-by: Linus Walleij
---
Linus or Bartosz, feel free to pick this up as the rest
layout (using "banks" instead of
separate SerDes). Perhaps this those use a "5G Lynx SerDes."
Signed-off-by: Sean Anderson
---
(no changes since v10)
Changes in v10:
- Fix debugging print with incorrect error variable
Changes in v9:
- Split off clock "driver" in
NXP has a "QIXIS" FPGA on several of their reference design boards. On
the LS1088ARDB there are several registers which control GPIOs. These
can be modeled with the MMIO GPIO driver.
Signed-off-by: Sean Anderson
Reviewed-by: Rob Herring
---
(no changes since v10)
Changes in
by the driver.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
(no changes since v6)
Changes in v6:
- frequence -> frequency
Changes in v5:
- Update commit description
- Dual id header
Changes in v4:
- New
include/dt-bindings/clock/fsl,lynx-10g.h | 14 ++
1 file changed,
re are two PLLs, each of which can be used as the master clock for
each lane. Each PLL has its own reference. For the moment they are
required, because it simplifies the driver implementation. Absent
reference clocks can be modeled by a fixed-clock with a rate of 0.
Signed-off-by: Sean Anderson
. It is typically used to communicate directly with SFP+
modules, or with 10GBASE-T phys.
Signed-off-by: Sean Anderson
Acked-by: Rob Herring
---
PR increasing phy-type maximum [1].
If this commit could be applied sooner rather than later, I'd appreciate
it. This should help avoid another respin
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