Excerpts from Miguel Ojeda's message of January 27, 2022 4:57 am:
> On Wed, Jan 26, 2022 at 4:03 PM Cédric Le Goater wrote:
>>
>> Indeed. I could reproduce.
>
> Thanks for the quick confirmation!
>
>> Could you please send the QEMU command line and the full dmesg ? and
>> possibly open an issue
Excerpts from Michael Ellerman's message of January 25, 2022 9:45 pm:
> Nicholas Piggin writes:
>> Per the ISA, a Trace interrupt is not generated for a system call
>> [vectored] instruction. Reject uprobes on such instructions as we are
>> not emulating a system call [vectored] instruction
Excerpts from naverao1's message of January 25, 2022 8:48 pm:
> On 2022-01-25 11:23, Christophe Leroy wrote:
>> Le 25/01/2022 à 04:04, Nicholas Piggin a écrit :
>>> +Naveen (sorry missed cc'ing you at first)
>>>
>>> Excerpts from Christophe Leroy's message of January 24, 2022 4:39 pm:
Excerpts from Fabiano Rosas's message of January 26, 2022 7:56 am:
> MMIO emulation can fail if the guest uses an instruction that we are
> not prepared to emulate. Since these instructions can be and most
> likely are valid ones, this is (slightly) closer to an access fault
> than to an illegal
The testcase uses event code 0x35340401e0 to verify
the settings for different fields in Monitor Mode Control
Register A (MMCRA). The fields include thresh_start, thresh_stop
thresh_select, sdar mode, sample and marked bit. Checks if
these fields are translated correctly via perf interface to
The testcase uses event code 0x134001c040 to verify
the settings for different src fields in Monitor Mode Control
Register 3 (MMCR3). Checks if these fields are translated
correctly via perf interface to MMCR3 on ISA v3.1 platform.
Signed-off-by: Kajol Jain
---
From: Madhavan Srinivasan
The testcases uses cycles event to verify the freeze counter
settings in Monitor Mode Control Register 2 (MMCR2). Event
modifier (exclude_kernel) setting is used for the event attribute
to check the FCxS and FCxH ( Freeze counter in privileged and
hypervisor state )
From: Madhavan Srinivasan
The testcases uses event code 0x01046080 to verify
the l2l3 bit setting for Monitor Mode Control Register 2
(MMCR2). check if this bit is set correctly via perf interface
in ISA v3.1 platform.
Signed-off-by: Madhavan Srinivasan
---
From: Athira Rajeev
The testcase uses event code "0x134001c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1
From: Athira Rajeev
The testcase uses event code "0x26880" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The field include PMCxCOMB.
Checks if this field are translated correctly via perf
interface to MMCR1
Add selftest for mmcr1 comb field.
From: Athira Rajeev
The testcase uses event code 0x500fa to verify the
FC5-6 bit setting in Monitor Mode Control Register 0 (MMCR0).
Check if FC5-6 bit is not set in MMCR0 when using Performance
Monitor Counter 5 and 6 (PMC5 and PMC6).
Signed-off-by: Athira Rajeev
---
From: Athira Rajeev
The testcase uses event code 0x1001e to verify two bit settings
(FC5-6 and PMC1CE) in Monitor Mode Control Register 0 (MMCR0).
Check if FC5-6 bit to be set in MMCR0 when not using Performance
Monitor Counter 5 and 6 (PMC5 and PMC6). And also PMC1CE is
expected to be set when
From: Athira Rajeev
The testcase uses event code 0x500fa ("instructions") to verify
the PMCjCE bit setting in Monitor Mode Control Register 0 (MMCR0).
This bit is expected to be set in MMCR0 when using Performance
Monitor Counter 5 (PMC5). Checks if perf interface sets this
bit correctly.
From: Athira Rajeev
The testcase uses cycles event to check the PMCCEXT
bit setting in Monitor Mode Control Register 0 (MMCR0).
Check if perf interface sets this control bit in MMCR0
on ISA v3.1 platform.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/Makefile | 4 +-
From: Athira Rajeev
The testcase uses "instructions" event to verify two
bits(PMAE and PMAO) in Monitor Mode Control Register 0
(MMCR0). At the time of interrupt, pmae bit ( which enables
performance monitor exception ) is expected to be cleared
and pmao (which indicates performance monitor
From: Athira Rajeev
The testcase uses event code 0x500fa ("instructions") to check
the CC56RUN bit setting in Monitor Mode Control Register 0(MMCR0).
In ISA v3.1 platform, this bit is expected to be set in MMCR0
when using Performance Monitor Counter 5 and 6 (PMC5 and PMC6).
Verify this is done
Add macro and utility functions to fetch individual
fields from Monitor Mode Control Register 3(MMCR3)and
Monitor Mode Control Register A(MMCRA) PMU registers
Signed-off-by: Kajol Jain
---
.../powerpc/pmu/sampling_tests/misc.h | 64 +++
1 file changed, 64 insertions(+)
From: Athira Rajeev
Add macro and utility functions to fetch individual
fields from Monitor Mode Control Register 0(MMCR0) and
Monitor Mode Control Register 1(MMCR1) PMU register.
Signed-off-by: Athira Rajeev
---
.../powerpc/pmu/sampling_tests/misc.h | 66 +++
1 file
From: Madhavan Srinivasan
Generic macro (GET_MMCR_FIELD) added to extract specific fields of
a given MMCRx. Along with it, patch also adds macro and utility
functions to fetch individual fields from
Monitor Mode Control Register 2(MMCR2) register.
Signed-off-by: Madhavan Srinivasan
---
From: Madhavan Srinivasan
Extended event_init_opts() to include initialization
of sampling testcases. Patch adds an event_init_sampling()
wrapper to initialize event attribute fields for sampling
events. This includes initializing sample period, sample type
and event type.
Signed-off-by:
Add couple of basic utility functions to post process the
mmap buffer. It includes function to read the total
number of samples present in the mmap buffer and function
to get the address of the first sample.
Add function "get_intr_regs" which will return pointer to
interrupt registers present in
From: Madhavan Srinivasan
Each platform has raw event encoding format which specifies
the bit positions for different fields. The fields from event
code gets translated into performance monitoring mode control
register (MMCRx) settings. Patch add macros to extract individual
fields from the
From: Athira Rajeev
Add support functions for enabling perf sampling test in
a new folder "sampling_tests" under "selftests/powerpc/pmu".
This includes support functions for allocating and processing
the mmap buffer. These functions are added/defined in
"sampling_tests/misc.*" files.
Also
Patch series adds support for perf sampling tests that
enables capturing sampling data in perf mmap buffer and
further support for reading and processing the samples.
It also addds basic utility functions to process the
mmap buffer inorder to read total count of samples as
well as the contents of
From: Athira Rajeev
To enable the capturing of samples as part of perf event,
add a new field "mmap_buffer" to "struct event". This
field is a place-holder for sample collection
Signed-off-by: Athira Rajeev
---
tools/testing/selftests/powerpc/pmu/event.h | 5 +
1 file changed, 5
On 2022/1/27 10:54, Kai-Heng Feng wrote:
Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
hint") enables ACS, and some platforms lose its NVMe after resume from
S3:
[ 50.947816] pcieport :00:1b.0: DPC: containment event, status:0x1f01
source:0x
[ 50.947817]
On Thu, Jan 27, 2022 at 08:29:22AM +0200, Mika Westerberg wrote:
> > For example, should we convert commit a697f072f5da8 ("PCI: Disable PTM
> > during suspend to save power") to PM hooks in PTM service?
>
> Yes, I think that's the right thing to do. I wonder how it was not using
> the PM hooks in
On Thu, Jan 27, 2022 at 10:54:18AM +0800, Kai-Heng Feng wrote:
> Since TLP and DLLP transmission is disabled for a Link in L2/L3 Ready,
> L2 and L3 (i.e. device in D3hot and D3cold), and DPC depends on AER, so
> also disable DPC here.
>
> Signed-off-by: Kai-Heng Feng
Reviewed-by: Mika
On Thu, Jan 27, 2022 at 10:54:17AM +0800, Kai-Heng Feng wrote:
> Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
> hint") enables ACS, and some platforms lose its NVMe after resume from
> S3:
> [ 50.947816] pcieport :00:1b.0: DPC: containment event, status:0x1f01
>
Hi,
On Thu, Jan 27, 2022 at 10:21:35AM +0800, Kai-Heng Feng wrote:
> On Wed, Jan 26, 2022 at 7:03 PM Mika Westerberg
> wrote:
> >
> > Hi,
> >
> > On Wed, Jan 26, 2022 at 03:18:51PM +0800, Kai-Heng Feng wrote:
> > > Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
> > > hint")
Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
hint") enables ACS, and some platforms lose its NVMe after resume from
S3:
[ 50.947816] pcieport :00:1b.0: DPC: containment event, status:0x1f01
source:0x
[ 50.947817] pcieport :00:1b.0: DPC: unmasked
Since TLP and DLLP transmission is disabled for a Link in L2/L3 Ready,
L2 and L3 (i.e. device in D3hot and D3cold), and DPC depends on AER, so
also disable DPC here.
Signed-off-by: Kai-Heng Feng
---
v2:
- Wording change.
- Empty line dropped.
drivers/pci/pcie/dpc.c | 60
On Wed, Jan 26, 2022 at 7:10 PM Mika Westerberg
wrote:
>
> Hi,
>
> On Wed, Jan 26, 2022 at 03:18:52PM +0800, Kai-Heng Feng wrote:
> > Since TLP and DLLP transmission is disabled for a Link in L2/L3 Ready,
> > L2 and L3, and DPC depends on AER, so also disable DPC here.
>
> Here too I think it is
On Wed, Jan 26, 2022 at 7:03 PM Mika Westerberg
wrote:
>
> Hi,
>
> On Wed, Jan 26, 2022 at 03:18:51PM +0800, Kai-Heng Feng wrote:
> > Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
> > hint") enables ACS, and some platforms lose its NVMe after resume from
> > S3:
> > [
On Mon, Jan 24, 2022 at 09:22:15AM +, Christophe Leroy wrote:
> within_module_core() and within_module_init() are doing the exact same
> test, one on core_layout, the second on init_layout.
>
> In preparation of increasing the complexity of that verification,
> refactor it into a single
The timekeeping subsystem could use some reorganization. Reorganize and
separate the headers by making ktime.h take care of the ktime_get()
family of functions, and reserve timekeeping.h for the actual timekeeping.
This also helps to avoid implicit function errors and strengthens the
header
David, et al --
...and then David Laight said...
%
% From: Paul Menzel
% > Sent: 26 January 2022 11:42
% >
% ..
% > +pound := \#
%
% Please use 'hash' not 'pound'.
Ahem ... Everyone knows that hash is best served hot and that
that symbol is an octothorpe.
% Only american greengrocers use
Hi Michael!
On 1/13/22 01:17, John Paul Adrian Glaubitz wrote:
> On 1/9/22 23:17, John Paul Adrian Glaubitz wrote:
>> On 1/7/22 12:20, John Paul Adrian Glaubitz wrote:
Can you separately test with (on the host):
# echo 0 > /sys/module/kvm_hv/parameters/dynamic_mt_modes
>>>
>>> I'm
On Wed, Jan 26, 2022 at 4:03 PM Cédric Le Goater wrote:
>
> Indeed. I could reproduce.
Thanks for the quick confirmation!
> Could you please send the QEMU command line and the full dmesg ? and
> possibly open an issue on :
>
>https://gitlab.com/qemu-project/qemu/-/issues/
>
> I guess it's a
On 1/26/22 15:16, Miguel Ojeda wrote:
Hi PPC folks,
Our ppc64le CI deterministically triggers a hard lockup / hang under
QEMU since v5.17-rc1 (upgrading from v5.16).
Bisecting points to 0faf20a1ad16 ("powerpc/64s/interrupt: Don't enable
MSR[EE] in irq handlers unless perf is in use").
Hi,
Steve pointed me at this thread over IRC -- I'm not subscribed to this list so
grabbed a copy of the thread thus far via b4.
On Tue, Jan 25, 2022 at 11:20:27AM +0800, Yinan Liu wrote:
> > Yeah, I think it's time to opt in, instead of opting out.
I agree this must be opt-in rather than
Hi PPC folks,
Our ppc64le CI deterministically triggers a hard lockup / hang under
QEMU since v5.17-rc1 (upgrading from v5.16).
Bisecting points to 0faf20a1ad16 ("powerpc/64s/interrupt: Don't enable
MSR[EE] in irq handlers unless perf is in use").
Cheers,
Miguel
[ 16.328310] watchdog: CPU 1
On Wed, Jan 26, 2022 at 12:21:49PM +, Christophe Leroy wrote:
> The code is enclosed in a #ifdef CONFIG_PPC64, it is not used for PPC32:
>
> /arch/powerpc/include/asm/bug.h
>99 #ifdef CONFIG_PPC64
Ah...
You know, life would be a lot easier for me personally if we added an
#ifndef
On Mon, Jan 17, 2022 at 08:42:57PM -0800, Walt Drummond wrote:
> This patchset adds TTY status message request feature to the n_tty
> line dicipline. This feature prints a brief message containing basic
> system and process group information to a user's TTY in response to a
> new control
Hi Michael,
Commit e432fe97f3e5 ("powerpc/bug: Cast to unsigned long before passing
to inline asm") breaks WARN_ON() for 32 bit systems.
arch/powerpc/include/asm/bug.h
109 #define WARN_ON(x) ({ \
110 bool __ret_warn_on = false;
Hi Dan,
Le 26/01/2022 à 12:56, Dan Carpenter a écrit :
>
> Hi Michael,
>
> Commit e432fe97f3e5 ("powerpc/bug: Cast to unsigned long before passing
> to inline asm") breaks WARN_ON() for 32 bit systems.
I think you missed commit db87a7199229 ("powerpc/bug: Remove specific
powerpc BUG_ON() and
Dear David,
Am 26.01.22 um 13:06 schrieb David Laight:
From: Paul Menzel
Sent: 26 January 2022 11:42
..
+pound := \#
Please use 'hash' not 'pound'.
Only american greengrocers use that horrid name.
A 'pound' is '£'.
Sure, I can change that, if you send a patch cleaning this up for the
From: Paul Menzel
> Sent: 26 January 2022 11:42
>
..
> +pound := \#
Please use 'hash' not 'pound'.
Only american greengrocers use that horrid name.
A 'pound' is '£'.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT,
UK
Registration No: 1397386
On Ubuntu 21.10 (ppc64le) building `raid6test` with gcc (Ubuntu
11.2.0-7ubuntu2) 11.2.0 fails with the error below.
$ cd lib/raid6/test
$ make
[…]
gcc -I.. -I ../../../include -g -O2
-I../../../arch/powerpc/include -DCONFIG_ALTIVEC -o raid6test test.c raid6.a
On Ubuntu 21.10 (ppc64le) building `raid6test` with gcc (Ubuntu
11.2.0-7ubuntu2) 11.2.0 fails with the error below.
gcc -I.. -I ../../../include -g -O2
-I../../../arch/powerpc/include -DCONFIG_ALTIVEC -c -o vpermxor1.o vpermxor1.c
vpermxor1.c: In function
Buidling `raid6test` on Ubuntu 21.10 (ppc64le) with GNU Make 4.3 shows the
errors below:
$ cd lib/raid6/test/
$ make
:1:1: error: stray ‘\’ in program
:1:2: error: stray ‘#’ in program
:1:11: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or ‘__attribute__’
before ‘<’ token
cp -f
Hi,
On Wed, Jan 26, 2022 at 03:18:52PM +0800, Kai-Heng Feng wrote:
> Since TLP and DLLP transmission is disabled for a Link in L2/L3 Ready,
> L2 and L3, and DPC depends on AER, so also disable DPC here.
Here too I think it is good to mention that the DPC "service" never
implemented the PM hooks
Hi,
On Wed, Jan 26, 2022 at 03:18:51PM +0800, Kai-Heng Feng wrote:
> Commit 50310600ebda ("iommu/vt-d: Enable PCI ACS for platform opt in
> hint") enables ACS, and some platforms lose its NVMe after resume from
> S3:
> [ 50.947816] pcieport :00:1b.0: DPC: containment event, status:0x1f01
>
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