[PATCH] powerpc/pseries/iommu: Split Dynamic DMA Window to be used in Hybrid mode

2024-05-13 Thread Gaurav Batra
. Maximum size possible DDW is created as permitted by the Hypervisor. Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/include/asm/iommu.h | 2 + arch/powerpc/platforms/pseries/iommu.c | 71 -- 2 files changed, 56 insertions(+), 17 deletions(-) diff

[PATCH v2] powerpc/pseries/iommu: LPAR panics during boot up with a frozen PE

2024-04-22 Thread Gaurav Batra
kernel_init_freeable+0x344/0x3e4 kernel_init+0x34/0x1d0 ret_from_kernel_user_thread+0x14/0x1c Fixes: b1fc44eaa9ba ("pseries/iommu/ddw: Fix kdump to work in absence of ibm,dma-window") Signed-off-by: Gaurav Batra --- arch/powerpc/platforms/pseries/iommu.c | 8 +

Re: [PATCH] powerpc/pseries/iommu: LPAR panics when rebooted with a frozen PE

2024-04-19 Thread Gaurav Batra
at 04:12:46PM +1000, Michael Ellerman wrote: Gaurav Batra writes: At the time of LPAR reboot, partition firmware provides Open Firmware property ibm,dma-window for the PE. This property is provided on the PCI bus the PE is attached to. AFAICS you're actually describing a bug that happens during bo

[PATCH] powerpc/pseries/iommu: LPAR panics when rebooted with a frozen PE

2024-04-16 Thread Gaurav Batra
kernel_init_freeable+0x344/0x3e4 kernel_init+0x34/0x1d0 ret_from_kernel_user_thread+0x14/0x1c Fixes: b1fc44eaa9ba ("pseries/iommu/ddw: Fix kdump to work in absence of ibm,dma-window") Signed-off-by: Gaurav Batra --- arch/powerpc/platforms/pseries/iommu.c | 8 +

[PATCH v3] powerpc/pseries/iommu: DLPAR ADD of pci device doesn't completely initialize pci_controller structure

2024-02-15 Thread Gaurav Batra
controller structure is allocated but there are no calls made to iommu_device_register() interface. Fix would be to register iommu device during DLPAR ADD as well. Fixes: a940904443e4 ("powerpc/iommu: Add iommu_ops to report capabilities and allow blocking domains") Signed-off-by: Ga

Re: [PATCH] powerpc/pseries/iommu: DLPAR ADD of pci device doesn't completely initialize pci_controller structure

2024-02-07 Thread Gaurav Batra
Hello All, There is still some issue even after applying the patch. This is not a complete fix. I am working on V3 of the patch. Please do not merge this patch upstream. Thanks, Gaurav On 1/10/24 4:53 PM, Gaurav Batra wrote: When a PCI device is Dynamically added, LPAR OOPS with NULL

[PATCH v2] powerpc/pseries/iommu: IOMMU table is not initialized for kdump over SR-IOV

2024-01-25 Thread Gaurav Batra
From: Gaurav Batra When kdump kernel tries to copy dump data over SR-IOV, LPAR panics due to NULL pointer execption. Here is the complete stack [ 19.944378] Kernel attempted to read user page (0) - exploit attempt? (uid: 0)^M [ 19.944388] BUG: Kernel NULL pointer dereference on read

[PATCH v2] powerpc/pseries/iommu: DLPAR ADD of pci device doesn't completely initialize pci_controller structure

2024-01-22 Thread Gaurav Batra
controller structure is allocated but there are no calls made to iommu_device_register() interface. Fix would be to register iommu device during DLPAR ADD as well. Fixes: a940904443e4 ("powerpc/iommu: Add iommu_ops to report capabilities and allow blocking domains") Signed-off-by: Gau

[PATCH] powerpc/pseries/iommu: DLPAR ADD of pci device doesn't completely initialize pci_controller structure

2024-01-10 Thread Gaurav Batra
controller structure is allocated but there are no calls made to iommu_device_register() interface. Fix would be to register iommu device during DLPAR ADD as well. Fixes: a940904443e4 ("powerpc/iommu: Add iommu_ops to report capabilities and allow blocking domains") Signed-off-by: Gau

Re: [PATCH] powerpc/pseries/iommu: IOMMU table is not initialized for kdump over SR-IOV

2023-12-14 Thread Gaurav Batra
On 12/14/23 4:18 AM, Aneesh Kumar K.V wrote: Gaurav Batra writes: When kdump kernel tries to copy dump data over SR-IOV, LPAR panics due to NULL pointer execption. Here is the complete stack [ 19.944378] Kernel attempted to read user page (0) - exploit attempt? (uid: 0)^M [ 19.944388

[PATCH] powerpc/pseries/iommu: IOMMU table is not initialized for kdump over SR-IOV

2023-12-13 Thread Gaurav Batra
kdump to succeed. Fixes: b1fc44eaa9ba ("pseries/iommu/ddw: Fix kdump to work in absence of ibm,dma-window") Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/platforms/pseries/iommu.c | 150 - 1 file changed, 99 insertions(+), 51

[PATCH v2] powerpc/pseries/iommu: enable_ddw incorrectly returns direct mapping for SR-IOV device

2023-10-02 Thread Gaurav Batra
DW for indirect mapping") Cc: sta...@vger.kernel.org Signed-off-by: Gaurav Batra --- arch/powerpc/platforms/pseries/iommu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 16d93b

[PATCH] powerpc/pseries/iommu: enable_ddw incorrectly returns direct mapping for SR-IOV device.

2023-10-02 Thread Gaurav Batra
When a device is initialized, the driver invokes dma_supported() twice - first for streaming mappings followed by coherent mappings. For an SR-IOV device, default window is deleted and DDW created. With vPMEM enabled, TCE mappings are dynamically created for both vPMEM and SR-IOV device. There are

Re: [PATCH] powerpc/iommu: TCEs are incorrectly manipulated with DLPAR add/remove of memory

2023-06-26 Thread Gaurav Batra
Thanks a lot On 6/25/23 11:54 PM, Michael Ellerman wrote: Gaurav Batra writes: Hello Michael, Did you get a chance to look into this patch? I don't mean to rush you. Just wondering if there is anything I can do to help make the patch to Upstream. I skimmed it and decided it wasn't

Re: [PATCH] powerpc/iommu: TCEs are incorrectly manipulated with DLPAR add/remove of memory

2023-06-23 Thread Gaurav Batra
Hello Michael, Did you get a chance to look into this patch? I don't mean to rush you. Just wondering if there is anything I can do to help make the patch to Upstream. Thanks, Gaurav On 6/13/23 12:17 PM, Gaurav Batra wrote: Hello Michael, I found this bug while going though the code

Re: [PATCH] powerpc/iommu: TCEs are incorrectly manipulated with DLPAR add/remove of memory

2023-06-13 Thread Gaurav Batra
ce I would need to hack kernel to force dynamically added TCEs to the high IO Bus Addresses. But, the concept isĀ  same. Thanks, Gaurav On 6/13/23 12:16 PM, Gaurav Batra wrote: When memory is dynamically added/removed, iommu_mem_notifier() is invoked. This routine traverses through all the DMA wi

[PATCH] powerpc/iommu: TCEs are incorrectly manipulated with DLPAR add/remove of memory

2023-06-13 Thread Gaurav Batra
This will wipe out those TCEs. The solution is for iommu_mem_notifier() to only invoke these routines for "direct" mapped DMA windows. Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/platforms/pseries/iommu.c | 17 + 1 file changed, 13 insertio

Re: [PATCH v2] powerpc/iommu: limit number of TCEs to 512 for H_STUFF_TCE hcall

2023-05-25 Thread Gaurav Batra
rrent form since the beginning. Cc: sta...@vger.kernel.org Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/platforms/pseries/iommu.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/plat

[PATCH v2] powerpc/iommu: limit number of TCEs to 512 for H_STUFF_TCE hcall

2023-05-25 Thread Gaurav Batra
...@vger.kernel.org Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/platforms/pseries/iommu.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index c74b71d4733d..f159a195101d

Re: [PATCH] powerpc/iommu: limit number of TCEs to 512 for H_STUFF_TCE hcall

2023-05-22 Thread Gaurav Batra
On 5/17/23 7:19 AM, Michael Ellerman wrote: Gaurav Batra writes: Hello Michael, System test hit the crash. I believe, it was PHYP that resulted in it due to number of TCEs passed in to be >512. OK. It's always good to spell out in the change log whether it's a theoretical/unlikely

Re: [PATCH v2] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-05-22 Thread Gaurav Batra
, Sorry I missed this. Please share the link to the your fix, I do not see it in my mail. In general, the problem can probably be solved by using huge pages (anything more than 64K) only for 1:1 mapping. On 03/05/2023 13:25, Gaurav Batra wrote: Hello Alexey, I recently joined IOMMU team

Re: [PATCH] powerpc/iommu: limit number of TCEs to 512 for H_STUFF_TCE hcall

2023-05-11 Thread Gaurav Batra
d I mention the first commit which created this source file? Thanks a lot for looking into it. Gaurav On 5/11/23 9:35 PM, Michael Ellerman wrote: Gaurav Batra writes: As of now, in tce_freemulti_pSeriesLP(), there is no limit on how many TCEs are passed to H_STUFF_TCE hcall. PAPR is enforc

[PATCH] powerpc/iommu: limit number of TCEs to 512 for H_STUFF_TCE hcall

2023-05-09 Thread Gaurav Batra
As of now, in tce_freemulti_pSeriesLP(), there is no limit on how many TCEs are passed to H_STUFF_TCE hcall. PAPR is enforcing this to be limited to 512 TCEs. Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/platforms/pseries/iommu.c | 12 ++-- 1 file changed, 10

[PATCH] iommu/powerpc: Incorrect DDW Table is referenced for SR-IOV device

2023-05-05 Thread Gaurav Batra
le pointer is passed in. Fixes: 381ceda88c4c ("powerpc/pseries/iommu: Make use of DDW for indirect mapping") Signed-off-by: Gaurav Batra Reviewed-by: Brian King --- arch/powerpc/kernel/dma-iommu.c| 4 +++- arch/powerpc/platforms/pseries/iommu.c | 13 + 2 files changed,

Re: [PATCH v2] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-05-04 Thread Gaurav Batra
ot;. Which essentially means, that a "rogue" device/driver has the potential to corrupt LPAR wide memory. I have sent you v3. Thanks, Gaurav On 5/4/23 12:10 AM, Michael Ellerman wrote: Gaurav Batra writes: Hello Michael, I was looking into the Bug: 199106 (https://bugzilla.linux.ibm

[PATCH v3] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-05-04 Thread Gaurav Batra
port, when DMA window is backed by 2MB TCEs. Fixes: 387273118714 ("powerps/pseries/dma: Add support for 2M IOMMU page size") Signed-off-by: Gaurav Batra Reviewed-by: Greg Joyce Reviewed-by: Brian King --- arch/powerpc/kernel/iommu.c | 11 +++ 1 file changed, 7 insert

Re: [PATCH v2] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-05-02 Thread Gaurav Batra
will resolve Srikar and Mellanox driver issues. The problem is with 2MB DDW. Since you have extensive knowledge of IOMMU design and code, in your opinion, which patch should we adopt? Thanks a lot Gaurav On 4/20/23 2:45 PM, Gaurav Batra wrote: Hello Michael, I was looking into the Bug: 199106 (https

Re: [PATCH v2] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-04-20 Thread Gaurav Batra
. In case we decide to go with my patch, I just realized that I need to fix nio_pages in iommu_free_coherent() as well. Thanks, Gaurav On 4/20/23 10:21 AM, Michael Ellerman wrote: Gaurav Batra writes: When DMA window is backed by 2MB TCEs, the DMA address for the mapped page should

[PATCH v2] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-04-19 Thread Gaurav Batra
port, when DMA window is backed by 2MB TCEs. Fixes: 3872731187141d5d0a5c4fb30007b8b9ec36a44d Signed-off-by: Gaurav Batra Reviewed-by: Greg Joyce Reviewed-by: Brian King --- arch/powerpc/kernel/iommu.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc

[PATCH] powerpc/iommu: DMA address offset is incorrectly calculated with 2MB TCEs

2023-04-19 Thread Gaurav Batra
port, when DMA window is backed by 2MB TCEs. Signed-off-by: Gaurav Batra Reviewed-by: Greg Joyce Reviewed-by: Brian King --- arch/powerpc/kernel/iommu.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index