xujuntwt95329 wrote:
> > Hi @mh4ck-Thales this is caused by [#77949
> > (comment)](https://github.com/llvm/llvm-project/pull/77949#discussion_r1463458728),
> > currently we need to modify it manually.
>
> Thanks! That did the trick for the breakpoint and disassembly problems. When
> using
Lewuathe wrote:
@joker-eph Oh, sorry for bothering you. I'll check what's going on.
https://github.com/llvm/llvm-project/pull/76316
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fhahn wrote:
@Enna1 thanks, should be fixed by 1b37e8087e1e1ecf5aadd8da536ee17dc21832e2. Bot
should be back to green
https://github.com/llvm/llvm-project/pull/73158
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https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
mordante wrote:
> @mordante I guess the PR missed LLVM18 release. I'll update the release notes
> accordingly. Is that OK?
Yes. It would have been nice to get this in LLVM 18, but I don't feel it's
critical to backport it. (Especially since it's a C++26 only feature and I
expect very few
RamaMalladiAWS wrote:
> Hello. Can you explain why this is needed, as opposed to using the equivalent
> shift/and/ors?
Hi @davemgreen, one of AWS customers requested for such an intrinsic to be made
available so that they could consume it their IR directly. The reasoning they
had was to use
@@ -4216,6 +4217,95 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
https://github.com/SunilKuravinakop updated
https://github.com/llvm/llvm-project/pull/79475
>From 6614e517cf0888b4502efc0af974d1612fa7a822 Mon Sep 17 00:00:00 2001
From: Sunil Kuravinakop
Date: Thu, 25 Jan 2024 10:37:20 -0600
Subject: [PATCH 1/2] Changes to Support Parsing & Sema of atomic
Enna1 wrote:
Hi @fhahn
I think this change introduce a memory leak in `VPlan::duplicate()`, see
https://lab.llvm.org/buildbot/#/builders/168/builds/18308/steps/10/logs/stdio
Can you take a look?
https://github.com/llvm/llvm-project/pull/73158
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davemgreen wrote:
Hello. Can you explain why this is needed, as opposed to using the equivalent
shift/and/ors?
https://github.com/llvm/llvm-project/pull/79672
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https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672
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@@ -2558,6 +2558,14 @@ def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
(EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
+def SDT_AArch64BFI_32bit : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1,
i32>,
+
https://github.com/inclyc commented:
Also I kindly wonder if this intrinsic is necessary for optimization/codegen.
Why not prefer inline assembly?
https://github.com/llvm/llvm-project/pull/79672
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https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672
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