[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

https://github.com/FreddyLeaf approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84491 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/84598 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

llvmbot wrote: @llvm/pr-subscribers-lld-elf @llvm/pr-subscribers-lld Author: Paul Kirth (ilovepi) Changes This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute specified in:

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Paul Kirth (ilovepi) Changes This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute specified in: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value It adds

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/84598 This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute specified in: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value It adds

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Daniel Paoliello (dpaoliello) Changes Backports fixes to be able to generate import libraries for ARM64EC: * https://github.com/llvm/llvm-project/pull/78769; * https://github.com/llvm/llvm-project/pull/81059; *

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

llvmbot wrote: @llvm/pr-subscribers-llvm-binary-utilities Author: Daniel Paoliello (dpaoliello) Changes Backports fixes to be able to generate import libraries for ARM64EC: * https://github.com/llvm/llvm-project/pull/78769; * https://github.com/llvm/llvm-project/pull/81059; *

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

https://github.com/dpaoliello created https://github.com/llvm/llvm-project/pull/84590 Backports fixes to be able to generate import libraries for ARM64EC: * * *

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/84404 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/84404 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

https://github.com/dpaoliello updated https://github.com/llvm/llvm-project/pull/81800 >From 064dd621c19b3738af5db29afd5b986a6d739ab1 Mon Sep 17 00:00:00 2001 From: Billy Laws Date: Wed, 31 Jan 2024 02:32:15 + Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

[llvm-branch-commits] [llvm] Remove RC suffix (PR #84430)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/84430 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] dba2a75 - Bump version to 18.1.1

Author: Tom Stellard Date: 2024-03-07T21:27:31-08:00 New Revision: dba2a75e9c7ef81fe84774ba5eee5e67e01d801a URL: https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a DIFF: https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a.diff

[llvm-branch-commits] [llvm] b92012c - Remove RC suffix

Author: Tobias Hieta Date: 2024-03-07T21:18:24-08:00 New Revision: b92012c777e602d557124583651313a0afa33484 URL: https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484 DIFF: https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484.diff

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

llvmbot wrote: @topperc What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84566 Backport 755b439694432d4f68e20e979b479cbc30602bb1 Requested by: @brad0 >From 86b5745e27533404e61912f0233ab38307174025 Mon Sep 17 00:00:00 2001 From: yingopq <115543042+ying...@users.noreply.github.com> Date:

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

https://github.com/JonPsson1 updated https://github.com/llvm/llvm-project/pull/84560 >From 639dceb13cf824e3f4e0f627becf8fb8f5ecb29c Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Fri, 8 Mar 2024 15:28:56 -0500 Subject: [PATCH] SystemZ release notes. --- clang/docs/ReleaseNotes.rst | 5

[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

llvmbot wrote: @llvm/pr-subscribers-lld Author: Jonas Paulsson (JonPsson1) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/84560.diff 3 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+5) - (modified) lld/docs/ReleaseNotes.rst (+6) - (modified)

[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

https://github.com/JonPsson1 created https://github.com/llvm/llvm-project/pull/84560 None >From b6bd83cace58517531380eb4e34594bddc973153 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Fri, 8 Mar 2024 15:28:56 -0500 Subject: [PATCH] SystemZ release notes. --- clang/docs/ReleaseNotes.rst

[llvm-branch-commits] [llvm] 9db26e9 - Revert "[IR] Add new Range attribute using new ConstantRange Attribute type (…"

Author: Florian Mayer Date: 2024-03-08T11:34:52-08:00 New Revision: 9db26e987297a6406adb5e0c80a6c2a93c59ade6 URL: https://github.com/llvm/llvm-project/commit/9db26e987297a6406adb5e0c80a6c2a93c59ade6 DIFF: https://github.com/llvm/llvm-project/commit/9db26e987297a6406adb5e0c80a6c2a93c59ade6.diff

[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Fixes naming inconsistency. (#83036) (PR #83156)

mordante wrote: I assume it will then be in 18.1.1 in a few weeks. https://github.com/llvm/llvm-project/pull/83156 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/84491 >From 54e01706d1764b689c8eb1ed4b173cca26b5f9ed Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 10:15:43 +0800 Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720)

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

llvmbot wrote: @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) Changes Backport ff72c83b017b Requested by: @johnplatts --- Full diff: https://github.com/llvm/llvm-project/pull/84491.diff 3 Files Affected: - (modified) llvm/lib/Target/X86/X86InstrVecCompiler.td (+3) -

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

llvmbot wrote: @FreddyLeaf What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/84491 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/84491 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/84491 Backport ff72c83b017b Requested by: @johnplatts >From d7a7ea38a011646ad9dc18f9c045e66df7296c39 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 4 Mar 2024 10:15:43 +0800 Subject: [PATCH] [X86] Add missing

[llvm-branch-commits] [llvm] release/18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

llvmbot wrote: @llvm/pr-subscribers-backend-arm Author: AtariDreams (AtariDreams) Changes This fixes a register allocation bug, because while r7 was marked as allowed to be used, LivePhysRegs always reported it as unavailable because it is reserved, despite this being an exception to

[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Fixes naming inconsistency. (#83036) (PR #83156)

mathstuf wrote: This missed 18.1.0 :( . https://github.com/llvm/llvm-project/pull/83156 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

https://github.com/AtariDreams edited https://github.com/llvm/llvm-project/pull/84475 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release 18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

https://github.com/AtariDreams created https://github.com/llvm/llvm-project/pull/84475 This fixes a register allocation bug, because while r7 was marked as allowed to be used, LivePhysRegs always reported it as unavailable because it is reserved, despite this being an exception to the rule.

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/lukel97 commented: Is this NFC? https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

https://github.com/wangpc-pp converted_to_draft https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Wang Pengcheng (wangpc-pp) Changes Reduce some duplications and make it easy to follow. We can optimize segment copies later. --- Full diff: https://github.com/llvm/llvm-project/pull/84455.diff 1 Files Affected: - (modified)

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84455 Reduce some duplications and make it easy to follow. We can optimize segment copies later. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang] [llvm] [LV][LAA] Vectorize math lib calls with mem write-only attribute (PR #78432)

https://github.com/paschalis-mpeis converted_to_draft https://github.com/llvm/llvm-project/pull/78432 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

https://github.com/jeanPerier edited https://github.com/llvm/llvm-project/pull/84376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

https://github.com/jeanPerier commented: Thanks for identifying the issue https://github.com/llvm/llvm-project/pull/84376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

@@ -208,7 +208,12 @@ class BoxedProcedurePass mlir::IRRewriter rewriter(context); BoxprocTypeRewriter typeConverter(mlir::UnknownLoc::get(context)); mlir::Dialect *firDialect = context->getLoadedDialect("fir"); - getModule().walk([&](mlir::Operation *op)

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Wang Pengcheng (wangpc-pp) Changes The opcode will be determined by LMUL. --- Full diff: https://github.com/llvm/llvm-project/pull/84448.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+26-26) -

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/84448 The opcode will be determined by LMUL. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

@@ -51,21 +51,40 @@ Improvements to clangd Inlay hints ^^^ +- Type hints +* Improved heuristics for showing sugared vs. desguared types +* Some hints which provide no information (e.g. ) are now omitted +- Parameter hints +* Parameter hints are now

[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

https://github.com/kadircet approved this pull request. thanks a lot for doing this @HighCommander4 ! https://github.com/llvm/llvm-project/pull/84436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

https://github.com/kadircet edited https://github.com/llvm/llvm-project/pull/84436 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits