[Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

Intel/AMD's hardware instructions do not handle arguments of 32. Constant evaluation should not produce a result different from the hardware instruction. --- src/glsl/nir/nir_opcodes.py | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/glsl/nir/nir_opcodes.py

[Mesa-dev] [PATCH 2/9] glsl: Delete the ir_binop_bfm and ir_triop_bfi opcodes.

From: Kenneth Graunke TGSI doesn't use these - it just translates ir_quadop_bitfield_insert directly. NIR can handle ir_quadop_bitfield_insert as well. These opcodes were only used for i965, and with Jason's recent patches, we can do this lowering in NIR (which also

[Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

If a Python codegen script failed, it would write a zero-byte file, which on subsequent invocations of make would trick it into thinking the file was appropriately generated. --- src/glsl/Makefile.am | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z); result.w =

[Mesa-dev] [PATCH 9/9] i965: Use nir_fixup_bitfield_insert_extract().

Fixes: ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2 ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3 ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595 --- src/mesa/drivers/dri/i965/brw_nir.c | 1 +

[Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's ir_binop_bfm takes as src0 and as src1. --- src/glsl/nir/nir_opcodes.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py index d31507f..398ae50 100644 ---

[Mesa-dev] [PATCH 6/9] glsl: Fix undefined shifts.

Shifting into the sign bit if undefined, as is shifting by 32. Reviewed-by: Jordan Justen --- src/glsl/ir_constant_expression.cpp | 8 src/glsl/nir/nir_opcodes.py | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 4/9] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldExtract(src0.x, src1.x, src2.x); result.y = bitfieldExtract(src0.y, src1.y, src2.y); result.z = bitfieldExtract(src0.z, src1.z, src2.z); result.w = bitfieldExtract(src0.w, src1.w,

[Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

The OpenGL specifications for bitfieldInsert() and bitfieldExtract() says: The result will be undefined if or is negative, or if the sum of and is greater than the number of bits used to store the operand. Therefore passing bits=32, offset=0 is legal and defined in GLSL. But the

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 6:33 PM, Dave Airlie wrote: > On 12 January 2016 at 03:04, Rob Clark wrote: >> On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: >>> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >>> >>>

Re: [Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

Yes, please! Reviewed-by: Ian Romanick On 01/11/2016 02:48 PM, Matt Turner wrote: > If a Python codegen script failed, it would write a zero-byte file, > which on subsequent invocations of make would trick it into thinking the > file was appropriately generated. > ---

Re: [Mesa-dev] [PATCH] glsl: track total amount of uniform locations used

On Mon, 2016-01-11 at 08:24 +0200, Tapani Pälli wrote: > > On 01/08/2016 11:32 AM, Tapani Pälli wrote: > > > > > > On 01/08/2016 11:17 AM, Timothy Arceri wrote: > > > On Fri, 2016-01-08 at 08:20 +0200, Tapani Pälli wrote: > > > > Linker missed a check for situation where we exceed max amount >

Re: [Mesa-dev] [PATCH 0/2] trivial cleanups

On Mon, Jan 11, 2016 at 11:50 PM, Timothy Arceri wrote: > On Mon, 2016-01-11 at 16:35 +0100, Erik Faye-Lund wrote: >> Ping? >> > > The other patch is also now > Reviewed-by: Timothy Arceri > > I take it you don't have commit access? Thanks.

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 3:25 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 6:18 PM, Ilia Mirkin wrote: >> On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: >>> On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin

Re: [Mesa-dev] [PATCH] nvc0/ir: be careful about propagating very large offsets into const load

On Mon, Jan 11, 2016 at 4:46 PM, Ilia Mirkin wrote: > Indirect constbuf indexing works by using very large offsets. However if > an indirect constbuf index load is const-propagated, it becomes a very > large const offset. Take that into account when legalizing the SSA by >

Re: [Mesa-dev] NIR, SCons, and Gallium

On 12 January 2016 at 03:04, Rob Clark wrote: > On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: >> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >> >> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >> >> It was actually

[Mesa-dev] [PATCH] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldExtract(src0.x, src1.x, src2.x); result.y = bitfieldExtract(src0.y, src1.y, src2.y); result.z = bitfieldExtract(src0.z, src1.z, src2.z); result.w = bitfieldExtract(src0.w, src1.w,

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: >> From: Kenneth Graunke >> >> We would like to be able to combine >> >>result.x = bitfieldInsert(src0.x, src1.x,

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Brian Paul changed: What|Removed |Added Component|Other |New Accounts

Re: [Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

On Mon, Jan 11, 2016 at 3:52 PM, Ian Romanick wrote: > On 01/11/2016 02:48 PM, Matt Turner wrote: >> NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's >> ir_binop_bfm takes as src0 and as src1. > > All the questions... > > Is the ordering of the operands

[Mesa-dev] [PATCH] nvc0: remove useless goto in nvc0_launch_grid()

Trivial. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c

[Mesa-dev] [PATCH] glsl: Make read_from_write_only_variable_visitor ignore .length().

.length() on an unsized SSBO variable doesn't actually read any data from the SSBO, and is allowed on variables marked 'writeonly'. Fixes compute shader compilation in Shadow of Mordor. Signed-off-by: Kenneth Graunke --- src/glsl/ast_to_hir.cpp | 9 + 1 file

Re: [Mesa-dev] NIR, SCons, and Gallium

On 01/11/2016 04:11 PM, Ian Romanick wrote: > On 01/11/2016 06:21 AM, Jose Fonseca wrote: >> So what is exactly the long term plan for NIR in Mesa general, and >> Gallium in particular? >> - replace GLSL IR completely? > > Not likely. GLSL IR has a lot of GLSL-specific semantics that aren't >

[Mesa-dev] [PATCH] i965: Mark TCS URB writes as having side effects.

This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing reads and writes from being incorrectly scheduled. Fixes rendering in GFXBench 4.0's tessellation demo. For some reason, we haven't ever listed URB writes as having side-effects. This hasn't been a problem because in most

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Ian Romanick changed: What|Removed |Added Status|NEW |ASSIGNED

[Mesa-dev] [PATCH] nvc0: do not force re-binding of compute constbufs on Fermi

Re-binding compute constant buffers after launching a grid have no effects because they are not currently validated and because dirty_cp is not updated accordingly. This might also prevent weird future behaviours when UBOs will be binded for compute. Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On 01/11/2016 04:14 PM, Matt Turner wrote: > On Mon, Jan 11, 2016 at 4:01 PM, Ian Romanick wrote: >> On 01/11/2016 02:48 PM, Matt Turner wrote: >>> Intel/AMD's hardware instructions do not handle arguments of 32. >>> Constant evaluation should not produce a result different

Re: [Mesa-dev] [PATCH 0/2] trivial cleanups

On Mon, 2016-01-11 at 16:35 +0100, Erik Faye-Lund wrote: > Ping? > The other patch is also now Reviewed-by: Timothy Arceri I take it you don't have commit access? > On Wed, Dec 16, 2015 at 5:09 PM, Erik Faye-Lund > wrote: > > Here's some

Re: [Mesa-dev] [PATCH] i965: Mark TCS URB writes as having side effects.

Reviewed-by: Chris Forbes On Tue, Jan 12, 2016 at 12:04 PM, Kenneth Graunke wrote: > This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing > reads and writes from being incorrectly scheduled. > > Fixes rendering in GFXBench 4.0's

Re: [Mesa-dev] [PATCH 07/18] meta/blit: Save and restore the sampler using gl_sampler_object instead of GL API object handle

On 01/09/2016 12:48 PM, Jason Ekstrand wrote: > > On Jan 8, 2016 6:59 PM, "Ian Romanick" > wrote: >> >> From: Ian Romanick > >> >> Some meta operations can be called recursively.

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 --- Comment #1 from Erik Faye-Lund --- Created attachment 120971 --> https://bugs.freedesktop.org/attachment.cgi?id=120971=edit SSH public key -- You are receiving this mail because: You are the QA Contact for the bug.

Re: [Mesa-dev] [PATCH] nvc0: do not force re-binding of compute constbufs on Fermi

On Mon, Jan 11, 2016 at 6:42 PM, Samuel Pitoiset wrote: > Re-binding compute constant buffers after launching a grid have no effects > because they are not currently validated and because dirty_cp is not updated > accordingly. This might also prevent weird future

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On 01/11/2016 02:48 PM, Matt Turner wrote: > Intel/AMD's hardware instructions do not handle arguments of 32. > Constant evaluation should not produce a result different from the > hardware instruction. > --- > src/glsl/nir/nir_opcodes.py | 9 ++--- > 1 file changed, 6 insertions(+), 3

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On Mon, Jan 11, 2016 at 4:01 PM, Ian Romanick wrote: > On 01/11/2016 02:48 PM, Matt Turner wrote: >> Intel/AMD's hardware instructions do not handle arguments of 32. >> Constant evaluation should not produce a result different from the >> hardware instruction. >> --- >>

[Mesa-dev] [PATCH] nvc0/ir: be careful about propagating very large offsets into const load

Indirect constbuf indexing works by using very large offsets. However if an indirect constbuf index load is const-propagated, it becomes a very large const offset. Take that into account when legalizing the SSA by moving the high parts of that offset into the file index. Also disallow very large

Re: [Mesa-dev] [PATCH 02/18] mesa: Add _mesa_set_sampler_filters method

On 01/09/2016 12:49 PM, Jason Ekstrand wrote: > > On Jan 8, 2016 6:59 PM, "Ian Romanick" > wrote: >> >> From: Ian Romanick > >> >> Signed-off-by: Ian Romanick

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: > On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: >> On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: >>> From: Kenneth Graunke >>> >>> We would like

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Bug ID: 93673 Summary: New account request Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority:

[Mesa-dev] [PATCHv3 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z); result.w =

Re: [Mesa-dev] NIR, SCons, and Gallium

On 01/11/2016 06:21 AM, Jose Fonseca wrote: > FWIW, I updated SCons to build NIR, both with GCC and MSVC: > > http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir > > It was actually simpler than I anticipated. > > But I hit a wall -- there's actually no way to get NIR used with >

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); >result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); >

Re: [Mesa-dev] [PATCH] nvc0: remove useless goto in nvc0_launch_grid()

Reviewed-by: Ilia Mirkin On Mon, Jan 11, 2016 at 6:12 PM, Samuel Pitoiset wrote: > Trivial. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 10 -- > 1 file changed,

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 6:18 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: >> On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: >>> On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner

Re: [Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

On 01/11/2016 02:48 PM, Matt Turner wrote: > NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's > ir_binop_bfm takes as src0 and as src1. All the questions... Is the ordering of the operands documented anywhere? I was only able to deduce this by looking at glsl_to_nir.cpp (and

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 3:33 PM, Matt Turner wrote: > Thanks. I apparently picked whatever tab completed first and was an > Snorm test, so it didn't trigger the assertion. > > I can reproduce this. I'll look into it. Okay, twas easy. Just needed to sprinkle 'u' around in a

[Mesa-dev] [PATCH] nvc0: allow fragment shader inputs to use indirect indexing

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 1f5e48e..e69e9cb 100644

Re: [Mesa-dev] [PATCH 6/9] glsl: Fix undefined shifts.

On 01/11/2016 02:48 PM, Matt Turner wrote: > Shifting into the sign bit if undefined, as is shifting by 32. > > Reviewed-by: Jordan Justen > --- > src/glsl/ir_constant_expression.cpp | 8 > src/glsl/nir/nir_opcodes.py | 6 +++--- > 2 files changed, 7

Re: [Mesa-dev] [PATCH] glsl: Make read_from_write_only_variable_visitor ignore .length().

On Mon, Jan 11, 2016 at 4:15 PM, Kenneth Graunke wrote: > .length() on an unsized SSBO variable doesn't actually read any data > from the SSBO, and is allowed on variables marked 'writeonly'. > > Fixes compute shader compilation in Shadow of Mordor. > > Signed-off-by:

Re: [Mesa-dev] [PATCH 1/7] glsl: enable offset layout qualifier for ARB_enhanced_layouts

This series is, Reviewed-by: Edward O'Callaghan On 2016-01-11 14:13, Timothy Arceri wrote: --- src/glsl/glsl_parser.yy | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 6b634f2..b2b94f4

Re: [Mesa-dev] radeon cmask sync with EGL/GBM

On 10/01/2016 19:38, Jay Cornwall wrote: Hi, Using EGL with the GBM platform it is possible to bind a GBM surface to a GL renderbuffer. I believe it's also valid to use the GBM BO as a framebuffer target with drmModeAddFB/drmModePageFlip. I haven't been able to locate a clear statement on

Re: [Mesa-dev] [PATCH] glsl: add image_format check in cross_validate_globals()

Reviewed-by: Tapani Pälli On 01/05/2016 03:32 PM, Samuel Iglesias Gonsálvez wrote: Fixes CTS test: ES31-CTS.shader_image_load_store.negative-linkErrors Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93410 Signed-off-by: Samuel Iglesias Gonsálvez

Re: [Mesa-dev] [PATCH 1/3] gallium/st: add pipe_context::generate_mipmap()

On Mon, Jan 11, 2016 at 9:31 PM, Charmaine Lee wrote: > This patch adds a new interface to support hardware mipmap generation. > PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify > if this new interface is supported; if not supported, the state tracker will >

Re: [Mesa-dev] [PATCH] glsl: track total amount of uniform locations used

On 01/12/2016 12:30 AM, Timothy Arceri wrote: On Mon, 2016-01-11 at 08:24 +0200, Tapani Pälli wrote: On 01/08/2016 11:32 AM, Tapani Pälli wrote: On 01/08/2016 11:17 AM, Timothy Arceri wrote: On Fri, 2016-01-08 at 08:20 +0200, Tapani Pälli wrote: Linker missed a check for situation where

[Mesa-dev] [Bug 93667] Crash in eglCreateImageKHR with huge texture size

https://bugs.freedesktop.org/show_bug.cgi?id=93667 Martin Gräßlin changed: What|Removed |Added CC||mgraess...@kde.org

Re: [Mesa-dev] [PATCH 1/3] gallium/st: add pipe_context::generate_mipmap()

On 12.01.2016 15:18, Charmaine Lee wrote: > This patch adds a new interface to support hardware mipmap generation. > PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify > if this new interface is supported; if not supported, the state tracker will > fallback to mipmap generation by

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

The type of the resulting variable is `uint64_t` not `unsigned long long`. To use ULL on constants one should also use `unsigned long long` everywhere else in Mesa. Mixing uint64_t and unsigned long long seems sloppy to me, as these types could potentially be different things on different

[Mesa-dev] [PATCH] nv50/ir: replace the right def in global cse

GlobalCSE looks for phi nodes with identically-defined sources, and replaces them with one of the (identical) instructions. However the defining instruction might have multiple defs, so we have to replace the one that the original phi node was pointing at. Observed when playing around with

Re: [Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

On Mon, Jan 11, 2016 at 10:04 PM, Connor Abbott wrote: > On Tue, Jan 12, 2016 at 12:54 AM, Matt Turner wrote: > > On Mon, Jan 11, 2016 at 6:58 PM, Jason Ekstrand > wrote: > >> > >> On Jan 11, 2016 2:47 PM, "Matt Turner"

[Mesa-dev] [PATCH 04/10] mesa/main: add USAGE_PIXEL_PACK_BUFFER flag to buffer UsageHistory

From: Nicolai Hähnle We will want to disable minmax index caching for buffers that are used in this way. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák --- src/mesa/main/bufferobj.c | 9 +

[Mesa-dev] [PATCH 1/3] gallium/st: add pipe_context::generate_mipmap()

This patch adds a new interface to support hardware mipmap generation. PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify if this new interface is supported; if not supported, the state tracker will fallback to mipmap generation by rendering/texturing. ---

[Mesa-dev] [PATCH 02/10] util/hash_table: add _mesa_hash_table_num_entries

From: Nicolai Hähnle --- src/mesa/main/hash.c | 4 +--- src/util/hash_table.h | 5 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c index 315b5d6..ab1b9e9 100644 --- a/src/mesa/main/hash.c +++

[Mesa-dev] [PATCH 3/3] svga: add DXGenMips command support

For those formats that support hw mipmap generation, use the DXGenMips command. Otherwise fallback to the mipmap generation utility. Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench) --- src/gallium/drivers/svga/svga_cmd.h | 4 ++

Re: [Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

On Jan 11, 2016 2:47 PM, "Matt Turner" wrote: > > The OpenGL specifications for bitfieldInsert() and bitfieldExtract() says: > >The result will be undefined if or is negative, or if >the sum of and is greater than the number of bits >used to store the operand.

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 7:40 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 7:11 PM, Ian Romanick wrote: >> On 01/11/2016 06:21 AM, Jose Fonseca wrote: >>> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >>> >>>

Re: [Mesa-dev] [PATCH] nv50/ir: replace the right def in global cse

Actually this is still a little bogus... We'd have to ensure that *all* of the defs are used in this bb or later. I'll try to come up with something that still maintains some of the potential benefit but is correct. On Mon, Jan 11, 2016 at 10:06 PM, Ilia Mirkin wrote: >

Re: [Mesa-dev] [PATCH] nv50/ir: replace the right def in global cse

On Tue, Jan 12, 2016 at 12:04 AM, Connor Abbott wrote: > On Mon, Jan 11, 2016 at 11:44 PM, Ilia Mirkin wrote: >> Actually this is still a little bogus... We'd have to ensure that >> *all* of the defs are used in this bb or later. I'll try to come up >>

Re: [Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

On Mon, Jan 11, 2016 at 6:58 PM, Jason Ekstrand wrote: > > On Jan 11, 2016 2:47 PM, "Matt Turner" wrote: >> >> The OpenGL specifications for bitfieldInsert() and bitfieldExtract() says: >> >>The result will be undefined if or is negative, or if >>

Re: [Mesa-dev] [PATCH 1/3] gallium/st: add pipe_context::generate_mipmap()

>From: ibmir...@gmail.com on behalf of Ilia Mirkin > >Sent: Monday, January 11, 2016 7:12 PM >To: Charmaine Lee >Cc: mesa-dev@lists.freedesktop.org >Subject: Re: [Mesa-dev] [PATCH 1/3] gallium/st: add >pipe_context::generate_mipmap() >On Mon, Jan 11,

[Mesa-dev] [Bug 93653] Crash while using GALLIUM_HUD

https://bugs.freedesktop.org/show_bug.cgi?id=93653 Michel Dänzer changed: What|Removed |Added Component|DRM/Radeon |Mesa core

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: > FWIW, I updated SCons to build NIR, both with GCC and MSVC: > > http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir > > It was actually simpler than I anticipated. > > But I hit a wall -- there's actually no

Re: [Mesa-dev] [PATCH] glsl: track total amount of uniform locations used

On Tue, 2016-01-12 at 07:59 +0200, Tapani Pälli wrote: > > On 01/12/2016 12:30 AM, Timothy Arceri wrote: > > On Mon, 2016-01-11 at 08:24 +0200, Tapani Pälli wrote: > > > > > > On 01/08/2016 11:32 AM, Tapani Pälli wrote: > > > > > > > > > > > > On 01/08/2016 11:17 AM, Timothy Arceri wrote: > >

[Mesa-dev] [PATCH 00/10] vbo: introduce a minmax_index cache (v3)

Hi, here is a new version of the series. I'm calling it v3 even though I never sent v2 because it contains v3 of the main patch. Changes relative to v1: - disable cache on USAGE_TEXTURE_BUFFER and bool/GLboolean nit - disable cache only temporarily when a persistent writable mapping exists - add

Re: [Mesa-dev] [PATCH] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

Reviewed-by: Ilia Mirkin On Mon, Jan 11, 2016 at 7:13 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldExtract(src0.x, src1.x, src2.x); >result.y =

[Mesa-dev] [PATCH 2/3] svga: add num-generate-mipmap HUD query

The actual increment of the num-generate-mipmap counter will be done in a subsequent patch when hw generate mipmap is supported. --- src/gallium/drivers/svga/svga_context.h| 4 +++- src/gallium/drivers/svga/svga_pipe_query.c | 7 +++ src/gallium/drivers/svga/svga_screen.c | 2 ++ 3

[Mesa-dev] [PATCH 07/10] vbo: cache/memoize the result of vbo_get_minmax_indices (v3)

From: Nicolai Hähnle Some games developers are unaware that an index buffer in a VBO still needs to be read by the CPU if some varying data comes from a user pointer (unless glDrawRangeElements and friends are used). This is particularly bad when they tell us that the

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 7:11 PM, Ian Romanick wrote: > On 01/11/2016 06:21 AM, Jose Fonseca wrote: >> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >> >> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >> >> It was actually simpler than I

Re: [Mesa-dev] [PATCHv3 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 7:12 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); >result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); >

[Mesa-dev] [PATCH] draw: fix key comparison with uninitialized value

From: Roland Scheidegger Discovered by accident, valgrind was complaining (could have possibly caused us to create redundant geometry shader variants). --- src/gallium/auxiliary/draw/draw_llvm.c | 3 +++ src/gallium/auxiliary/draw/draw_llvm.h | 5 + 2 files changed, 8

[Mesa-dev] [PATCH] st/mesa: fix incorrect buffer token passed to _mesa_BindFramebuffer()

I added this code right at the end, and got it wrong. Only used by the WGL_ARB_render_texture code. --- src/mesa/state_tracker/st_copytex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/state_tracker/st_copytex.c b/src/mesa/state_tracker/st_copytex.c index

[Mesa-dev] [PATCH 06/10] vbo: move vbo_get_minmax_indices into its own source file

From: Nicolai Hähnle We will add more code for caching/memoization. Moving the existing code into its own file helps keep things modular. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák --- src/mesa/Makefile.sources

Re: [Mesa-dev] [PATCH] st/mesa: fix incorrect buffer token passed to _mesa_BindFramebuffer()

Reviewed-by: Charmaine Lee From: Brian Paul Sent: Monday, January 11, 2016 5:24 PM To: mesa-dev@lists.freedesktop.org Cc: Charmaine Lee; Jose Fonseca Subject: [PATCH] st/mesa: fix incorrect buffer token passed to

[Mesa-dev] [PATCH 09/10] vbo: disable the minmax cache when the hit rate is low

From: Nicolai Hähnle When applications stream their index buffers, the caches for those BOs become useless and add overhead, so we want to disable them. The tricky part is coming up with the right heuristic for *when* to disable them. The first question is which hit

[Mesa-dev] [PATCH 01/10] util/hash_table: add _mesa_hash_table_clear

From: Nicolai Hähnle Reviewed-by: Ian Romanick --- src/util/hash_table.c | 25 ++ src/util/hash_table.h | 2 + src/util/tests/hash_table/Makefile.am | 1 + src/util/tests/hash_table/clear.c | 91

[Mesa-dev] [PATCH 03/10] mesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory

From: Nicolai Hähnle We will want to disable minmax index caching for buffers that are used in this way. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák --- src/mesa/main/mtypes.h| 1 +

[Mesa-dev] [Bug 27512] Illegal instruction _mesa_x86_64_transform_points4_general

https://bugs.freedesktop.org/show_bug.cgi?id=27512 --- Comment #15 from Michael Harder --- It worked for a few days but now I get this: [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". Core was generated

[Mesa-dev] [PATCH 10/10] mesa: add MESA_NO_MINMAX_CACHE environment variable

From: Nicolai Hähnle When set to a truish value, this globally disables the minmax cache for all buffer objects. No #ifdef DEBUG guards because this option can be interesting for benchmarking. --- docs/envvars.html | 1 + src/mesa/main/bufferobj.c | 22

[Mesa-dev] [PATCH 08/10] mesa: add USAGE_DISABLE_MINMAX_CACHE flag to buffer UsageHistory

From: Nicolai Hähnle --- src/mesa/main/mtypes.h | 1 + src/mesa/vbo/vbo_minmax_index.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 7285bc0..cfa11e8 100644 ---

Re: [Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

Thanks! On Jan 11, 2016 3:57 PM, "Ian Romanick" wrote: > Yes, please! > > Reviewed-by: Ian Romanick > > On 01/11/2016 02:48 PM, Matt Turner wrote: > > If a Python codegen script failed, it would write a zero-byte file, > > which on subsequent

Re: [Mesa-dev] [PATCH 01/10] util/hash_table: add _mesa_hash_table_clear

On Mon, Jan 11, 2016 at 6:32 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Reviewed-by: Ian Romanick > --- > src/util/hash_table.c | 25 ++ > src/util/hash_table.h | 2 + >

Re: [Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

On Tue, Jan 12, 2016 at 12:54 AM, Matt Turner wrote: > On Mon, Jan 11, 2016 at 6:58 PM, Jason Ekstrand wrote: >> >> On Jan 11, 2016 2:47 PM, "Matt Turner" wrote: >>> >>> The OpenGL specifications for bitfieldInsert() and

[Mesa-dev] [PATCH 1/3] gallium/st: add pipe_context::generate_mipmap()

This patch adds a new interface to support hardware mipmap generation. PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify if this new interface is supported; if not supported, the state tracker will fallback to mipmap generation by rendering/texturing. v2: add PIPE_CAP_GENERATE_MIPMAP

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 9:53 PM, Connor Abbott wrote: > On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: >> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >> >> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >> >> It was

Re: [Mesa-dev] [PATCH] nv50/ir: replace the right def in global cse

On Mon, Jan 11, 2016 at 11:44 PM, Ilia Mirkin wrote: > Actually this is still a little bogus... We'd have to ensure that > *all* of the defs are used in this bb or later. I'll try to come up > with something that still maintains some of the potential benefit but > is

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On 11/01/16 21:07, Oded Gabbay wrote: The ISO C99 standard (7.18.4) specifies that C++ implementations should define UINT64_C only when __STDC_CONSTANT_MACROS is defined. ecause we now use UINT64_C in our cpp files (since commit 208bfc493debe0344d0b9cb93975981f14412628), we need to add this

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On Mon, Jan 11, 2016 at 11:24 PM, Jose Fonseca wrote: > On 11/01/16 21:07, Oded Gabbay wrote: >> >> The ISO C99 standard (7.18.4) specifies that C++ >> implementations should define UINT64_C only when >> __STDC_CONSTANT_MACROS is defined. >> >> ecause we now use UINT64_C in

[Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

The ISO C99 standard (7.18.4) specifies that C++ implementations should define UINT64_C only when __STDC_CONSTANT_MACROS is defined. ecause we now use UINT64_C in our cpp files (since commit 208bfc493debe0344d0b9cb93975981f14412628), we need to add this define. This also solves compilation

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

I'm not strictly opposed to passing this in, but... why not just fix it by removing that imho weird macro and instead use ULL suffix on literals? On Mon, Jan 11, 2016 at 4:07 PM, Oded Gabbay wrote: > The ISO C99 standard (7.18.4) specifies that C++ > implementations should

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On Mon, Jan 11, 2016 at 11:09 PM, Ilia Mirkin wrote: > I'm not strictly opposed to passing this in, but... why not just fix > it by removing that imho weird macro and instead use ULL suffix on > literals? Well, I thought about it, but because I didn't add that macro to the

[Mesa-dev] [Bug 93667] Crash in eglCreateImageKHR with huge texture size

https://bugs.freedesktop.org/show_bug.cgi?id=93667 Bug ID: 93667 Summary: Crash in eglCreateImageKHR with huge texture size Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

[Mesa-dev] NIR, SCons, and Gallium

FWIW, I updated SCons to build NIR, both with GCC and MSVC: http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir It was actually simpler than I anticipated. But I hit a wall -- there's actually no way to get NIR used with softpipe/llvmpipe, not even as an intermediate IR somewhere

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