Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

On Tuesday, May 8, 2018 10:02:22 AM PDT Scott D Phillips wrote: > Kenneth Graunke <kenn...@whitecape.org> writes: [snip] > > + /* If this node is now completely full, remove it from the free list. */ > > + if (node->bitmap == 0ull) { > > + (void) util

Re: [Mesa-dev] gcc bug / crash in ast_type_qualifier::validate_in_qualifier()?

On Tuesday, May 8, 2018 1:23:32 AM PDT Eero Tamminen wrote: > Hi, > > On 08.05.2018 06:45, Matt Turner wrote: > > On Mon, May 7, 2018 at 8:02 PM, Brian Paul wrote: > >> > >> I don't know when this started happening (I'll try bisecting tomorrow) but > >> we're seeing a crash in

Re: [Mesa-dev] [PATCH 1/8] i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE

On Tuesday, May 8, 2018 8:07:36 AM PDT Jason Ekstrand wrote: > On Mon, May 7, 2018 at 11:44 PM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > > On Monday, May 7, 2018 12:49:32 PM PDT Jason Ekstrand wrote: > > > --- > > > src/mesa/drivers/dri/i965/

Re: [Mesa-dev] [PATCH 1/2] intel/isl: Several UNORM formats support typed writes on gen11+

On Monday, May 7, 2018 2:56:40 PM PDT Jason Ekstrand wrote: > --- > src/intel/isl/isl_format.c | 26 +- > 1 file changed, 13 insertions(+), 13 deletions(-) Awesome, thanks for taking care of this. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

Re: [Mesa-dev] [PATCH 8/8] i965/miptree: Remove redundant fields from intel_miptree_aux_buffer

ee this done with ISL finally, and good riddance to multiple atoms, vtable entries, prototypes, and piles of manual OUT_BATCH. Thanks for taking care of this! Series is: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally s

Re: [Mesa-dev] [PATCH 1/8] i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE

On Monday, May 7, 2018 12:49:32 PM PDT Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/gen7_misc_state.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c > b/src/mesa/drivers/dri/i965/gen7_misc_state.c > index

Re: [Mesa-dev] [PATCH 09/10] i965: Softpin all buffers and never use relocations.

On Thursday, May 3, 2018 11:51:52 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:39) > > --- > > src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > This enables it for Broadwell (

Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

On Saturday, May 5, 2018 12:25:20 AM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:36) [snip] > > +static uint64_t > > +bucket_vma_alloc(struct brw_bufmgr *bufmgr, > > + struct bo_cache_bucket *bucket, > > + e

[Mesa-dev] [PATCH 3/3] intel/genxml: Assert that genxml field start and ends are sane.

Chris recently fixed a bunch of genxml end < start bugs, as well as booleans that are wider than a bit. These are way too easy to write, so asserting that the fields are sane is a good plan. --- src/intel/genxml/gen_pack_header.py | 7 +++ 1 file changed, 7 insertions(+) diff --git

[Mesa-dev] [PATCH 2/3] intel/genxml: Fix some more fake booleans in genxml.

None of these are actually booleans. Tile Parameter is a tiling mode enum. Display pipes take plane numbers. Predicate Enable has some operations (and the default value of 6 was particular bogus). --- src/intel/genxml/gen10.xml | 4 ++-- src/intel/genxml/gen11.xml | 10 +-

[Mesa-dev] [PATCH 1/3] intel/genxml: Make assert in gen_pack_header print a message.

Python's assert can take both a condition and a string, which will cause it to print the string if the assertion trips. (You can't use parens as that creates a tuple.) Doing "condition and string" works in C, but doesn't have the desired effect in Python. --- src/intel/genxml/gen_pack_header.py

Re: [Mesa-dev] A question about nir_lower_wpos_ytransform

On Monday, May 7, 2018 8:53:34 AM PDT Jason Ekstrand wrote: > On Mon, May 7, 2018 at 8:02 AM, Alejandro Piñeiro > wrote: > > > Hi Jason, > > > > as part of the ARB_gl_spirv work, we are doing the linking based on the > > nir shader that comes from spirv_to_nir. On some

[Mesa-dev] [PATCH] i965: Don't leak blorp on Gen4-5.

We used to only initialize BLORP on Gen6+. When we added it on Gen4-5, we forgot to destroy it unconditionally. Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support for gen4-5) --- src/mesa/drivers/dri/i965/brw_context.c | 3 +-- 1 file changed, 1 insertion(+), 2

Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

On Saturday, May 5, 2018 12:49:18 AM PDT Chris Wilson wrote: > Quoting Chris Wilson (2018-05-04 22:27:27) > > Quoting Kenneth Graunke (2018-05-04 02:12:36) > > > + if (brw_using_softpin(bufmgr) && bo->gtt_offset == 0ull) { > > > + bo->gtt_offset

Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

On Friday, May 4, 2018 2:27:27 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:36) > > + if (brw_using_softpin(bufmgr) && bo->gtt_offset == 0ull) { > > + bo->gtt_offset = vma_alloc(bufmgr, memzone, bo->size, 1); > > +

Re: [Mesa-dev] [PATCH 05/10] i965: Introduce a "memory zone" concept on BO allocation.

On Friday, May 4, 2018 2:18:11 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:35) > > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c > > b/src/mesa/drivers/dri/i965/brw_bufmgr.c > > index 66f30a1637f..66828f319be 100644 > > --- a/src/mesa/dr

[Mesa-dev] [PATCH] i965: Fix occlusion queries for BLORP operations.

Gen4-5 traditionally don't use GEM context support, which means that the PS_DEPTH_COUNT register isn't saved/restored for us across batches. This means that we have to bookend each batch with start/end snapshots, and add deltas from a series of pairs, instead of simply having a single

Re: [Mesa-dev] [PATCH 3/5] ffvertex: Don't try to read output registers in fog calculation

none of the classic drivers are calling that, though, so they would be broken if they tried to enable this. Either your patch, or calling _mesa_remove_output_reads(), would probably solve the issue. At any rate, using a temporary seems reasonable. Series is: Reviewed-by: Kenneth Graunke

Re: [Mesa-dev] [PATCH 02/10] i965: perf: sklgt2: drop special programming for pre-production stepping

I cannot find any documentation at all indicating that 0x80 can be changed to 0 on modern Skylakes...register 0x9840 only appears to be documented on Broadwell. At any rate, I was able to confirm that Skylake PCI ID rev 02 appears to be preproduction, and shouldn't exist, so I think this is fine t

Re: [Mesa-dev] [PATCH 01/10] i965: perf: sklgt2: update a priority for register programming

SkuRevisionId 0x02 UGTE" > - priority="1" > + priority="0" > > > > > Yeah...kind of annoying to have useless fields in our XML, but... I guess if we're trying to reuse XML created by o

Re: [Mesa-dev] [PATCH] intel: devinfo: fix assertion on devices with odd number of EUs

Not sure this link will stay live forever... Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> > Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing > masks values") > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > --- >

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

On Friday, May 4, 2018 2:10:19 AM PDT Daniel Vetter wrote: > On Fri, May 04, 2018 at 11:07:45AM +0200, Daniel Vetter wrote: > > On Fri, May 04, 2018 at 01:28:02AM -0700, Kenneth Graunke wrote: > > > On Friday, May 4, 2018 1:16:29 AM PDT Kenneth Graunke wrote: > > > >

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

On Friday, May 4, 2018 1:16:29 AM PDT Kenneth Graunke wrote: > On Friday, May 4, 2018 12:39:12 AM PDT Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-05-04 08:34:07) > > > On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote: > > > > Quoting Kennet

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

On Friday, May 4, 2018 12:39:12 AM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 08:34:07) > > On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote: > > > Quoting Kenneth Graunke (2018-05-04 02:12:40) > > > > This isn't strictly necessary,

Re: [Mesa-dev] [PATCH 08/10] i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.

On Thursday, May 3, 2018 11:49:51 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:38) > > We'd like to start using soft-pin to assign BO addresses up front, and > > never move them again. Our previous plan for dealing with 48-bit VF > > cache bugs w

Re: [Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

On Friday, May 4, 2018 12:02:33 AM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:36) > > This introduces a new fast virtual memory allocator integrated with our > > BO cache bucketing. For larger objects, it falls back to the simple > > free-list allocat

Re: [Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

On Thursday, May 3, 2018 11:53:24 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2018-05-04 02:12:40) > > This isn't strictly necessary, but anyone running Cannonlake will > > already have Kernel 4.5 or later, so there's no reason to support > > the relocation model on

[Mesa-dev] [PATCH 05/10] i965: Introduce a "memory zone" concept on BO allocation.

We're planning to start managing the PPGTT in userspace in the near future, rather than relying on the kernel to assign addresses. While most buffers can go anywhere, some need to be restricted to within 4GB of a base address. This commit adds a "memory zone" parameter to the BO allocation

[Mesa-dev] [PATCH 07/10] i965: Prepare batchbuffer module for softpin support.

If EXEC_OBJECT_PINNED is set, we don't want to emit any relocations. We simply want to add the BO to the validation list, and possibly mark it as writeable. The new brw_use_pinned_bo() interface does just that. To avoid having to make every caller consider both the relocation and softpin cases,

[Mesa-dev] [PATCH 08/10] i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.

We'd like to start using soft-pin to assign BO addresses up front, and never move them again. Our previous plan for dealing with 48-bit VF cache bugs was to relocate vertex buffers to the low 4GB, so we'd never have addresses that alias in the low 32 bits. But that requires moving buffers

[Mesa-dev] [PATCH 01/10] i965: Set initial kflags on BO creation.

This simplifies kflag initialization, by creating a bufmgr-wide setting for initial kflags, and just applying it whenever we create a new BO. This also properly allows 48-bit addresses for imported BOs (via prime or flink), which I had missed in my earlier 48-bit support series. This will be

[Mesa-dev] [PATCH 09/10] i965: Softpin all buffers and never use relocations.

--- src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) This enables it for Broadwell (with a 64-bit kernel) and Skylake+ (with any kernel). Unfortunately, it doesn't enable it for Cherryview as that has a 32-bit GTT. We could switch that over as well,

[Mesa-dev] [PATCH 10/10] i965: Require softpin support for Cannonlake and later.

This isn't strictly necessary, but anyone running Cannonlake will already have Kernel 4.5 or later, so there's no reason to support the relocation model on Gen10+. This will let us avoid dealing with them for new features. --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 4 1 file changed, 4

[Mesa-dev] [PATCH 04/10] i965: Dump validation list on INTEL_DEBUG=bat, submit.

This is really useful when debugging any sort of buffer management issues, so just printing it during INTEL_DEBUG=bat,submit seems reasonable. With bat, we're already spamming so much output that it doesn't really hurt. With submit, it's still easy to grep for the older information, and the new

[Mesa-dev] [PATCH 02/10] util: Add a virtual memory allocator

From: Jason Ekstrand This is simple linear-walk first-fit allocator roughly based on the allocator in the radeon winsys code. This allocator has two primary functional differences: 1) It cleanly returns 0 on allocation failure 2) It allocates addresses top-down

[Mesa-dev] [PATCH 06/10] i965: Add virtual memory allocator infrastructure to brw_bufmgr.

This introduces a new fast virtual memory allocator integrated with our BO cache bucketing. For larger objects, it falls back to the simple free-list allocator (util_vma). This puts the allocators in place but doesn't enable softpin yet. --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 291

[Mesa-dev] [PATCH 03/10] util: Make vma.c support non-power-of-two alignments.

I want to use this in a bucketing allocator for i965. --- src/util/vma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/util/vma.c b/src/util/vma.c index 3d61f6969ed..d6ee05988ef 100644 --- a/src/util/vma.c +++ b/src/util/vma.c @@ -88,7 +88,6 @@

Re: [Mesa-dev] [PATCH 2/2] intel: aubinator: add an option to limit the number of decoded VBO lines

, (int *) _full_decode, > false }, > + { "color", required_argument, NULL, > 'c' }, > + { "xml", required_argument, NULL, > 'x' }, > + { "max-vbo-lines", required_argument, NULL

Re: [Mesa-dev] [PATCH] nir: add missing dependency in meson.build

On Wednesday, May 2, 2018 9:49:34 AM PDT Rob Clark wrote: > nir_builder_opcodes.h also depends on nir_intrinsics.py for generating > the system-value builders. > > Reported-by: Christoph Haag <haa...@frickel.club> > Reported-by: Kenneth Graunke <kenn...@whitecape.org>

Re: [Mesa-dev] [PATCH] intel: Fix 3DSTATE_CONSTANT buffer decoding.

On Wednesday, May 2, 2018 9:50:33 AM PDT Lionel Landwerlin wrote: > On 02/05/18 17:45, Kenneth Graunke wrote: > > First, this was iterating over the 3DSTATE_CONSTANT_* instruction > > but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure. > > > > Sec

Re: [Mesa-dev] [PATCH 2/9] util/set: add a set_clear function

> _mesa_set_destroy(struct set *set, >void (*delete_function)(struct set_entry *entry)); > +void > +_mesa_set_clear(struct set *set, > + void (*delete_function)(struct set_entry *entry)); > > struct set_entry * > _mesa_set_add(struct set *set,

[Mesa-dev] [PATCH] intel: Fix 3DSTATE_CONSTANT buffer decoding.

First, this was iterating over the 3DSTATE_CONSTANT_* instruction but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure. Secondly, the fields have been called Buffer[0] and Read Length[0], for a while now, and we were not handling the subscripts correctly. ---

Re: [Mesa-dev] [PATCH 4/5] intel: decoder: fix starting dword of struct fields

On Wednesday, May 2, 2018 2:57:50 AM PDT Lionel Landwerlin wrote: > On 02/05/18 07:44, Kenneth Graunke wrote: > > On Tuesday, May 1, 2018 4:43:05 PM PDT Lionel Landwerlin wrote: > >> Struct fields might span several dwords, but iter_dword is incremented > >> up to th

Re: [Mesa-dev] [PATCH 2/3] intel: Give the batch decoder a callback to ask about state size.

On Wednesday, May 2, 2018 3:52:22 AM PDT Lionel Landwerlin wrote: > On 02/05/18 06:50, Kenneth Graunke wrote: > > Given an arbitrary batch, we don't always know what the size of certain > > things are, such as how many entries are in a binding table. But it's > > easy fo

Re: [Mesa-dev] [PATCH 0/5] intel: decoder fixes

ields > intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields Patches 1-3 and 5 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Thanks for fixing all of these! Being able to use 'while' instead of 'do..while' is so much nicer. signature.asc Desc

Re: [Mesa-dev] [PATCH 4/5] intel: decoder: fix starting dword of struct fields

On Tuesday, May 1, 2018 4:43:05 PM PDT Lionel Landwerlin wrote: > Struct fields might span several dwords, but iter_dword is incremented > up to the last dword of the current field before we print out the > struct's fields. We can't use iter_dword for computing the offset into > the pointer of

[Mesa-dev] [PATCH 3/3] i965: Reuse batch decoder infrastructure rather than open coding it.

With the new callback, Jason's newer batch decoder infrastructure should be able to do just as well as the old open coded INTEL_DEBUG=bat handling, with much less code. If there are any limitations, we'd like to improve the common code rather than doing one-off hacks here. ---

[Mesa-dev] [PATCH 1/3] intel: Move batch decoder/disassembler from tools/ to common/

Making these part of libintel_common allows us to use them in the DRI driver. The standalone tool binaries already link against the common library, too, so it's no harder for them. --- src/intel/Makefile.sources| 3 +++ src/intel/Makefile.tools.am |

[Mesa-dev] [PATCH 2/3] intel: Give the batch decoder a callback to ask about state size.

Given an arbitrary batch, we don't always know what the size of certain things are, such as how many entries are in a binding table. But it's easy for the driver to track that information, so with a simple callback we can calculate this correctly for INTEL_DEBUG=bat. ---

Re: [Mesa-dev] [PATCH v2 00/13] 86 gtt maps

On Monday, April 30, 2018 10:25:39 AM PDT Scott D Phillips wrote: > Here is a v2 of the 86 gtt maps series with the refactor > suggestions by Chris folded in. > > Chris Wilson (8): > i965: Move unmap_gtt before map_gtt > i965: Move unmap_blit before map_blit > i965: Move unmap_movntdqa

Re: [Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

On Monday, April 30, 2018 10:25:49 AM PDT Scott D Phillips wrote: > Rename the (un)map_gtt functions to (un)map_map (map by > returning a map) and add new functions (un)map_tiled_memcpy that > return a shadow buffer populated with the intel_tiled_memcpy > functions. > > Tiling/detiling with the

Re: [Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

struct intel_mipmap_tree *mt, > @@ -3688,8 +3773,13 @@ intel_miptree_map(struct brw_context *brw, >(mt->surf.row_pitch % 16 == 0)) { >intel_miptree_map_movntdqa(brw, mt, map, level, slice); > #endif > + } else if (mt->surf.tiling != ISL_TILING

Re: [Mesa-dev] [PATCH 11/13] i965/miptree: Map with movntdqa for linear buffers only

On Monday, April 30, 2018 10:25:50 AM PDT Scott D Phillips wrote: > Removes a place where gtt mapping is used. > > Reviewed-by: Nanley Chery > Reviewed-by: Chris Wilson > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- > 1 file

Re: [Mesa-dev] [PATCH] mesa: add TBO support for GL_EXT_texture_norm16

r_format(const struct gl_context > *ctx, GLenum internalFormat) > case GL_R8: >return MESA_FORMAT_R_UNORM8; > case GL_R16: > - if (_mesa_is_gles(ctx)) > + if (_mesa_is_gles(ctx) && !_mesa_has_EXT_texture_norm16(ctx)) > return M

Re: [Mesa-dev] [PATCH v4] mesa: GL_EXT_texture_norm16 extension plumbing

gt; > v4: fix rest of the issues found > > Signed-off-by: Tapani Pälli <tapani.pa...@intel.com> > Acked-by: Ilia Mirkin <imir...@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. _

Re: [Mesa-dev] [PATCH 1/3] Autotools: include include/vulkan headers

include/GL/wglext.h \ > include/HaikuGL \ > include/no_extern_c.h \ > - include/pci_ids > + include/pci_ids \ > + include/vulkan I'm not sure off-hand what caused this to be necessary - it would be nice to note that in the commit message. Still, it s

Re: [Mesa-dev] [PATCH 2/3] Autotools: Add passes.h to sources so it will be included in the tarball

following to the commit message: This was introduced in commit 8f848ada8a42d9aaa8136afa1bafe32281a0fb48 but not added to the sources list, which is necessary for it to be included in release tarballs. Fixes: 8f848ada8a42d9aaa8136afa1bafe32281a0fb48 (swr/rast: Start refactoring of builder/packetizer.) Reviewed-by: Kenn

Re: [Mesa-dev] [PATCH 3/3] Autotools: Include new meson files

> src/gallium/tests/unit/Makefile.am | 2 ++ > src/mesa/state_tracker/tests/Makefile.am | 2 ++ > 5 files changed, 10 insertions(+), 1 deletion(-) Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: Thi

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

e solution. I don't like list of > instructions in general but I'm a bit more ok with duct tape in vec4. > Adding matt & Ken in case they have opinions. Duct tape in vec4 seems good to me. Patch is: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> In the scalar back

Re: [Mesa-dev] [PATCH v3 3/5] i965: perf: read slice/unslice frequencies from OA reports

'm unclear whether the RPT_ID fields exist on BDW. Some docs seem to indicate so, but they're really a mess. I was also wondering if we wanted a bit more precision on the 16.66 approximation, but it's probably always going to be a bit off, and this seems good enough. Reviewed-by: Kenneth Graunke <ken

[Mesa-dev] [PATCH 2/3] i965: Let batchbuffers be placed anywhere in the 48-bit address space.

We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process. There's no reason to restrict batch buffers to the lower 4GB. --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1

[Mesa-dev] [PATCH 3/3] i965: Don't stomp initial kflags for program cache.

We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any existing kflags. Today, there are none (as the program cache doesn't support 48-bit addressing), but once we start using softpin, we'll need to preserve EXEC_OBJECT_PINNED. --- src/mesa/drivers/dri/i965/brw_program_cache.c | 4

[Mesa-dev] [PATCH 1/3] intel: fix check for 48b ppgtt support

From: Scott D Phillips The previous logic of the supports_48b_addresses wasn't actually checking if i915.ko was running with full_48bit_ppgtt. The ENOENT it was checking for was actually coming from the invalid context id provided in the test execbuffer. There is no

Re: [Mesa-dev] [PATCH 1/1] i965: Make sure the shadow buffers have enough space

On Friday, April 13, 2018 2:37:05 PM PDT James Xiong wrote: > On Fri, 13 Apr 2018 14:33:09 -0700 > Kenneth Graunke <kenn...@whitecape.org> wrote: > > > On Friday, April 13, 2018 2:08:40 PM PDT James Xiong wrote: > > > On Fri, 13 Apr 2018 13:51:02 -0700 > > >

[Mesa-dev] [PATCH] i965: Allocate shadow batches to explicitly be the BO size.

This unfortunately makes it malloc/realloc on every new batch, rather than once at startup. But it ensures that the shadow buffer's size will absolutely match the BO size. Otherwise, as we tune BATCH_SZ/STATE_SZ or bufmgr cache bucket sizes, we may get a BO size that's rounded up, and fail to

Re: [Mesa-dev] [PATCH v2 3/5] i965: perf: read slice/unslice frequencies from OA reports

On Tuesday, April 17, 2018 4:45:13 PM PDT Lionel Landwerlin wrote: > On 16/04/18 23:16, Kenneth Graunke wrote: > > On Tuesday, April 3, 2018 7:48:11 AM PDT Lionel Landwerlin wrote: > >> Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > >> ---

Re: [Mesa-dev] [PATCH v2 3/3] i965: enable INTEL_blackhole_render

On Friday, April 6, 2018 7:31:41 AM PDT Lionel Landwerlin wrote: > v2: condition the extension on context isolation support from the > kernel (Chris) > > v3: (Lionel) > > The initial version of this change used a feature of the Gen7+ > command parser to turn the primitive

Re: [Mesa-dev] [PATCH v2 2/3] mesa: add INTEL_blackhole_render

; > @@ -4704,6 +4705,11 @@ struct gl_driver_flags > > /** Shader constants (uniforms, program parameters, state constants) */ > uint64_t NewShaderConstants[MESA_SHADER_STAGES]; > + > + /** > +* gl_context::IntelBlackholeRender > +*/ > + uint64_t NewIn

Re: [Mesa-dev] [PATCH v2 3/3] i965: enable INTEL_blackhole_render

On Friday, April 6, 2018 7:31:41 AM PDT Lionel Landwerlin wrote: > v2: condition the extension on context isolation support from the > kernel (Chris) > > v3: (Lionel) > > The initial version of this change used a feature of the Gen7+ > command parser to turn the primitive

Re: [Mesa-dev] [PATCH v2 5/5] i965: perf: enable GPA query statistics

"N fragment shader invocations"); > + else > + brw_perf_query_info_add_basic_stat_reg(query, PS_INVOCATION_COUNT, > + "N fragment shader > invocations"); Braces around single statements that span multiple lines, please. > + brw_per

Re: [Mesa-dev] [PATCH v2 4/5] i965: perf: add support for raw queries

text *brw); > + > + > +#endif /* BRW_PERFORMANCE_QUERY_MDAPI_H */ Personally I'd just add these to brw_performance_query.h, not sure it's worth adding a whole new header file for 2-3 prototypes... Up to you though. With the cherryview thing fixed, Reviewed-by: Kenneth Graunke <kenn...@

Re: [Mesa-dev] [PATCH v2 3/5] i965: perf: read slice/unslice frequencies from OA reports

On Tuesday, April 3, 2018 7:48:11 AM PDT Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin > --- > src/mesa/drivers/dri/i965/brw_performance_query.c | 37 > +++ > src/mesa/drivers/dri/i965/brw_performance_query.h | 12 > 2

Re: [Mesa-dev] [PATCH v2 2/5] i965: perf: snapshot RPSTAT register

t; + obj->oa.gt_frequency[0] = GET_FIELD(start, GEN7_RPSTAT1_CURR_GT_FREQ) > * 50ULL; > + obj->oa.gt_frequency[1] = GET_FIELD(end, GEN7_RPSTAT1_CURR_GT_FREQ) * > 50ULL; > + break; > + case 9: > + case 10: > + case 11: > + obj->oa.gt_frequen

Re: [Mesa-dev] [PATCH 1/2] dri: Add __DRI_IMAGE_FORMAT_SABGR8

lly know what these numbers mean, but assuming this is a correct define, the patches look pretty reasonable to me. Both patches are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> ("It's just sRGB, what could go wrong?" - quote on a tombstone) signature.asc Description: This is

Re: [Mesa-dev] [PATCH 1/1] i965: Make sure the shadow buffers have enough space

On Friday, April 13, 2018 2:08:40 PM PDT James Xiong wrote: > On Fri, 13 Apr 2018 13:51:02 -0700 > Kenneth Graunke <kenn...@whitecape.org> wrote: > > > On Friday, April 13, 2018 1:35:45 PM PDT Kenneth Graunke wrote: > > > On Monday, April 9, 2018 4:06:16 PM PDT Jam

Re: [Mesa-dev] [PATCH 1/1] i965: Make sure the shadow buffers have enough space

On Friday, April 13, 2018 1:35:45 PM PDT Kenneth Graunke wrote: > On Monday, April 9, 2018 4:06:16 PM PDT James Xiong wrote: > > From: "Xiong, James" <james.xi...@intel.com> > > > > On non-LLC platforms, we malloc shadow batch/state buffers > > of the

[Mesa-dev] [PATCH v2] i965: Fix shadow batches to be the same size as the real BO.

brw_bo_alloc may round up our allocation size to the next bucket size. In this case, we would malloc a shadow buffer that was the original intended size, but use bo->size (the larger size) for all of our checks. This could cause us to run off the end of the shadow buffer. v2: Actually use the

Re: [Mesa-dev] [PATCH 1/1] i965: Make sure the shadow buffers have enough space

On Monday, April 9, 2018 4:06:16 PM PDT James Xiong wrote: > From: "Xiong, James" > > On non-LLC platforms, we malloc shadow batch/state buffers > of the same sizes as our batch/state buffers' GEM allocations. > However the buffer allocator reuses similar-sized gem

[Mesa-dev] [PATCH] i965: Fix shadow batches to be the same size as the real BO.

brw_bo_alloc may round up our allocation size to the next bucket size. In this case, we would malloc a shadow buffer that was the original intended size, but use bo->size (the larger size) for all of our checks. This could cause us to run off the end of the shadow buffer. Reported-by: James

Re: [Mesa-dev] Request for new Components in bugzilla

On Friday, April 13, 2018 12:00:02 AM PDT Timothy Arceri wrote: > Wasn't sure who to bug about this so I've sent it here. > > I've spent a little big of time lately fixing a few bugs and cleaning > out bugzilla. One thing that is annoying is the growing number of > software rast bug in the Mesa

[Mesa-dev] [PATCH] i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

I'd like to drop this pre-isl function. This drops one of the two uses. --- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index

Re: [Mesa-dev] [PATCH] i965: Extend the negative 32-bit deltas to 64-bits

On Tuesday, April 3, 2018 11:56:27 PM PDT Sergii Romantsov wrote: > Hello, Mark. > I've done: Cc, Tested-by and Reviewed-by also added. I pushed your patch. Thanks so much for tracking this down! signature.asc Description: This is a digitally signed message part.

Re: [Mesa-dev] [PATCH shaderdb] run: -p option accepts hex format pci-id

On Wednesday, March 14, 2018 5:49:35 PM PDT Dongwon Kim wrote: > -p option now takes hex format pci-id of target architecture. > > Signed-off-by: Dongwon Kim > --- > run.c | 35 +-- > 1 file changed, 25 insertions(+), 10 deletions(-) I had

Re: [Mesa-dev] [PATCH 08/11] i965: perf: snapshot RPSTAT1 register

> >> diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c > >> b/src/mesa/drivers/dri/i965/brw_performance_query.c > >> index 98666759d75..7d5b44cf61d 100644 > >> --- a/src/mesa/drivers/dri/i965/brw_performance_query.c > >> +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c > >> @@

Re: [Mesa-dev] [PATCH] RFC: Externd IMG_context_priority with NV_context_priority_realtime

On Saturday, March 31, 2018 5:56:57 AM PDT Chris Wilson wrote: > Quoting Chris Wilson (2018-03-31 12:00:16) > > Quoting Kenneth Graunke (2018-03-30 19:20:57) > > > On Friday, March 30, 2018 7:40:13 AM PDT Chris Wilson wrote: > > > > For i915, we are proposing to use

Re: [Mesa-dev] [PATCH] RFC: Externd IMG_context_priority with NV_context_priority_realtime

On Friday, March 30, 2018 7:40:13 AM PDT Chris Wilson wrote: > NV_context_priority_realtime > https://www.khronos.org/registry/EGL/extensions/NV/EGL_NV_context_priority_realtime.txt > > "This extension allows an EGLContext to be created with one extra > priority level in addition to three

Re: [Mesa-dev] [PATCH 06/61] nir/validator: Validate that all used variables exist

gt;var_defs, var, is_global ? NULL : state->impl); since we want to insert into the same set either way, just with NULL for the impl if there isn't one. Doesn't matter though, your call. Patches 1-6 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

[Mesa-dev] [PATCH 3/4] i965: Drop unused alignment parameter from brw_bo_alloc().

brw_bo_alloc no longer uses this parameter, so there's no point. --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965/brw_bufmgr.c| 2 +- src/mesa/drivers/dri/i965/brw_bufmgr.h| 2 +- src/mesa/drivers/dri/i965/brw_performance_query.c | 5

[Mesa-dev] [PATCH 1/4] i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().

intel_miptree_create_for_bo does not actually allocate a BO, so specifying allocation flags accomplishes nothing and is confusing. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 2/4] i965: Drop alignment parameter from bo_alloc_internal().

Buffers are always page aligned on 965+ hardware; I believe this extra parameter is a vestige from the Gen2-3 era. All callers pass 0, and in fact we assert that the alignment is 0 unless BO_ALLOC_BUSY is set (for some reason). We can just drop the parameter and set the value to 0 explicitly.

[Mesa-dev] [PATCH 4/4] i965: Drop unnecessary bo->align field.

bo->align is always 0; there's no need to waste 8 bytes storing it. Thanks to C99 initializers zeroing fields, we can completely drop the only read of the field altogether. --- src/mesa/drivers/dri/i965/brw_bufmgr.c| 2 -- src/mesa/drivers/dri/i965/brw_bufmgr.h| 7 ---

Re: [Mesa-dev] [PATCH 08/11] i965: perf: snapshot RPSTAT1 register

On Thursday, March 8, 2018 7:42:53 AM PDT Lionel Landwerlin wrote: > This register contains the frequency of the GT, it's one of the value > GPA would like to have as part of their queries. > > Signed-off-by: Lionel Landwerlin > --- >

Re: [Mesa-dev] [PATCH 07/11] i965: perf: extract utility functions

tions(+), 252 deletions(-) > create mode 100644 src/mesa/drivers/dri/i965/brw_performance_query_metrics.h patch did a fine job of mangling these motions, but they all look okay once you detangle them :) Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

[Mesa-dev] [PATCH] i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

This is just zero - passing nothing already gives us a post-sync operation of "nothing". --- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +--- src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +- src/mesa/drivers/dri/i965/brw_program.c | 4 +--- src/mesa/drivers/dri/i965/gen7_l3_state.c

Re: [Mesa-dev] [PATCH] i965/perf: fix config registration when uploading to kernel

egister_oa_config(brw, query, ret); > DBG("metric set: %s (added)\n", query->guid); > } > } > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 5/8] intel: devinfo: add helper functions to fill fusing masks values

orm > across slices. > > v2: Change gen_device_info_update_from_masks() to generate topology > and call into gen_device_info_update_from_topology (Lionel/Ken) > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> With the num_eus_per_subslice asserts gone and div

Re: [Mesa-dev] [PATCH v3 3/8] drm-uapi: bump headers

m-uapi/drm_mode.h | 43 +--- > include/drm-uapi/i915_drm.h | 152 > +-- > include/drm-uapi/tegra_drm.h | 22 +-- > 4 files changed, 189 insertions(+), 36 deletions(-) Acked-by: Kenneth Graunke <kenn...@whitecape.org> Though, I honestly don'

Re: [Mesa-dev] [PATCH 05/11] intel/compiler: Use null destination register for memory fence messages

On Wednesday, March 21, 2018 2:06:16 PM PDT Matt Turner wrote: > From Message Descriptor section in gfxspecs: > > "Memory fence messages without Commit Enable set do not return >anything to the thread (response length is 0 and destination >register is null)." > > This fixes a GPU hang

Re: [Mesa-dev] [PATCH 10/11] intel/compiler: Skip 64-bit type tests when types not available

e) == 8 && inst[i].dst_type != BRW_REGISTER_TYPE_NF or omit that last part if NF isn't a consideration. Or at least make a helper function so as not to repeat so much. But it's up to you. Either way, this patch is: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

Re: [Mesa-dev] [PATCH 06/11] intel/compiler/icl: Clear "null render target" bit in extended message descriptor

all the macros to support Gen11+ only bits also seems pretty lame. Given that Curro's already reworking all the message descriptor stuff, this will probably do for now. With a comment saying something like /* actually only Gen11+ */, Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> si

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