Re: [Mesa-dev] [PATCH 08/11] intel: Disable fast color clear on icl

On Wednesday, March 21, 2018 2:06:19 PM PDT Matt Turner wrote: > From: Anuj Phogat > > Disabling fast color clear makes fbo-clearmipmap test render correct > texture in base miplevel. Fast color clear is anyways disabled for > non-base miplevels. > --- >

Re: [Mesa-dev] [PATCH 07/11] intel/compiler/icl: Set the condition for dependency control on gen11+

On Wednesday, March 21, 2018 2:06:18 PM PDT Matt Turner wrote: > From: Anuj Phogat > > When source or destination datatype is 64b or operation is integer > DWord multiply, DepCtrl must not be used. > We had this restriction on few previous intel platforms. It has been >

Re: [Mesa-dev] [PATCH 01/11] intel/tools/aubinator: Drop platform list from print_help()

'auto' > (default\n" > "if omitted), 'always', or 'never'\n" > Patches 1-4 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 5/8] intel: devinfo: add helper functions to fill fusing masks values

On Tuesday, March 20, 2018 11:10:11 AM PDT Lionel Landwerlin wrote: > On 20/03/18 00:08, Kenneth Graunke wrote: > > On Wednesday, March 14, 2018 10:19:11 AM PDT Lionel Landwerlin wrote: > >> + devinfo->num_slices = __builtin_popcount(devinfo->slice_masks); > > _mesa

Re: [Mesa-dev] [PATCH v2 8/8] i965: add performance query support on CNL

insertions(+), 2 deletions(-) > create mode 100644 src/mesa/drivers/dri/i965/brw_oa_cnl.xml Acked-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev m

Re: [Mesa-dev] [PATCH v2 5/8] intel: devinfo: add helper functions to fill fusing masks values

devinfo->num_slices = __builtin_popcount(devinfo->slice_masks); _mesa_bitcount() here and elsewhere. > + > + uint32_t max_slices = util_last_bit(slice_mask); > + uint32_t max_subslices = util_last_bit(subslice_mask); > + devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslice

Re: [Mesa-dev] [PATCH v2 4/8] intel: devinfo: meson: include drm uapi

( >['intel_dev'], >files_libintel_dev, > - include_directories : [inc_common, inc_intel], > + include_directories : [inc_common, inc_intel, inc_drm_uapi], >c_args : [c_vis_args, no_override_init_args], > ) > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org&

Re: [Mesa-dev] [PATCH v2 7/8] i965: perf: add support for new equation operators

emit_umul) > ops["USUB"] = (2, emit_usub) > ops["UMIN"] = (2, emit_umin) > +ops["<<"] = (2, emit_lshft) > +ops[">>"] = (2, emit_rshft) > +ops["AND"] = (2, emit_and) > > def brkt(subexp): > if " " in subexp: > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 6/8] i965: perf: query topology

gt;perfquery.sys_vars.slice_mask = devinfo->slice_masks; > + brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices; > + > + for (int i = 0; i < sizeof(devinfo->subslice_masks[i]); i++) { > + brw->perfquery.sys_vars.n_eu_sub_slices += > + __builtin_popcount(devinfo->subslice_masks[i]); Probably best to use _mesa_bitcount() here and elsewhere. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 2/8] intel: devinfo: store slice/subslice/eu masks

subslice_stride; > + > +devinfo->eu_masks[subslice_offset + b_eu] = > + (((1UL << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & > 0xff; > + } > + } > + } > +} > + This is kind of messy, b

Re: [Mesa-dev] [PATCH v2 1/8] intel: devinfo: store number of EUs per subslice

{ 2, }, > + .num_eu_per_subslice = 8, You're probably going to have to update this to 6 based on the Cherryview fusing information. Look for sseu in i965. :( So far, we've been putting the larger number (for the 2x8 model) in gen_device_info and correcting it down for the 2x6 model. We'll nee

Re: [Mesa-dev] [PATCH 2/4] i965: pipecontrol: add LRI write immediate flag

ESET (1 << 19) > #define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/4] intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers

tel/genxml/gen7.xml | 7 +++ > src/intel/genxml/gen75.xml | 7 +++ > src/intel/genxml/gen8.xml | 7 +++ > src/intel/genxml/gen9.xml | 6 ++ > 7 files changed, 46 insertions(+) Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Descriptio

Re: [Mesa-dev] [PATCH 2/2] i965: perf: reduce i965 binary size

..@intel.com> > Reviewed-by: Emil Velikov <emil.veli...@collabora.com> (build system part) This is a good idea and your Python changes all looked reasonable. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] i965: perf: fix a counter return type on hsw

gt; max_equation="100" > equation="A 3 READ $EuCoresTotalCount UDIV 100 UMUL > $GpuCoreClocks FDIV" > underscore_name="vs_eu_stall" > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Descrip

Re: [Mesa-dev] [PATCH shaderdb 2/3] run: new '--pci-id' option for overriding pci-id

On Wednesday, March 14, 2018 3:43:18 PM PDT Dongwon Kim wrote: > Yeah, thought about that (checking name then -> try to parse it as PCI-ID) > but didn't implement it because it won't work when there are multiple > different PCI-ID bound to same 'name' (e.g. want to use a specific PCI-ID > hsw).

[Mesa-dev] Releasing 18.0

Hi Emil, all, I think we've closed the last of the Mesa 18.0 blocker bugs. It looks like there are some patches nominated for the 18.0 branch still (fixing some of those issues), but assuming things are merged, I think we're ready to release. I checked with Mark and Jason on IRC and they seemed

Re: [Mesa-dev] [PATCH shader-db 4/4] run: handling binding of attribute variable name

On Friday, March 9, 2018 2:28:36 PM PDT Dongwon Kim wrote: > Optional binding of variables can be processed before linking shader > objects for creating shader program. It is activated by adding lines > with a keyword "BindAttribLoc" followed by name and index as, > > "BindAttribLoc name_str1 " >

Re: [Mesa-dev] [PATCH shaderdb 3/3] run: shader program file created via GetProgramBinary (v3)

On Monday, February 26, 2018 2:17:05 PM PDT Dongwon Kim wrote: > extraction of linked binary program to a file using glGetProgramBinary. > This file is intended to be loaded by glProgramBinary in the graphic > application running on the target system. > > To enable this feature, a new option

Re: [Mesa-dev] [PATCH shaderdb 2/3] run: new '--pci-id' option for overriding pci-id

On Monday, February 12, 2018 5:26:15 PM PDT Dongwon Kim wrote: > Add a new option, '--pciid' to override a pci id of the target arch > to support cross-architecture shader compilation. Not like "-p" option, > it is for accepting any GFX devices supported by the driver. > > Setting both "-p" and

Re: [Mesa-dev] [PATCH shaderdb 2/3] run: new '--pci-id' option for overriding pci-id

On Monday, February 12, 2018 5:26:15 PM PDT Dongwon Kim wrote: > Add a new option, '--pciid' to override a pci id of the target arch > to support cross-architecture shader compilation. Not like "-p" option, > it is for accepting any GFX devices supported by the driver. > > Setting both "-p" and

Re: [Mesa-dev] [RFC] Mesa 17.3.x release problems and process improvements

On Friday, March 9, 2018 12:12:28 PM PDT Mark Janes wrote: [snip] > I've been doing this for Intel. Developers are on the hook to fix their > bugs, but you can't make them do it. They have many pressures on them, > and a maintainer can't make the call as to whether a rendering bug is > more

Re: [Mesa-dev] [PATCH] i965: Emit texture cache invalidates around blorp_copy

OL_CS_STALL | > +PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); > + > intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1, > dst_aux_usage); > } > This is probably best for now, though

Re: [Mesa-dev] [PATCH 3/5] intel/dev: Add devinfo cs_scratch_ids_per_subslice field

On Wednesday, March 7, 2018 12:36:02 PM PST Jordan Justen wrote: > On 2018-03-07 00:47:12, Kenneth Graunke wrote: > > On Wednesday, March 7, 2018 12:16:28 AM PST Jordan Justen wrote: > > > Suggested-by: Kenneth Graunke <kenn...@whitecape.org> > > > Signed-of

Re: [Mesa-dev] [PATCH 04/11] i965: perf: reuse timescale base function from query

. But, the ternary is checking the /numerator/ for zero, which seems kinda pointless... 0 / timestamp_frequency == 0... Patches 1-6 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. __

Re: [Mesa-dev] [PATCH 3/5] intel/dev: Add devinfo cs_scratch_ids_per_subslice field

On Wednesday, March 7, 2018 12:16:28 AM PST Jordan Justen wrote: > Suggested-by: Kenneth Graunke <kenn...@whitecape.org> > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > --- > src/intel/dev/gen_device_info.c | 13 - > src/intel/dev/gen_devic

Re: [Mesa-dev] [PATCH 1/5] i965: Hard code scratch_ids_per_subslice for Cherryview

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104636 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105290 > Cc: Kenneth Graunke <kenn...@whitecape.org> > Cc: Eero Tamminen <eero.t.tammi...@intel.com> > Cc: <mesa-sta...@lists.freedesktop.org> > Signed-off-by: Jordan

Re: [Mesa-dev] [PATCH 20/22] i965/vec4: Relax writemask condition in CSE

On Tuesday, March 6, 2018 11:10:57 AM PST Ian Romanick wrote: > On 03/05/2018 02:50 PM, Kenneth Graunke wrote: > > On Friday, February 23, 2018 3:56:05 PM PST Ian Romanick wrote: > >> From: Ian Romanick <ian.d.roman...@intel.com> > >> > >> If the previou

Re: [Mesa-dev] [PATCH 3/3] i965/tex_image: Avoid the ASTC LDR workaround on gen9lp

flush_astc_denorms(ctx, dims, texImage, > xoffset, yoffset, zoffset, > width, height, depth); > I don't know how to review this, really, but it sounds very plausible that they would have fixed that bug on gen9lp. If it doesn't regress

Re: [Mesa-dev] [PATCH 2/3] i965/extensions: Enable ASTC HDR on CannonLake

On Monday, March 5, 2018 2:07:54 PM PST Nanley Chery wrote: > Cc: Rafael Antognolli > --- > src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c >

Re: [Mesa-dev] [PATCH 1/3] i965/mipmap_tree: Don't allocate CCS when emulating ETC support

On Monday, March 5, 2018 2:07:53 PM PST Nanley Chery wrote: > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c >

Re: [Mesa-dev] [PATCH] intel: Add missing includes for building on Android

drivers/dri/i965/Android.mk > +++ b/src/mesa/drivers/dri/i965/Android.mk > @@ -289,6 +289,7 @@ LOCAL_SRC_FILES := \ > LOCAL_WHOLE_STATIC_LIBRARIES := \ > $(MESA_DRI_WHOLE_STATIC_LIBRARIES) \ > $(I965_PERGEN_LIBS) \ > + libmesa_intel_dev \ > libmesa_intel_commo

Re: [Mesa-dev] [PATCH 21/22] i965/vec4: Allow CSE on subset VF constant loads

uint32_t mask = ((ab_writemask & WRITEMASK_X) ? 0x00ff : 0) | ((ab_writemask & WRITEMASK_Y) ? 0xff00 : 0) | ((ab_writemask & WRITEMASK_Z) ? 0x00ff : 0) | ((ab_writemask & WRITEMASK_W) ? 0xff00 : 0); tmp_x.ud &= m

Re: [Mesa-dev] [PATCH 20/22] i965/vec4: Relax writemask condition in CSE

h leaving some kind of comment (or renaming variables?) in instructions_match() to indicate that 'a' is the generating expression and 'b' is the second instance...since it's no longer exactly symmetrical. Either way, Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description

Re: [Mesa-dev] [PATCH 19/22 v3] i965/fs: Merge CMP and SEL into CSEL on Gen8+

gt; No changes on earlier platforms. > > Signed-off-by: Ian Romanick <ian.d.roman...@intel.com> Nice, thanks for doing this, Ian! Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 18/22] i965/fs: Add infrastructure for generating CSEL instructions.

On Monday, March 5, 2018 11:17:29 AM PST Ian Romanick wrote: > On 02/28/2018 12:58 AM, Samuel Iglesias Gonsálvez wrote: > > On 24/02/18 00:56, Ian Romanick wrote: > >> From: Kenneth Graunke <kenn...@whitecape.org> > >> > >> v2 (idr): Don't allow CSEL with

Re: [Mesa-dev] [PATCH 1/2] i965: Generalize intel_upload.c to support multiple uploaders.

On Thursday, March 1, 2018 4:16:13 PM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-03-01 23:39:54) > > I'd like to reuse the upload logic for a new program cache, but the > > buffers will need to have a different lifetime than the default > > uploader, and al

[Mesa-dev] [PATCH 1/2] i965: Generalize intel_upload.c to support multiple uploaders.

I'd like to reuse the upload logic for a new program cache, but the buffers will need to have a different lifetime than the default uploader, and also some address space restrictions. This makes it a bit more like u_upload_mgr. --- src/mesa/drivers/dri/i965/brw_context.c | 2 +

[Mesa-dev] [PATCH 2/2] i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.

This should have no practical impact. For the default uploader, we don't really care, but for others, we may want to append more data as the GPU is reading existing data, which means we need async and persistent flags. --- src/mesa/drivers/dri/i965/intel_upload.c | 4 +++- 1 file changed, 3

Re: [Mesa-dev] [PATCH 5/6] intel/fs: Handle surface opcode sample masks via predication.

inst->predicate = BRW_PREDICATE_ALIGN1_ALLV; > + ubld.MOV(retype(brw_flag_subreg(inst->flag_subreg + 2), > + sample_mask.type), > + sample_mask); I was surprised to see flag_subreg remain unchanged here, but then I re-read

Re: [Mesa-dev] [PATCH 3/6] intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.

On Tuesday, February 27, 2018 1:38:25 PM PST Francisco Jerez wrote: > This shouldn't cause any functional change at this point, it changes > SHADER_OPCODE_FIND_LIVE_CHANNEL to use the flag register specified at > the IR level instead of the hard-coded f1.0, now that it can be > represented in

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On Wednesday, February 28, 2018 2:21:24 PM PST Emil Velikov wrote: > On 27 February 2018 at 00:05, Kenneth Graunke <kenn...@whitecape.org> wrote: > > > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

able_insert(array_types, > - ralloc_strdup(mem_ctx, key), > + strdup(key), >(void *) t); > } > > diff --git a/src/compiler/glsl_types.h b/src/compiler

Re: [Mesa-dev] [PATCH] anv: Always set has_context_priority

ntext_priority = true; > + device->has_context_priority = anv_gem_has_context_priority(fd); > > bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X); > > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digit

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of going through the bitfield of inputs (which doesn't include > padding

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

i?id=105224 > Fixes: 16631ca30ea6 (i965/sbe: fix active components for SSO programs with > over 16 inputs) > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 31 > --- > 1 file changed, 23 insertions(+), 8 deletions(-) :( Thanks for fixi

[Mesa-dev] [PATCH] intel: Drop program size pointer from vec4/fs assembly getters.

These days, we're just passing a pointer to a prog_data field, which we already have access to. We can just use it directly. (In the past, it was a pointer to a separate value.) --- src/intel/compiler/brw_fs.cpp | 4 ++-- src/intel/compiler/brw_fs.h| 2 +-

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

\ > + .size = 1024, \ > + } This might need to be 768 on some variants - I'm not certain, though. Sometimes there's autoscaling that applies, and I haven't followed exactly how it works these days. Otherwise, the updated version with the subslices thing fixed is, Reviewed-by: Kenneth Graunke <kenn.

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On Tuesday, February 27, 2018 12:35:32 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-27 00:05:46) > > +static bool > > +gem_supports_48b_addresses(int fd) > > +{ > > + struct drm_i915_gem_exec_object2 obj = { > > + .flags =

Re: [Mesa-dev] [PATCH 2/2] i965: Shorten the name of the workaround BO.

On Tuesday, February 27, 2018 2:04:36 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-26 23:55:00) > > This makes the name shorter in debug printouts. If "workaround_bo" > > is good enough for the code, it's probably good enough for debugging. > > br

Re: [Mesa-dev] [PATCH 1/2] i965: Add debugging code to dump the validation list.

On Tuesday, February 27, 2018 2:03:52 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-26 23:54:59) > > When anything goes wrong with this code, dumping the validation list > > is a useful way to figure out what's happening. > > --- > > src/mesa/drivers/d

[Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

This allows most GPU objects to use the full 48-bit address space offered by Gen8+ platforms, rather than being stuck with 32-bit. This expands the available GPU memory from 4G to 256TB or so. A few objects - instruction, scratch, and vertex buffers - need to remain pinned in the low 4GB of the

[Mesa-dev] [PATCH 1/2] i965: Add debugging code to dump the validation list.

When anything goes wrong with this code, dumping the validation list is a useful way to figure out what's happening. --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 1 file changed, 20 insertions(+) I've now used this code on multiple occasions to debug issues.

[Mesa-dev] [PATCH 2/2] i965: Shorten the name of the workaround BO.

This makes the name shorter in debug printouts. If "workaround_bo" is good enough for the code, it's probably good enough for debugging. --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

> + > + x.subnr = 0 * sizeof(float); > + y.subnr = 1 * sizeof(float); > + z.subnr = 2 * sizeof(float); > + w.subnr = 3 * sizeof(float); > + With or without any suggestions, this patch is: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

= BRW_VERTICAL_STRIDE_4; > + src0.width = BRW_WIDTH_4; > + src0.hstride = BRW_HORIZONTAL_STRIDE_0; > + src1.vstride = BRW_VERTICAL_STRIDE_4; > + src1.width = BRW_WIDTH_4; > + src1.hstride = BRW_HORIZONTAL_STRIDE_0; > + src1.subnr = 2 * sizeof(flo

Re: [Mesa-dev] [PATCH 15/17] intel/compiler: Add instruction compaction support on Gen11

datatype_table) - 1] != 0); > > switch (devinfo->gen) { > + case 11: > + control_index_table = gen8_control_index_table; > + datatype_table = gen11_datatype_table; > + subreg_table = gen8_subreg_table; > + src_index_table = gen8_src_index_table; >

Re: [Mesa-dev] [PATCH 16/17] intel/compiler: Disable Align16 tests on Gen11+

On Tuesday, February 20, 2018 9:15:23 PM PST Matt Turner wrote: > Align16 is no more. Patches 16-17 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mai

Re: [Mesa-dev] [PATCH 14/17] intel/compiler: Mark line, pln, and lrp as removed on Gen11+

t;, .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6) & > GEN_LE(GEN10), > }, > [93] = { >.name = "madm",.nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8), > @@ -662,6 +663,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo) >

Re: [Mesa-dev] [PATCH 09/17] intel/compiler/fs: Don't generate integer DWord multiply on Gen11

| 6 +- > 3 files changed, 6 insertions(+), 5 deletions(-) That's too bad. Correct, though. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___

Re: [Mesa-dev] [PATCH 08/17] intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pair

bout that. With this ordering, patch 7 will break LINE/MAC and patch 8 will fix it...so at least that much needs changing. I'm fine with handling this explicitly, so it's: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> but we could also just...

Re: [Mesa-dev] [PATCH 13/17] intel/compiler: Lower flrp32 on Gen11+

itional precision, which GL doesn't require. It looks like that would be 4 MADs in SIMD16 vs. add/mul/neg, so I think lowering is the right call here. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___

Re: [Mesa-dev] [PATCH 06/17] intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+

t_default_saturate() is called before emitting > instructions, > + * so the saturate bit is set in each instruction, so we need to > unset > + * it on the first instruction of each pair. > + */ > + brw_inst_set

Re: [Mesa-dev] [PATCH 07/17] intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

On Friday, February 23, 2018 3:51:37 PM PST Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:14 PM PST Matt Turner wrote: > > If multiple instructions are emitted, special handling of things like > > conditional mod, saturate, and NoDDClr/NoDDChk need to be performed. >

Re: [Mesa-dev] [PATCH 07/17] intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

On Tuesday, February 20, 2018 9:15:14 PM PST Matt Turner wrote: > If multiple instructions are emitted, special handling of things like > conditional mod, saturate, and NoDDClr/NoDDChk need to be performed. > > I noticed that conditional mods were misapplied when adding support for > Gen11 (in

[Mesa-dev] [PATCH 1/4] glsl: Add a SYSTEM_BIT_PRIMITIVE_ID #define.

Less typing than ((uint64_t)1 << SYSTEM_VALUE_PRIMITIVE_ID). --- src/compiler/shader_enums.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h index ac83c65b30c..33a9d3d8a1d 100644 --- a/src/compiler/shader_enums.h +++

[Mesa-dev] [PATCH 4/4] i965: Implement dual-patch tessellation evaluation shaders.

Normally, SIMD8 tessellation evaluation shaders operate on a single patch, with each channel operating on a different vertex within the patch. For patch primitives with fewer than 8 vertices, this means that some of the channels are disabled, effectively wasting compute power. This is a fairly

[Mesa-dev] [PATCH 2/4] i965: Add a copy constructor (of sorts) for cfg_t.

This clones an existing CFG. We can't properly copy the instruction lists from cfg_t itself, as it's fs_inst/vec4_instruction agnostic, and we don't use templates. To accomplish this, we pass in an instruction-list-copying function. --- src/intel/compiler/brw_cfg.cpp | 41

[Mesa-dev] [PATCH 3/4] i965: Don't set alloc.count = grf_used.

alloc is about virtual registers, and grf_used is the number of actual hardware registers used. alloc's information is not terribly useful after register allocation, but there's no real use in conflating them. I plan to generate two CFGs from a single fs_visitor invocation, each representing a

Re: [Mesa-dev] [PATCH 05/17] intel/compiler: Add Gen11+ native float type

but...probably good enough for our purposes here... Patches 3-4 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.

Re: [Mesa-dev] [PATCH] intel: aubinator_error_decode: fix segfault on missing register

*reg_spec = !name ? NULL : gen_spec_find_register_by_name(spec, name); or struct gen_group *reg_spec = name ? gen_spec_find_register_by_name(spec, name) : NULL; because assignments in expressions, giving them side-effects, can be a bit surprising, while ternaries are common and straig

Re: [Mesa-dev] [ANNOUNCE] Mesa 17.3.4 release candidate

On Thursday, February 8, 2018 8:47:00 PM PST Emil Velikov wrote: > Rejected (9) > > Jason Ekstrand (2): > e52a9f18d69c94b7cb7f81361cdb9e2582c3d742 i965: Replace > draw_aux_buffer_disabled with draw_aux_usage > 20f70ae3858bc213e052a8434f0e637eb36203c4 i965/draw: Set >

[Mesa-dev] [PATCH] glsl: Parse 'layout' as a token with advanced blending or bindless

Both KHR_blend_equation_advanced and ARB_bindless_texture provide layout qualifiers, and are exposed in compatibility contexts. We need to parse the layout qualifier as a token in order for those to work, but forgot to extend this check. ARB_shader_image_load_store would need a similar

Re: [Mesa-dev] [PATCH] anv/gpu_memcpy: CS Stall before a MI memcpy on gen7

s for BLORP to fix the same issue. These shouldn't > actually do anything right now because the only use of indirect clears > in BLORP today is for resolves which are already guarded by a render > cache flush and CS stall. However, this will guard us against potential > issues in the

[Mesa-dev] [PATCH 2/2] i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.

By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic state base address. This makes it unusable for pushing UBOs. There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake) which controls whether buffer 0 is relative to dynamic state base address, or simply a normal

[Mesa-dev] [PATCH 1/2] i965: Stop restoring the default L3 configuration on Kernel 4.16+.

Kernel 4.16 has proper context isolation, which means we can change the L3 configuration without worrying about that leaking to other newly created contexts, breaking the assumptions of other userspace. So, disable our workaround to reprogram it back to the default. ---

Re: [Mesa-dev] [PATCH v2 1/2] glsl/nir: add pixel_center_integer to shader info

-164,6 +164,8 @@ typedef struct shader_info { > > bool post_depth_coverage; > > + bool pixel_center_integer; > + > /** gl_FragDepth layout for ARB_conservative_depth. */ > enum gl_frag_depth_layout depth_layout; >

Re: [Mesa-dev] [PATCH V2 16/16] i965/icl: Add render target flush after uploading binding table

> > + Target Cache Flush by enabling this bit. When render target flush > > + is set due to new association of BTI, PS Scoreboard Stall bit must > > + be set in this packet." > > + */ Mesa coding style is: /* The PIPE_CONTROL command

Re: [Mesa-dev] [PATCH 14/16] intel/common/icl: Add has_sample_with_hiz flag in gen_device_info

dding device info for gen11. > > Suggested-by: Kenneth Graunke <kenn...@whitecape.org> > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> > Cc: Kenneth Graunke <kenn...@whitecape.org> > --- > src/intel/common/gen_device_info.c| 7 +++ >

[Mesa-dev] [PATCH] i965: Drop EXEC_OBJECT_CAPTURE defines.

These only existed to avoid making people update libdrm for new uABI headers. A while ago we imported those headers into the Mesa repo, so the dependency is gone and these are no longer useful. --- src/mesa/drivers/dri/i965/brw_bufmgr.h | 3 --- 1 file changed, 3 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

On Wednesday, February 14, 2018 10:17:07 AM PST Jason Ekstrand wrote: > On Wed, Feb 14, 2018 at 10:12 AM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > > On Wednesday, February 14, 2018 6:05:22 AM PST Marek Olšák wrote: > > > On Wed, Feb 14, 2018 at

Re: [Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

On Wednesday, February 14, 2018 6:05:22 AM PST Marek Olšák wrote: > On Wed, Feb 14, 2018 at 7:57 AM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > On Tuesday, February 13, 2018 2:57:07 PM PST Jason Ekstrand wrote: > >> This fixes the build in clang > >>

Re: [Mesa-dev] [PATCH 2/2] anv/pipeline: Set the correct binding count for compute shaders

On Wednesday, February 14, 2018 8:28:54 AM PST Jason Ekstrand wrote: > On Tue, Feb 13, 2018 at 11:06 PM, Kenneth Graunke <kenn...@whitecape.org> > wrote: > > > On Monday, February 12, 2018 7:35:05 PM PST Jason Ekstrand wrote: > > > --- > > > src/intel/vulk

Re: [Mesa-dev] [PATCH] i965: Enable disk shader cache by default

t; { > #ifdef ENABLE_SHADER_CACHE > - if (env_var_as_boolean("MESA_GLSL_CACHE_DISABLE", true)) > - return; > - > char renderer[10]; > MAYBE_UNUSED int len = snprintf(renderer, sizeof(renderer), "i965_%04x", >

Re: [Mesa-dev] [RFC 2/2] anv: enable VK_EXT_shader_stencil_export

On Sunday, February 11, 2018 6:26:41 PM PST Gustavo Lima Chaves wrote: > --- > src/intel/vulkan/anv_extensions.py | 1 + > src/intel/vulkan/anv_pipeline.c| 1 + > 2 files changed, 2 insertions(+) > > diff --git a/src/intel/vulkan/anv_extensions.py > b/src/intel/vulkan/anv_extensions.py >

Re: [Mesa-dev] [RFC 0/2] VK_EXT_shader_stencil_export

On Sunday, February 11, 2018 6:26:39 PM PST Gustavo Lima Chaves wrote: > I've been seeking to add this extension support on my free time and > have now come to a point where some input could really help. Hi Gustavo! Welcome to the Mesa community :) Thanks for taking a shot at this! > At

Re: [Mesa-dev] [PATCH 1/5] i965/tiled_memcpy: change linear pointer from (0, 0) to (xt1, yt1)

rivers/dri/i965/intel_tex_image.c| 4 ++-- > src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 16 > 3 files changed, 11 insertions(+), 11 deletions(-) Patches 1 and 3 are: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Feel free to push those two (assuming yo

Re: [Mesa-dev] [PATCH 1/2] intel/aubinator: Correctly decode INTERFACE_DESCRIPTOR_DATA

printf(ctx->fp, "descriptor %d: %08x\n", i, descriptor_offset); > > - ctx_print_group(ctx, inst, desc_addr, desc_map); > + ctx_print_group(ctx, desc, desc_addr, desc_map); > >gen_field_iterator_init(, desc, desc_map, 0, false); >uint64_t ks

Re: [Mesa-dev] [PATCH 2/2] anv/pipeline: Set the correct binding count for compute shaders

On Monday, February 12, 2018 7:35:05 PM PST Jason Ekstrand wrote: > --- > src/intel/vulkan/genX_pipeline.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/intel/vulkan/genX_pipeline.c > b/src/intel/vulkan/genX_pipeline.c > index 45ebe31..4aee9ec 100644 > ---

Re: [Mesa-dev] [PATCH] i965: Add gl_state_index casts for PATCH_VERTICES_IN

On Tuesday, February 13, 2018 2:57:07 PM PST Jason Ekstrand wrote: > This fixes the build in clang > --- > src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp >

Re: [Mesa-dev] [PATCH 1/2] nir: retain pixel_center_integer information when lowering gl_FragCoord

On Tuesday, February 13, 2018 10:00:44 PM PST Timothy Arceri wrote: > On 14/02/18 16:24, Jason Ekstrand wrote: > > First off, you should add an index to the intrinsic if you're going to > > do this and it should probably be set elsewhere. Otherwise, it becomes > > this magic secret radeonsi

Re: [Mesa-dev] [PATCH 05/16] intel/isl/icl: Build and use gen11 surface state emit functions

el/isl/isl.c| 3 +++ > src/intel/isl/isl_priv.h | 3 +++ > src/intel/isl/meson.build | 2 +- > 6 files changed, 35 insertions(+), 1 deletion(-) I barely skimmed this, trusting that Dylan had looked in more detail, but since I reviewed the rest of the series, you may as well hav

Re: [Mesa-dev] [PATCH 03/16] intel/genxml/icl: Update genx_bits header

; { > switch (devinfo->gen) { > + case 11: return ${item.get_prop(prop, 11)}; > case 10: return ${item.get_prop(prop, 10)}; > case 9: return ${item.get_prop(prop, 9)}; > case 8: return ${item.get_prop(prop, 8)}; > Reviewed-by: Kenneth Graunke <kenn...@w

Re: [Mesa-dev] [PATCH 08/16] i965/icl: Build and use gen11 functions for genxml state-upload and blorp

On Tuesday, February 13, 2018 11:15:08 AM PST Anuj Phogat wrote: > Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part. _

Re: [Mesa-dev] [PATCH 07/16] i965/icl: Don't set ResetGatewayTimer

g we don't need to, and could have just used the "keep the timestamp" value...deleting this code entirely. But, I'm not sure either. For now, this seems like a good plan. Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed me

Re: [Mesa-dev] [PATCH 10/16] i965/icl: Define and use icl mocs settings

by the kernel...we were already relying on the fact that SKL_MOCS_* == CNL_MOCS_* in some places... But, we can clean it up later...so... Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> signature.asc Description: This is a digitally signed message part.

Re: [Mesa-dev] [PATCH 11/16] i965/icl: Update the assert in brw_memory_barrier()

mp; devinfo->gen <= 10); > + assert(devinfo->gen >= 7 && devinfo->gen <= 11); > > if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT | > GL_ELEMENT_ARRAY_BARRIER_BIT | > Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> sign

Re: [Mesa-dev] [PATCH 02/16] intel/genxml/icl: Generate packing headers

en_macros.h | 3 +++ > 4 files changed, 12 insertions(+), 1 deletion(-) No Meson changes in this patch. It looks like the addition in the previous patch may have been sufficient. It's kind of weird to have the build systems in different patches. I might squash this, but it's up to you. Eithe

Re: [Mesa-dev] [PATCH 14/16] i965/icl: Disable HiZ surface sampling

On Tuesday, February 13, 2018 11:15:14 AM PST Anuj Phogat wrote: > On gen11+ AUX_HIZ is not a supported value for surfaces being > sampled by the 3D sampler. > > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++-- > 1 file changed,

Re: [Mesa-dev] [PATCH 16/16] i965/icl: Add render target flush after uploading binding table

On Tuesday, February 13, 2018 11:15:16 AM PST Anuj Phogat wrote: > From PIPE_CONTROL command description in gfxspecs: > > "Whenever a Binding Table Index (BTI) used by a Render Taget Message > points to a different RENDER_SURFACE_STATE, SW must issue a Render > Target Cache Flush by enabling

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