Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
src/amd/vulkan/si_cmd_buffer.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 3d6c672dd0f..d48ed804e63 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -311,6 +311,7 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
late_alloc_limit = (num_cu_per_sh - 2) * 4;
}
+ unsigned late_alloc_limit_gs = late_alloc_limit;
unsigned cu_mask_vs = 0xffff;
unsigned cu_mask_gs = 0xffff;
@@ -324,6 +325,12 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
}
}
+ /* Don't use late alloc for NGG on Navi14 due to a hw bug. */
+ if (physical_device->rad_info.family == CHIP_NAVI14) {
+ late_alloc_limit_gs = 0;
+ cu_mask_gs = 0xffff;
+ }
+
radeon_set_sh_reg_idx(physical_device, cs,
R_00B118_SPI_SHADER_PGM_RSRC3_VS,
3, S_00B118_CU_EN(cu_mask_vs) |
S_00B118_WAVE_LIMIT(0x3F));
@@ -336,7 +343,7 @@ si_emit_graphics(struct radv_physical_device
*physical_device,
if (physical_device->rad_info.chip_class >= GFX10) {
radeon_set_sh_reg_idx(physical_device, cs,
R_00B204_SPI_SHADER_PGM_RSRC4_GS,
3, S_00B204_CU_EN(0xffff) |
-
S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
+
S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs));
}
radeon_set_sh_reg_idx(physical_device, cs,
R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
--
2.22.0
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