Re: [PATCH net-next v3 0/2] net: stmmac: Coalesce and tail addr fixes

On Thu, 2018-09-13 at 09:02 +0100, Jose Abreu wrote: > The fix for coalesce timer and a fix in tail address setting that impacts > XGMAC2 operation. > > Cc: Florian Fainelli > Cc: Neil Armstrong > Cc: Jerome Brunet > Cc: Martin Blumenstingl > Cc: David S. Miller

Re: [PATCH net-next 1/2] net: stmmac: Rework coalesce timer and fix multi-queue races

On Tue, 2018-09-04 at 10:57 +0100, Jose Abreu wrote: > Hi Jerome, > > On 03-09-2018 17:22, Jerome Brunet wrote: > > > > Situation is even worse with this. > > I'm using an NFS root filesystem. With your fixup, I'm not reaching the > > prompt > > anymore

Re: [RFT net-next] net: stmmac: Rework coalesce timer and fix multi-queue races

On Mon, 2018-09-03 at 16:47 +0100, Jose Abreu wrote: > On 03-09-2018 16:38, Jerome Brunet wrote: > > On Mon, 2018-09-03 at 16:22 +0100, Jose Abreu wrote: > > > On 03-09-2018 15:10, Jerome Brunet wrote: > > > > On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote:

Re: [PATCH net-next 1/2] net: stmmac: Rework coalesce timer and fix multi-queue races

On Mon, 2018-09-03 at 16:19 +0100, Jose Abreu wrote: > On 03-09-2018 15:07, Jerome Brunet wrote: > > > > You had it on what you sent in the RFT, but this different. > > Yeah, I had to fix the logic where tx queues != rx queues... > > > > > Like with t

Re: [RFT net-next] net: stmmac: Rework coalesce timer and fix multi-queue races

On Mon, 2018-09-03 at 16:22 +0100, Jose Abreu wrote: > On 03-09-2018 15:10, Jerome Brunet wrote: > > On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote: > > > On 03-09-2018 11:16, Jerome Brunet wrote: > > > > No notable change. Rx is fine but Tx: > > > >

Re: [RFT net-next] net: stmmac: Rework coalesce timer and fix multi-queue races

On Mon, 2018-09-03 at 12:47 +0100, Jose Abreu wrote: > On 03-09-2018 11:16, Jerome Brunet wrote: > > No notable change. Rx is fine but Tx: > > [ 5] 3.00-4.00 sec 3.55 MBytes 29.8 Mbits/sec 51 12.7 KBytes > > > > I suppose the problem as something to do with

Re: [PATCH net-next 1/2] net: stmmac: Rework coalesce timer and fix multi-queue races

he coalesce frames > to 25. > > Tested in B2B setup between XGMAC2 and GMAC5. > > Signed-off-by: Jose Abreu > Cc: Jerome Brunet > Cc: Martin Blumenstingl > Cc: David S. Miller > Cc: Joao Pinto > Cc: Giuseppe Cavallaro > Cc: Alexandre Torgue > --- > J

Re: [RFT net-next] net: stmmac: Rework coalesce timer and fix multi-queue races

On Mon, 2018-09-03 at 10:36 +0100, Jose Abreu wrote: > Hi Jerome, > > On 03-09-2018 09:56, Jerome Brunet wrote: > > On Thu, 2018-08-30 at 11:37 +0100, Jose Abreu wrote: > > > [ As for now this is only for testing! ] > > > > > > This follows David Mil

Re: [RFT net-next] net: stmmac: Rework coalesce timer and fix multi-queue races

On Thu, 2018-08-30 at 11:37 +0100, Jose Abreu wrote: > [ As for now this is only for testing! ] > > This follows David Miller advice and tries to fix coalesce timer in > multi-queue scenarios. > > We are now using per-queue coalesce values and per-queue TX timer. This > assumes that tx_queues ==

Re: [v3, net-next, 02/12] net: stmmac: Do not keep rearming the coalesce timer in stmmac_xmit

On Fri, 2018-05-18 at 14:55 +0100, Jose Abreu wrote: > This is cutting down performance. Once the timer is armed it should run > after the time expires for the first packet sent and not the last one. > > After this change, running iperf, the performance gain is +/- 24%. Hi Guys, Since v4.18, we

Re: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting

On Thu, 2018-04-26 at 16:05 +, Yixun Lan wrote: > In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer > is extended from bit[0] to bit[2:0]. > There is no problem if we configure it to the RGMII 1000M PHY mode, > since the register setting is coincidentally compatible

[PATCH net-next] net: phy: mdio-mux: slience probe defer error

If we fail to register the mdio bus due to probe defer, we should not print an error message. Just be silent in this case. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/mdio-mux-mmioreg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/d

Re: [net-next PATCH v1 3/3] net: stmmac: dwmac-meson8b: make the clock configurations private

structs out of struct meson8b_dwmac, > so only meson8b_init_rgmii_tx_clk() and the common clock framework know > about these configurations. > > Suggested-by: Jerome Brunet <jbru...@baylibre.com> > Signed-off-by: Martin Blumenstingl <martin.blumensti...@googlemail.com&g

Re: [net-next PATCH v1 1/3] net: stmmac: dwmac-meson8b: simplify clock registration

lt;martin.blumensti...@googlemail.com> Reviewed-by: Jerome Brunet <jbru...@baylibre.com>

Re: [PATCH net-next v5 0/4] dwmac-meson8b: clock fixes for Meson8b

On Tue, 2018-01-16 at 12:17 +0100, Martin Blumenstingl wrote: > > > Hi Martin > > > > > > I'm having problem with this series applied. > > > I've tested on the A113D (AXG) platform, if this patch is applied, the > > > driver will choose MPLL2 as clk source, and seems it doesn't work out > > >

Re: [PATCH net-next v5 0/4] dwmac-meson8b: clock fixes for Meson8b

On Tue, 2018-01-16 at 16:25 +0800, Yixun Lan wrote: > > On 01/16/18 01:10, Martin Blumenstingl wrote: > > Hi Dave, > > > > this series is now successfully tested, thus we think it's ready to be > > applied to your net-next tree. > > > > Emiliano reported [0] that he couldn't get dwmac-meson8b

Re: [RFT net-next v4 2/5] net: stmmac: dwmac-meson8b: simplify generating the clock names

On Mon, 2018-01-15 at 13:02 +0100, Martin Blumenstingl wrote: > > Here you'd allocate memory for each string which will remain until the > > driver > > unload. It's not much, but still, it is wasted memory. > > good catch, thank you! > maybe I should drop this patch for now and clean up the

Re: [RFT net-next v4 3/5] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration

On Mon, 2018-01-15 at 13:08 +0100, Martin Blumenstingl wrote: > can you share your thoughts how to do this? > I can devm_kzalloc the memory for struct clk_mux, clk_divider and > clk_fixed_factor in the function which registers these clocks. but I > cannot declare them on the stack, because the

Re: [RFT net-next v4 5/5] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock

e cannot be changed (which is fine > since it's running at 1GHz, so it's already a multiple of 250MHz and > 125MHz). > > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson > 8b / GXBB DWMAC") > Suggested-by: Jerome Brunet <jbru...@baylibre.c

Re: [RFT net-next v4 3/5] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration

et before, with that non-existing > divide-by-5-or-10 divider). > > Special thanks go to Linus Lüssing for testing the various bits and > checking the results with an oscilloscope on his Odroid-C1! > > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Mes

Re: [RFT net-next v4 2/5] net: stmmac: dwmac-meson8b: simplify generating the clock names

On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote: > Instead of using a custom buffer, snprintf() and devm_kstrdup() we can > simplify this by using devm_kasprintf(). > No functional changes - this just makes the code shorter. CCF copies the name from the init_data to its own

Re: [RFT net-next v4 1/5] net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode

On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote: > [...] > @@ -204,12 +200,24 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac > *dwmac) > > meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, > tx_dly_val <<

Re: [RFT net-next v4 0/5] dwmac-meson8b: clock fixes for Meson8b

68 insertions(+), 56 deletions(-) Ethernet works with this series applied (and tweaked DT patches from Emiliano) Tested-by: Jerome Brunet <jbru...@baylibre.com>

[PATCH net] net: stmmac: enable EEE in MII, GMII or RGMII only

, MII, or RGMII interface." Applying this restriction solves a stability issue observed on Amlogic gxl platforms operating with RMII interface and the internal PHY. Fixes: 83bf79b6bb64 ("stmmac: disable at run-time the EEE if not supported") Signed-off-by: Jerome Brunet <jbru.

Re: [RFT net-next v3 3/5] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration

On Sat, 2017-12-30 at 00:40 +0100, Martin Blumenstingl wrote: > > Maybe this bit 10 is indeed a 5/10 divider, as amlogic claims it is. Maybe, > > as > > Emiliano suggested, the output rate of div250 actually needs to be 250Mhz in > > RGMII, before being divided by 10 to produce the 25MHz of div25

Re: [RFT net-next v3 0/5] dwmac-meson8b: RGMII clock fixes for Meson8b

On Fri, 2017-12-29 at 02:31 +0100, Emiliano Ingrassia wrote: > Hi Martin, Hi Dave, > > On Thu, Dec 28, 2017 at 11:21:23PM +0100, Martin Blumenstingl wrote: > > Hi Dave, > > > > please do not apply this series until it got a Tested-by from Emiliano. > > > > > > Hi Emiliano, > > > > you

Re: [RFT net-next v3 3/5] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration

On Thu, 2017-12-28 at 23:21 +0100, Martin Blumenstingl wrote: > While testing the dwmac-meson8b with an RGMII PHY on Meson8b we > discovered that the m25_div is not actually a divider but rather a gate. > This matches with the datasheet which describes bit 10 as "Generate > 25MHz clock for PHY".

Re: [RFT net-next 2/2] net: stmmac: dwmac-meson8b: don't try to change m250_div parent's rate

On Sat, 2017-12-23 at 22:49 +0100, Martin Blumenstingl wrote: > while calculating this with a target frequency of 500MHz manually > again I saw that there's a remainder of 10Mhz after the initial > division. > remainder * SDM_DEN = 16384000 - this value overflows 32-bit, > things will go

Re: [RFT net-next 2/2] net: stmmac: dwmac-meson8b: don't try to change m250_div parent's rate

On Sat, 2017-12-23 at 21:00 +0100, Martin Blumenstingl wrote: > Hi Jerome, > > On Sat, Dec 23, 2017 at 6:40 PM, Jerome Brunet <jbru...@baylibre.com> wrote: > > On Sat, 2017-12-23 at 18:04 +0100, Martin Blumenstingl wrote: > > > Trying to set the rate of m250_div

Re: [RFT net-next 2/2] net: stmmac: dwmac-meson8b: don't try to change m250_div parent's rate

On Sat, 2017-12-23 at 18:40 +0100, Jerome Brunet wrote: > > Trying to set the rate of m250_div's parent clock makes no sense since > > it's a mux which has neither CLK_MUX_ROUND_CLOSEST nor > > CLK_SET_RATE_PARENT set. > > It even does harm on Meson8b SoCs where the

Re: [RFT net-next 2/2] net: stmmac: dwmac-meson8b: don't try to change m250_div parent's rate

On Sat, 2017-12-23 at 18:04 +0100, Martin Blumenstingl wrote: > Trying to set the rate of m250_div's parent clock makes no sense since > it's a mux which has neither CLK_MUX_ROUND_CLOSEST nor > CLK_SET_RATE_PARENT set. > It even does harm on Meson8b SoCs where the input clock for the mux > cannot

Re: [RFT net-next 1/2] net: stmmac: dwmac-meson8b: fix setting the PHY clock on Meson8b

ti...@googlemail.com> Makes sense to add ROUND_CLOSEST (no risk if the rate is slightly over the requested one) Reviewed-by: Jerome Brunet <jbru...@baylibre.com>

[PATCH net-next v3 0/7] net: phy: meson-gxl: clean-up and improvements

things up a little This series has been tested on the libretech-cc and khadas VIM Changes since v2 [0]: Drop LPA corruption fix which has been merged through net. Apart from this, series remains the same. [0]: https://lkml.kernel.org/r/20171207142715.32578-1-jbru...@baylibre.com Jerome Brunet (7

[PATCH net-next v3 1/7] net: phy: meson-gxl: check phy_write return value

Always check phy_write return values. Better to be safe than sorry Reviewed-by: Andrew Lunn <and...@lunn.ch> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 50 ++--- 1 file changed, 38 insertions(+),

[PATCH net-next v3 5/7] net: phy: meson-gxl: leave CONFIG_A6 untouched

down and soft reset, so we will never see the value which may have been set by the bootloader. In the end, we have used the default configuration so far and there is no reason to change now. Remove CONFIG_A6 poke to make this clear. Reviewed-by: Andrew Lunn <and...@lunn.ch> Signed-off-by:

[PATCH net-next v3 2/7] net: phy: meson-gxl: define control registers

Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meso

[PATCH net-next v3 6/7] net: phy: meson-gxl: add interrupt support

Enable interrupt support in meson-gxl PHY driver Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 37 - 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson

[PATCH net-next v3 3/7] net: phy: meson-gxl: add read and write helpers for banked registers

Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers and what the driver actually does Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/n

[PATCH net-next v3 7/7] net: phy: meson-gxl: join the authors

Following previous changes, join the other authors of this driver and take the blame with them Reviewed-by: Andrew Lunn <and...@lunn.ch> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/n

[PATCH net-next v3 4/7] net: phy: meson-gxl: use genphy_config_init

Use the generic init function to populate some of the phydev structure fields Reviewed-by: Andrew Lunn <and...@lunn.ch> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/n

Re: [PATCH v2] ARM64: dts: meson-axg: add ethernet mac controller

On Thu, 2017-12-14 at 11:02 +0800, Yixun Lan wrote: > --- > Changes in v2 since [1]: > - rebase to kevin's v4.16/dt64 branch > - add Neil's Reviewed-by > - move clock info to board.dts instead of in soc.dtsi You got this comment regarding the pwm clock setup. the setup of the pwm clocks

Re: [PATCH v2] ARM64: dts: meson-axg: add ethernet mac controller

s = "okay"; > }; > + > + { We try to keep nodes alphabetically ordered. Please put ethmac before uart_A0 thx > > With all the dependencies sorted out, it works Tested-by: Jerome Brunet <jbru...@baylibre.com>

Re: [PATCH][next] net: phy: meson-gxl: make function meson_gxl_read_status static

mbol 'meson_gxl_read_status' was not declared. Should it be static? > > Signed-off-by: Colin Ian King <colin.k...@canonical.com> Indeed, silly mistake, thx for spotting it. Reviewed-by: Jerome Brunet <jbru...@baylibre.com>

[PATCH net v3] net: phy: meson-gxl: detect LPA corruption

river") Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- I suppose this patch probably seems a bit hacky, especially the part about the link partner acknowledge. I'm trying to figure out if the value in MII_LPA makes sense but I don't have such a deep knowledge of the ethernet spec.

Re: [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers

On Thu, 2017-12-07 at 16:46 +0100, Andrew Lunn wrote: > On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote: > > Add read and write helpers to manipulate banked registers on this PHY > > This helps clarify the settings applied to these registers in the init > >

Re: [PATCH net-next v2 6/8] net: phy: meson-gxl: leave CONFIG_A6 untouched

On Thu, 2017-12-07 at 16:49 +0100, Andrew Lunn wrote: > On Thu, Dec 07, 2017 at 03:27:13PM +0100, Jerome Brunet wrote: > > The PHY performs just as well when left in its default configuration and > > it makes senses because this poke gets reset just after init. > > The o

Re: [PATCH net-next v2 5/8] net: phy: meson-gxl: detect LPA corruption

On Thu, 2017-12-07 at 17:12 +0100, Andrew Lunn wrote: > > Would it be Ok if send patches 1 to 5 to net ? > > and 6 to 8 separately on net-next ? > > No. The rules for stable is that a patch must really fix something and > be minimal. > > Documentation/process/stable-kernel-rules.rst > > What

Re: [PATCH net-next v2 7/8] net: phy: meson-gxl: add interrupt support

On Thu, 2017-12-07 at 16:54 +0100, Andrew Lunn wrote: > On Thu, Dec 07, 2017 at 03:27:14PM +0100, Jerome Brunet wrote: > > Enable interrupt support in meson-gxl PHY driver > > Hi Jerome > > Is it possible to implement did_interrupt()? That allows for shared > interrup

Re: [PATCH net-next v2 5/8] net: phy: meson-gxl: detect LPA corruption

On Thu, 2017-12-07 at 16:34 +0100, Andrew Lunn wrote: > On Thu, Dec 07, 2017 at 03:27:12PM +0100, Jerome Brunet wrote: > > The purpose of this change is to fix the incorrect detection of the link > > partner (LP) advertised capabilities which sometimes happens with this PHY >

[PATCH net-next v2 0/8] phy: net: meson-gxl: clean-up and improvements

patch CONFIG_A6 settings is removed since this statement was without effect Finally interrupt support is added, speeding things up a little This series has been tested on the libretech-cc and khadas VIM Jerome Brunet (8): net: phy: meson-gxl: check phy_write return value net: phy: meson-gxl

[PATCH net-next v2 1/8] net: phy: meson-gxl: check phy_write return value

Always check phy_write return values. Better to be safe than sorry Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 50 ++--- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/net/phy/meson-g

[PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers

Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers in the init function and upcoming changes. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c

[PATCH net-next v2 2/8] net: phy: meson-gxl: define control registers

Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meso

[PATCH net-next v2 4/8] net: phy: meson-gxl: use genphy_config_init

Use the generic init function to populate some of the phydev structure fields Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c

[PATCH net-next v2 5/8] net: phy: meson-gxl: detect LPA corruption

river") Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- I suppose this patch probably seems a bit hacky, especially the part about the link partner acknowledge. I'm trying to figure out if the value in MII_LPA makes sense but I don't have such a deep knowledge of the ethernet spec.

[PATCH net-next v2 6/8] net: phy: meson-gxl: leave CONFIG_A6 untouched

the default configuration so far and there is no reason to change now. Remove CONFIG_A6 poke to make this clear. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- Out of curiosity, I tried to re-apply the ANALOG/DSP settings on speed changes (patch available here [0] if someone wants to try)

[PATCH net-next v2 7/8] net: phy: meson-gxl: add interrupt support

Enable interrupt support in meson-gxl PHY driver Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 37 - 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson

[PATCH net-next v2 8/8] net: phy: meson-gxl: join the authors

Following previous changes, join the other authors of this driver and take the blame with them Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/meson-gxl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c

Re: [PATCH net-next] net: phy: meson-gxl: cleanup by defining the control registers

On Tue, 2017-12-05 at 19:01 +0100, Andrew Lunn wrote: > On Tue, Dec 05, 2017 at 10:33:34AM +0100, Jerome Brunet wrote: > > From: Neil Armstrong <narmstr...@baylibre.com> > > > > Define registers and bits in meson-gxl PHY driver to make a bit > > more hum

Re: [PATCH net-next] net: phy: meson-gxl: cleanup by defining the control registers

On Tue, 2017-12-05 at 23:23 +0800, Yixun Lan wrote: > > +static inline int meson_gxl_write_reg(struct phy_device *phydev, > > + unsigned int bank, unsigned int reg, > > + uint16_t value) > > +{ > > + int ret; > > + > > +

[RFC PATCH] net: stmmac: enable EEE in MII, GMII or RGMII only

, MII, or RGMII interface." Applying this restriction solves a stability issue observed on Amlogic gxl platforms operating with RMII interface and the internal PHY. Fixes: 83bf79b6bb64 ("stmmac: disable at run-time the EEE if not supported") Signed-off-by: Jerome Brunet <jbru..

[PATCH net-next] net: phy: meson-gxl: cleanup by defining the control registers

From: Neil Armstrong <narmstr...@baylibre.com> Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/n

Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode

t; > With this patch the phy is working properly in interrupt mode. > > Signed-off-by: Heiner Kallweit <hkallwe...@gmail.com> Tested-by: Jerome Brunet <jbru...@baylibre.com>

Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode

On Sun, 2017-11-12 at 21:06 +0100, Andrew Lunn wrote: > On Sun, Nov 12, 2017 at 07:36:48PM +0100, Jerome Brunet wrote: > > On Sun, 2017-11-12 at 19:25 +0100, Andrew Lunn wrote: > > > On Sun, Nov 12, 2017 at 04:16:04PM +0100, Heiner Kallweit wrote: > > > > After co

Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode

On Sun, 2017-11-12 at 10:29 -0800, Florian Fainelli wrote: > Hi Heiner, > > On 11/12/2017 07:16 AM, Heiner Kallweit wrote: > > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY > > interrupt on some platforms" ethernet stopped working on my Odroid-C2 > > which has a RTL8211F phy.

Re: [PATCH] net: phy: realtek: fix RTL8211F interrupt mode

On Sun, 2017-11-12 at 19:25 +0100, Andrew Lunn wrote: > On Sun, Nov 12, 2017 at 04:16:04PM +0100, Heiner Kallweit wrote: > > After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY > > interrupt on some platforms" ethernet stopped working on my Odroid-C2 > > which has a RTL8211F phy. >

[PATCH net] net: phy: Kconfig: Fix PHY infrastructure menu in menuconfig

-language.txt, section "Menu structure", 2nd method. This is fixed by placing the PHYLINK option just before PHYLIB. Fixes: 9525ae83959b ("phylink: add phylink infrastructure") Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/Kconfig | 18 +--

Re: ARM GLX Khadas VIM Pro - Ethernet detected as only 10Mbps and stalled after some traffic

On Tue, 2017-07-25 at 18:56 +0200, crow wrote: > Hi, > Today I did test on ArchLinuxArm the Kernel v4.13-rc2. On downloading > the linux git source the network will eventually get stalled. Here are > the information > > Over SSH (network works). > > [root@alarm ~]# uname -a > Linux alarm

Re: ARM GLX Khadas VIM Pro - Ethernet detected as only 10Mbps and stalled after some traffic

On Sun, 2017-06-11 at 08:31 +0200, crow wrote: > Hi Andrew, > > On Sat, Jun 10, 2017 at 5:27 PM, Andrew Lunn wrote: > > > Also what Martin Blumenstingl wrote is following which is also crucial > > > for fixing the issue: > > > Amlogic has given their ethernet PHY driver some

Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue

On Fri, 2017-01-06 at 11:42 +, Russell King - ARM Linux wrote: > On Fri, Jan 06, 2017 at 11:11:36AM +0100, Jerome Brunet wrote: > > > > The purpose of this patch is to provide a way to mark as broken a > > particular eee mode. At first, it had nothin

Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue

On Thu, 2017-01-05 at 23:25 +, Russell King - ARM Linux wrote: > On Mon, Nov 28, 2016 at 09:54:28AM -0800, Florian Fainelli wrote: > > > > If we start supporting generic "enable", "disable" type of > > properties > > with values that map directly to register definitions of the HW, we > >

Re: [PATCH net-next v4 2/4] dt-bindings: net: add EEE capability constants

, Rob Herring wrote: > On Mon, Nov 28, 2016 at 04:50:26PM +0100, Jerome Brunet wrote: > > > > Signed-off-by: Jerome Brunet <jbru...@baylibre.com> > > Tested-by: Yegor Yefremov <yegorsli...@googlemail.com> > > Tested-by: Andreas Färber <afaer...@suse.

[PATCH net 0/3] Fix integration of eee-broken-modes

r each EEE broken mode. [0]: http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbru...@baylibre.com [1]: http://lkml.kernel.org/r/1480348229-25672-1-git-send-email-jbru...@baylibre.com [2]: http://lkml.kernel.org/r/e14a3b0c-dc34-be14-48b3-518a0ad0c...@gmail.com Jerome Brunet (3): net

[PATCH net 3/3] dt: bindings: net: use boolean dt properties for eee broken modes

com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- Documentation/devicetree/bindings/net/phy.txt | 10 -- include/dt-bindings/net/mdio.h| 19 --- 2 files changed, 8 insertions(+), 21 deletions(-) delete mode 100644 include/dt-bindings/net/

[PATCH net 2/3] net: phy: use boolean dt properties for eee broken modes

com> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/phy_device.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index ee5ebadb1463..92b08383cafa 100644 --- a/dri

[PATCH net 1/3] net: phy: fix sign type error in genphy_config_eee_advert

e EEE advertisement") Reported-by: Julia Lawall <julia.law...@lip6.fr> Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/phy_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_devic

Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue

On Mon, 2016-11-28 at 09:54 -0800, Florian Fainelli wrote: > On 11/28/2016 07:50 AM, Jerome Brunet wrote: > > > > This patchset fixes an issue with the OdroidC2 board (DWMAC + > > RTL8211F). > > The platform seems to enter LPI on the Rx path too often while > >

[PATCH net-next v4 3/4] dt: bindings: add ethernet phy eee-broken-modes option documentation

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> Reviewed-by: Andreas Färber <afaer...@suse.de> Tested-by: Neil Armstrong <narmstr...@baylibre.com> --- Documentation/devicetree/bindings/net/phy.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devic

[PATCH net-next v4 1/4] net: phy: add an option to disable EEE advertisement

provides a convenient way for these platforms to disable EEE advertisement and work around the issue. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> Tested-by: Yegor Yefremov <yegorsli...@googlemail.com> Tested-by: Andreas Färber <afaer...@suse.de> Tested-by: Neil Armstrong <na

[PATCH net-next v4 4/4] ARM64: dts: meson: odroidc2: disable advertisement EEE for GbE.

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> Tested-by: Neil Armstrong <narmstr...@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts

[PATCH net-next v4 2/4] dt-bindings: net: add EEE capability constants

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> Tested-by: Yegor Yefremov <yegorsli...@googlemail.com> Tested-by: Andreas Färber <afaer...@suse.de> Tested-by: Neil Armstrong <narmstr...@baylibre.com> --- include/dt-bindings/net/mdio.h | 19 +++ 1 fil

[PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue

79742524-30222-1-git-send-email-jbru...@baylibre.com [3] : http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbru...@baylibre.com Jerome Brunet (4): net: phy: add an option to disable EEE advertisement dt-bindings: net: add EEE capability constants dt: bindings: add ethernet phy eee

Re: [PATCH net-next v3 4/4] ARM64: dts: meson: odroidc2: disable advertisement EEE for GbE.

On Mon, 2016-11-28 at 13:31 +0100, Andreas Färber wrote: > Am 28.11.2016 um 10:46 schrieb Jerome Brunet: > > > > Signed-off-by: Jerome Brunet <jbru...@baylibre.com> > > --- > >  arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 16 > >

[PATCH net-next v3 0/4] Fix OdroidC2 Gigabit Tx link issue

79220154-25851-1-git-send-email-jbru...@baylibre.com [2] : http://lkml.kernel.org/r/1479742524-30222-1-git-send-email-jbru...@baylibre.com Jerome Brunet (4): net: phy: add an option to disable EEE advertisement dt-bindings: net: add EEE capability constants dt: bindings: add ethernet phy eee

[PATCH net-next v3 1/4] net: phy: add an option to disable EEE advertisement

provides a convenient way for these platforms to disable EEE advertisement and work around the issue. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/phy.c| 3 ++ drivers/net/phy/phy_device.c | 80 +++- include/linux

[PATCH net-next v3 2/4] dt-bindings: net: add EEE capability constants

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- include/dt-bindings/net/mdio.h | 19 +++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/net/mdio.h diff --git a/include/dt-bindings/net/mdio.h b/include/dt-bindings/net/mdio.h new file mode

[PATCH net-next v3 4/4] ARM64: dts: meson: odroidc2: disable advertisement EEE for GbE.

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts

[PATCH net-next v3 3/4] dt: bindings: add ethernet phy eee-broken-modes option documentation

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- Documentation/devicetree/bindings/net/phy.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 4627da3d52c4..54749b60a466

Re: [PATCH net-next v3 0/4] Documentation: net: phy: Improve documentation

lorian. This is really helping, especially the part about RGMII delays. Reviewed-by: Jerome Brunet <jbru...@baylibre.com> > Florian Fainelli (4): >   Documentation: net: phy: remove description of function pointers >   Documentation: net: phy: Add a paragraph about pause fram

Re: [RFC PATCH net v2 0/3] Fix OdroidC2 Gigabit Tx link issue

On Thu, 2016-11-24 at 18:10 +0100, Martin Blumenstingl wrote: > On Thu, Nov 24, 2016 at 5:01 PM, Jerome Brunet <jbru...@baylibre.com> > wrote: > > > > On Thu, 2016-11-24 at 15:40 +0100, Martin Blumenstingl wrote: > > > > > > Hi Jerome, > > > &

Re: [net-next PATCH v1 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay

On Thu, 2016-11-24 at 18:05 +0100, Martin Blumenstingl wrote: > On Thu, Nov 24, 2016 at 4:56 PM, Jerome Brunet <jbru...@baylibre.com> > wrote: > > > > On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote: > > > > > > Currently the dwmac-meson8b s

Re: [net-next PATCH v1 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay

On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote: > Currently the dwmac-meson8b stmmac glue driver uses a hardcoded 1/4 > cycle TX clock delay. This seems to work fine for many boards (for > example Odroid-C2 or Amlogic's reference boards) but there are some > others where TX traffic

Re: [RFC PATCH net v2 0/3] Fix OdroidC2 Gigabit Tx link issue

On Thu, 2016-11-24 at 15:40 +0100, Martin Blumenstingl wrote: > Hi Jerome, > > On Mon, Nov 21, 2016 at 4:35 PM, Jerome Brunet <jbru...@baylibre.com> > wrote: > > > > This patchset fixes an issue with the OdroidC2 board (DWMAC + > > RTL8211F). > > Initi

Re: [net-next PATCH v1 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay

On Thu, 2016-11-24 at 15:34 +0100, Martin Blumenstingl wrote: > Currently the dwmac-meson8b stmmac glue driver uses a hardcoded 1/4 > cycle TX clock delay. This seems to work fine for many boards (for > example Odroid-C2 or Amlogic's reference boards) but there are some > others where TX traffic

Re: [RFC PATCH net v2 2/3] dt: bindings: add ethernet phy eee-disable-advert option documentation

On Mon, 2016-11-21 at 21:35 -0800, Florian Fainelli wrote: > Le 21/11/2016 à 08:47, Andrew Lunn a écrit : > > > > > > > > What I did not realize when doing this patch for the realtek > > > driver is > > > that there is already 6 valid modes defined in the kernel > > > > > > #define

Re: [RFC PATCH net v2 2/3] dt: bindings: add ethernet phy eee-disable-advert option documentation

On Mon, 2016-11-21 at 17:01 +0100, Andrew Lunn wrote: > On Mon, Nov 21, 2016 at 04:35:23PM +0100, Jerome Brunet wrote: > > > > Signed-off-by: Jerome Brunet <jbru...@baylibre.com> > > --- > >  Documentation/devicetree/bindings/net/phy.txt | 5 +

[RFC PATCH net v2 3/3] ARM64: dts: meson: odroidc2: disable advertisement EEE for GbE.

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts

[RFC PATCH net v2 2/3] dt: bindings: add ethernet phy eee-disable-advert option documentation

Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- Documentation/devicetree/bindings/net/phy.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index bc1c3c8bf8fa..7f066b7c1e2c

[RFC PATCH net v2 0/3] Fix OdroidC2 Gigabit Tx link issue

, I can rebase on net-next instead. Chnages since V1: [1] - Disable the advertisement of EEE in the generic code instead of the realtek driver. [1] : http://lkml.kernel.org/r/1479220154-25851-1-git-send-email-jbru...@baylibre.com Jerome Brunet (3): net: phy: add an option to disable EEE

[RFC PATCH net v2 1/3] net: phy: add an option to disable EEE advertisement

provides a convenient way for these platforms to disable EEE advertisement and work around the issue. Signed-off-by: Jerome Brunet <jbru...@baylibre.com> --- drivers/net/phy/phy.c| 3 ++ drivers/net/phy/phy_device.c | 80 +++- include/linux

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