Re: [net-next 2/8] net/mlx5: Configure cache line size for start and end padding

On 2/1/2017 5:12 AM, David Laight wrote: > From: Saeed Mahameed >> Sent: 31 January 2017 20:59 >> From: Daniel Jurgens <dani...@mellanox.com> >> >> There is a hardware feature that will pad the start or end of a DMA to >> be cache line aligned to avoid R

Re: [PATCH net-next 3/9] net/mlx4_core: Set EQ affinity hint to local NUMA CPUs

On 1/16/2017 3:59 PM, Or Gerlitz wrote: > On Mon, Jan 16, 2017 at 11:54 PM, Daniel Jurgens <dani...@mellanox.com> wrote: >> On 1/16/2017 3:44 PM, Or Gerlitz wrote: >>> On Mon, Jan 16, 2017 at 7:29 PM, Tariq Toukan <tar...@mellanox.com> wrote: >>>>

Re: [PATCH net-next 3/9] net/mlx4_core: Set EQ affinity hint to local NUMA CPUs

On 1/16/2017 3:44 PM, Or Gerlitz wrote: > On Mon, Jan 16, 2017 at 7:29 PM, Tariq Toukan <tar...@mellanox.com> wrote: >> From: Daniel Jurgens <dani...@mellanox.com> >> >> Use CPUs on the close NUMA when setting the EQ affinity hints. > Dan, are we sure ther

Re: [BUG] ethernet:mellanox:mlx5: Oops in health_recover get_nic_state(dev)

On 3/28/2017 4:11 AM, Saeed Mahameed wrote: > On Tue, Mar 28, 2017 at 2:45 AM, Goel, Sameer wrote: >> Stack frame: >> [ 1744.418958] [] get_nic_state+0x24/0x40 [mlx5_core] >> [ 1744.425273] [] health_recover+0x28/0x80 [mlx5_core] >> [ 1744.431496] []