16.05.2024 06:45, Li Zhijian wrote:
Make the code more tight.
Suggested-by: Michael Tokarev
Reviewed-by: Peter Xu
Reviewed-by: Zhang Chen
Signed-off-by: Li Zhijian
Signed-off-by: Michael Tokarev
/mjt
---
V2: Collected reviewed-by tags
This change/comment suggested by "Michael Tokarev
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Now that only 6xx cases left in ppc_jumbo_xlate() we can change it
> to ppc_6xx_xlate() also removing get_physical_address_wtlb().
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 5
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx
> in ppc_jumbo_xlate() now.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 150
On Mon May 13, 2024 at 9:28 AM AEST, BALATON Zoltan wrote:
> This function is used only once, its return value is ignored and one
> of its parameter is a return value from a previous call. It is better
> to inline it in the caller and remove it.
Debatable. It's definitely clunky code that could
On 16/05/2024 16.42, Marc Hartmayer wrote:
On Thu, May 09, 2024 at 07:00 PM +0200, Paolo Bonzini
wrote:
Instead of mucking with css_migration_enabled(), add a property specific to
the FLIC device, similar to what is done for TYPE_S390_STATTRIB.
Signed-off-by: Paolo Bonzini
---
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Add ppc_real_mode_xlate() to handle real mode translation and allow
> removing this case from ppc_jumbo_xlate().
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 46
On 16/05/2024 19.43, Peter Maydell wrote:
On Thu, 16 May 2024 at 18:34, Michael S. Tsirkin wrote:
On Thu, May 16, 2024 at 06:29:39PM +0100, Peter Maydell wrote:
On Thu, 16 May 2024 at 17:22, Daniel P. Berrangé wrote:
Currently we have a short paragraph saying that patches must include
a
On Thu May 16, 2024 at 2:31 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> On 5/14/24 08:39, Nicholas Piggin wrote:
> > On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
> >> + qemu-devel
> >>
> >> On 4/23/24 11:40, Harsh Prateek Bora wrote:
> >>> On ppc64, the PowerVM hypervisor
On Thu May 16, 2024 at 11:35 PM AEST, Salil Mehta wrote:
>
> > From: Harsh Prateek Bora
> > Sent: Thursday, May 16, 2024 2:07 PM
> >
> > Hi Salil,
> >
> > On 5/16/24 17:42, Salil Mehta wrote:
> > > Hi Harsh,
> > >
> > >> From: Harsh Prateek Bora
> > >> Sent: Thursday, May 16,
On Mon May 13, 2024 at 9:49 PM AEST, Cédric Le Goater wrote:
> Hello,
>
> On 5/10/24 16:30, Nicholas Piggin wrote:
> > The POWER8 LPC ISA device irqs all get combined and reported to the line
> > connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
> > host controller irqs use
Ping :)
> -Original Message-
> From: Wafer
> Sent: 2024/05/10 15:29
> To: epere...@redhat.com; m...@redhat.com; jasow...@redhat.com
> Cc: qemu-devel@nongnu.org; Angus Chen ;
> Wafer
> Subject: [PATCH v3] hw/virtio: Fix obtain the buffer id from the last
> descriptor
>
> The virtio-1.3
Local variable fence_fd is defined but not used if CONFIG_GBM is
not enabled, and there is compiling problem.
Signed-off-by: Bibo Mao
---
ui/gtk-egl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index 0473f689c9..9831c10e1b 100644
---
With KVM virtualization, debug exception is passthrough to guest kernel
rather than host mode. Here hypercall instruction with special code is used
for sw breakpoint usage.
Now only software breakpoint is supported, and it is allowed to
insert/remove software breakpoint. We can debug guest kernel
Fan,
Many thanks, it helps a lot. Previous I forgot to create a new dax
device(daxctl create-device region0)
Question: Why we need to create a the dax0.1, why the dax0.0 doesn't associate
to the new adding DCD region.
Ira,
Let me try to report a kernel panic.
kernel: dcd-2024-04-17
qemu:
Reviewed-by: Frank Chang
On Thu, May 16, 2024 at 8:34 PM Jerry Zhang Jian
wrote:
> - According to RISC-V crypto spec, Zvkb extension is a proper subset of
> the Zvbb extension.
>
> - Reference:
>
in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240516
for you to fetch changes up to d55d16700a2e2b36c7e34724d4d77f4a75c5243a:
target/loongarch/kvm: fpu save the vreg registers high 192bit (2024-05-16
16:32:35 +0800
On 2024/5/17 1:10, Daniel Henrique Barboza wrote:
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use
On Thu, May 16, 2024 at 9:51 PM Fiona Ebner wrote:
>
> Hi,
>
> Am 08.09.23 um 08:44 schrieb Jason Wang:
> > diff --git a/hw/core/machine.c b/hw/core/machine.c
> > index da699cf..230aab8 100644
> > --- a/hw/core/machine.c
> > +++ b/hw/core/machine.c
> > @@ -38,6 +38,7 @@
> > #include
On Thu, 16 May 2024, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Pass the ram_addr offset to xen_map_cache.
> This is in preparation for adding grant mappings that need
> to compute the address within the RAMBlock.
>
> No functional changes.
>
> Signed-off-by: Edgar E. Iglesias
This plugin uses the new time control interface to make decisions
about the state of time during the emulation. The algorithm is
currently very simple. The user specifies an ips rate which applies
per core. If the core runs ahead of its allocated execution time the
plugin sleeps for a bit to let
From: Alex Bennée
Expose the ability to control time through the plugin API. Only one
plugin can control time so it has to request control when loaded.
There are probably more corner cases to catch here.
From: Alex Bennée
Signed-off-by: Alex Bennée
---
include/qemu/qemu-plugin.h | 23
From: Alex Bennée
We are about to remove direct calls to individual accelerators for
this information and will need a central point for plugins to hook
into time changes.
From: Alex Bennée
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h
From: Alex Bennée
This generalises the qtest_clock_warp code to use the AccelOps
handlers for updating its own sense of time. This will make the next
patch which moves the warp code closer to pure code motion.
From: Alex Bennée
Signed-off-by: Alex Bennée
Acked-by: Thomas Huth
---
The goal here is to be able to scale temporally execution of qemu-user/system,
using a given number of instructions per second.
We define a virtual clock, that can be late or in advance compared to real time.
When we are in advance, we slow execution (by sleeping) until catching real
time.
From: Alex Bennée
Move the key functionality of moving time forward into the clock
sub-system itself. This will allow us to plumb in time control into
plugins.
From: Alex Bennée
Signed-off-by: Alex Bennée
---
include/qemu/timer.h | 15 +++
system/qtest.c | 25
Daniel P. Berrangé writes:
> On Fri, Apr 26, 2024 at 11:20:34AM -0300, Fabiano Rosas wrote:
>> We're enabling using the fdset interface to pass file descriptors for
>> use in the migration code. Since migrations can happen more than once
>> during the VMs lifetime, we need a way to remove an fd
Hi all, sorry to have been away from this thread for a while, I was
trying to catch up on my reviews queue.
Peter Xu writes:
> On Fri, Apr 26, 2024 at 11:20:34AM -0300, Fabiano Rosas wrote:
>> We're enabling using the fdset interface to pass file descriptors for
>> use in the migration code.
On 5/8/24 04:26, Frank Chang wrote:
Hi Daniel,
Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道：
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are
On 15/05/2024 16:30, Richard Henderson wrote:
On 4/29/24 23:02, Richard Henderson wrote:
On 4/29/24 13:52, Mark Cave-Ayland wrote:
No objections here about the remainder of the series, other than that I don't have
an easy/obvious way to test the new instructions...
I was thinking about
On 16.05.24 17:48, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Pass the ram_addr offset to xen_map_cache.
This is in preparation for adding grant mappings that need
to compute the address within the RAMBlock.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
Reviewed-by:
On 16.05.24 17:48, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
For xen, when checking for the first RAM (xen_memory), use
xen_mr_is_memory() rather than checking for a RAMBlock with
offset 0.
All Xen machines create xen_memory first so this has no
functional change for existing
On 16.05.24 17:48, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Always pass address with offset to xen_map_cache().
This is in preparation for support for grant mappings.
Since this is within a block that checks for offset == 0,
this has no functional changes.
Signed-off-by: Edgar E.
* Daniel P. Berrang? [2024-05-16 16:04:24]:
> On Thu, May 16, 2024 at 02:33:47PM +, Srivatsa Vaddagiri wrote:
> > This adds support to launch hypervisor-assisted confidential guests,
> > where guest's memory is protected from a potentially untrusted host.
> > Hypervisor can setup host's
On 5/10/24 08:14, Andrew Jones wrote:
On Fri, May 10, 2024 at 06:36:51PM GMT, Frank Chang wrote:
...
static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
-IOMMUTLBEntry *iotlb)
+IOMMUTLBEntry *iotlb, bool gpa)
{
+dma_addr_t addr, base;
+uint64_t
On Thu, May 16, 2024 at 05:52:43PM +0100, Camilla Conte wrote:
> Enables caching from the qemu-project repository.
>
> Uses a dedicated "$NAME-cache" tag for caching, to address limitations.
> See issue "when using --cache=true, kaniko fail to push cache layer [...]":
>
On Thu, May 16, 2024 at 11:06 AM John Snow wrote:
>
>
> On Thu, May 16, 2024, 5:34 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Add a semantic tag to paragraphs that appear *before* tagged
>> > sections/members/features and those that appear after. This will control
>> > how they
On 5/16/2024 1:24 PM, Michael Galaxy wrote:
On 5/14/24 08:54, Michael Tokarev wrote:
On 5/14/24 16:39, Michael Galaxy wrote:
Steve,
OK, so it does not look like this bugfix you wrote was included in 8.2.4
(which was released yesterday). Unfortunately, that means that anyone using
CPR in
On Tue, May 14, 2024 at 05:57:19PM -0400, John Snow wrote:
> Howdy - this patch series is the first batch of patches meant to prepare
> the QAPI documentation for a new Sphinx module that adds
> cross-references, an index, improved inlining, elision of types unseen
> on the wire, and other
On Thu, 16 May 2024 at 18:34, Michael S. Tsirkin wrote:
>
> On Thu, May 16, 2024 at 06:29:39PM +0100, Peter Maydell wrote:
> > On Thu, 16 May 2024 at 17:22, Daniel P. Berrangé
> > wrote:
> > >
> > > Currently we have a short paragraph saying that patches must include
> > > a Signed-off-by line,
On Thu, May 16, 2024 at 06:34:13PM +0100, Peter Maydell wrote:
> On Thu, 16 May 2024 at 18:20, Michael S. Tsirkin wrote:
> >
> > On Thu, May 16, 2024 at 05:22:27PM +0100, Daniel P. Berrangé wrote:
> > > AFAICT at its current state of (im)maturity the question of licensing
> > > of AI code
On Thu, 16 May 2024 at 18:20, Michael S. Tsirkin wrote:
>
> On Thu, May 16, 2024 at 05:22:27PM +0100, Daniel P. Berrangé wrote:
> > AFAICT at its current state of (im)maturity the question of licensing
> > of AI code generator output does not have a broadly accepted / settled
> > legal position.
On Thu, May 16, 2024 at 06:29:39PM +0100, Peter Maydell wrote:
> On Thu, 16 May 2024 at 17:22, Daniel P. Berrangé wrote:
> >
> > Currently we have a short paragraph saying that patches must include
> > a Signed-off-by line, and merely link to the kernel documentation.
> > The linked kernel docs
On Thu, May 16, 2024 at 05:22:28PM +0100, Daniel P. Berrangé wrote:
> Currently we have a short paragraph saying that patches must include
> a Signed-off-by line, and merely link to the kernel documentation.
> The linked kernel docs have a lot of content beyond the part about
> sign-off an thus
On Thu, May 16, 2024 at 2:01 AM Markus Armbruster wrote:
> John Snow writes:
>
> > If a comment immediately follows a doc block, the parser doesn't ignore
> > that token appropriately. Fix that.
>
> Reproducer?
>
> >
> > Signed-off-by: John Snow
> > ---
> > scripts/qapi/parser.py | 2 +-
> >
These are very compelling results, no?
(40gbps cards, right? Are the cards active/active? or active/standby?)
- Michael
On 5/14/24 10:19, Yu Zhang wrote:
Hello Peter and all,
I did a comparison of the VM live-migration speeds between RDMA and
TCP/IP on our servers
and plotted the results to
On Thu, 16 May 2024 at 17:22, Daniel P. Berrangé wrote:
>
> Currently we have a short paragraph saying that patches must include
> a Signed-off-by line, and merely link to the kernel documentation.
> The linked kernel docs have a lot of content beyond the part about
> sign-off an thus are
On 5/14/24 08:54, Michael Tokarev wrote:
On 5/14/24 16:39, Michael Galaxy wrote:
Steve,
OK, so it does not look like this bugfix you wrote was included in
8.2.4 (which was released yesterday). Unfortunately, that means that
anyone using CPR in that release will still (eventually) encounter
On Thu, May 16, 2024 at 05:22:27PM +0100, Daniel P. Berrangé wrote:
> This patch kicks the hornet's nest of AI / LLM code generators.
>
> With the increasing interest in code generators in recent times,
> it is inevitable that QEMU contributions will include AI generated
> code. Thus far we have
On Tue, May 14, 2024 at 02:16:51AM +, Zhijian Li (Fujitsu) wrote:
> Hi Fan
>
>
> Do you have a newer instruction to play with the DCD. It seems that
> the instruction in RFC[0] doesn't work for current code.
>
> [0] https://lore.kernel.org/all/20230511175609.2091136-1-fan...@samsung.com/
>
On Thu, May 16, 2024 at 05:22:30PM +0100, Daniel P. Berrangé wrote:
> There has been an explosion of interest in so called AI code generators
> in the past year or two. Thus far though, this is has not been matched
> by a broadly accepted legal interpretation of the licensing implications
> for
Hi,
Commit 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
changed 'reg_width' for vector regs, a change that I believe to be
unintended, and we're unable to print vector regs in GDB ATM.
The following is a gdb output of a simple program running with
qemu-riscv64 when trying to print
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.
Cc:
On Tue, May 14, 2024 at 08:28:27AM +, Zhijian Li (Fujitsu) wrote:
>
>
> On 19/04/2024 07:10, nifan@gmail.com wrote:
> > +uint64_t dc_size;
> > +
> > +mr = host_memory_backend_get_memory(ct3d->dc.host_dc);
> > +dc_size = memory_region_size(mr);
> > +region_len =
On Tue, May 14, 2024 at 08:14:59AM +, Zhijian Li (Fujitsu) wrote:
>
>
> On 19/04/2024 07:10, nifan@gmail.com wrote:
> > From: Fan Ni
> >
>
> > +}
> > +
> > static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
> > {
> > DeviceState *ds = DEVICE(ct3d);
> > @@ -635,6
On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> On Thu, Apr 18, 2024 at 04:10:51PM -0700, nifan@gmail.com wrote:
> > A git tree of this series can be found here (with one extra commit on top
> > for printing out accepted/pending extent list):
> >
On Thu, May 16, 2024 at 05:22:29PM +0100, Daniel P. Berrangé wrote:
> Files contributed to QEMU are generally expected to be provided in the
> preferred format for manipulation. IOW, we generally don't expect to
> have generated / compiled code included in the tree, rather, we expect
> to run the
Enables caching from the qemu-project repository.
Uses a dedicated "$NAME-cache" tag for caching, to address limitations.
See issue "when using --cache=true, kaniko fail to push cache layer [...]":
https://github.com/GoogleContainerTools/kaniko/issues/1459
Does not specify a context since no
Hello Zhenzhong,
On 5/15/24 10:20, Zhenzhong Duan wrote:
Hi
This is the last round of cleanup series to change functions in hw/vfio/
to return bool when the error is passed through errp parameter.
The first round is at
https://lists.gnu.org/archive/html/qemu-devel/2024-05/msg01147.html
I
On 5/7/24 08:42, Zhenzhong Duan wrote:
Hi
This is a cleanup series to change functions in hw/vfio/ to return bool
when the error is passed through errp parameter, also some cleanup
with g_autofree.
See discussion at
https://lists.gnu.org/archive/html/qemu-devel/2024-04/msg04782.html
This
On 5/15/24 15:21, Avihai Horon wrote:
Hello,
This series adds a new QAPI event for VFIO device migration state
change. This event will be emitted when a VFIO device changes its
state, for example, during migration or when stopping/starting the
guest.
This event can be used by management
On 5/3/24 16:51, Vinayak Kale wrote:
In case of migration, during restore operation, qemu checks config space of the
pci device with the config space in the migration stream captured during save
operation. In case of config space data mismatch, restore operation is failed.
config space check is
Applied series to vfio-next.
Thanks,
C.
On 4/25/24 11:02, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/vfio/ap.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index
Hi Richard,
On 5/12/24 17:08, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
@@ -2934,6 +2870,184 @@ static bool do_vx_vaddsubcuw(DisasContext
*ctx, arg_VX *a, int add)
return true;
}
+static inline void do_vadd_vsub_sat
+(
+ unsigned vece, TCGv_vec t, TCGv_vec
On 5/16/24 14:46, Cédric Le Goater wrote:
Hello,
The motivation behind these changes is to improve error reporting to
the upper management layer (libvirt) with a more detailed error, this
to let it decide, depending on the reported error, whether to try
migration again later. It would be useful
Files contributed to QEMU are generally expected to be provided in the
preferred format for manipulation. IOW, we generally don't expect to
have generated / compiled code included in the tree, rather, we expect
to run the code generator / compiler as part of the build process.
There are some
There has been an explosion of interest in so called AI code generators
in the past year or two. Thus far though, this is has not been matched
by a broadly accepted legal interpretation of the licensing implications
for code generator outputs. While the vendors may claim there is no
problem and a
This patch kicks the hornet's nest of AI / LLM code generators.
With the increasing interest in code generators in recent times,
it is inevitable that QEMU contributions will include AI generated
code. Thus far we have remained silent on the matter. Given that
everyone knows these tools exist,
Currently we have a short paragraph saying that patches must include
a Signed-off-by line, and merely link to the kernel documentation.
The linked kernel docs have a lot of content beyond the part about
sign-off an thus are misleading/distracting to QEMU contributors.
This introduces a dedicated
Hi Richard,
On 5/12/24 15:59, Richard Henderson wrote:
On 5/12/24 11:38, Chinmay Rath wrote:
1. vsubsbs and bcdtrunc :
In this pair, bcdtrunc has the insn flag check PPC2_ISA300 in the
vmx-impl file, within the GEN_VXFORM_DUAL macro, which does this flag
check.
However it also has this flag
Hi Eric,
On Wed, May 15, 2024 at 03:15:02PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
> > In "5.2 Stream Table Entry":
> > [51:6] S1ContextPtr
> > If Config[1] == 1 (stage 2
From: "Edgar E. Iglesias"
For xen, when checking for the first RAM (xen_memory), use
xen_mr_is_memory() rather than checking for a RAMBlock with
offset 0.
All Xen machines create xen_memory first so this has no
functional change for existing machines.
Signed-off-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
Add a second mapcache for grant mappings. The mapcache for
grants needs to work with XC_PAGE_SIZE granularity since
we can't map larger ranges than what has been granted to us.
Like with foreign mappings (xen_memory), machines using grants
are expected to initialize
From: "Edgar E. Iglesias"
Make MCACHE_BUCKET_SHIFT runtime configurable per cache instance.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
---
hw/xen/xen-mapcache.c | 54 ++-
1 file changed, 33 insertions(+), 21 deletions(-)
diff
From: "Edgar E. Iglesias"
Hi,
Grant mappings are a mechanism in Xen for guests to grant each other
permissions to map and share pages. These grants can be temporary
so both map and unmaps must be respected. See here for more info:
From: "Edgar E. Iglesias"
Pass the ram_addr offset to xen_map_cache.
This is in preparation for adding grant mappings that need
to compute the address within the RAMBlock.
No functional changes.
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 16 +++-
From: "Edgar E. Iglesias"
Always pass address with offset to xen_map_cache().
This is in preparation for support for grant mappings.
Since this is within a block that checks for offset == 0,
this has no functional changes.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
---
From: "Edgar E. Iglesias"
When invalidating memory ranges, if we happen to hit the first
entry in a bucket we were never unmapping it. This was harmless
for foreign mappings but now that we're looking to reuse the
mapcache for transient grant mappings, we must unmap entries
when invalidated.
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
---
hw/arm/xen_arm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
index 15fa7dfa84..6fad829ede 100644
--- a/hw/arm/xen_arm.c
+++ b/hw/arm/xen_arm.c
@@
From: "Edgar E. Iglesias"
Add xen_mr_is_memory() to abstract away tests for the
xen_memory MR.
No functional changes.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
Acked-by: David Hildenbrand
---
hw/xen/xen-hvm-common.c | 10 --
include/sysemu/xen.h| 8
Hi Eric,
On Wed, May 15, 2024 at 03:54:36PM +0200, Eric Auger wrote:
>
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > In the previous patch, comine_tlb() was added which combines 2 TLB
> combine
Will do.
> > entries into one, which chooses the granule and level from the
> > smallest entry.
> >
Looks good here, thanks.
On Thu, May 16, 2024, 2:40 a.m. wrote:
> From: Marc-André Lureau
>
> Hi,
>
> The aforementioned patch breaks virtio-gpu device migrations for versions
> pre-9.0/9.0, both forwards and backwards. Versioning of `VMS_STRUCT` is
> more
> complex than it may initially
Hi Eric,
On Wed, May 15, 2024 at 03:48:05PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > This patch adds support for nested(combined) TLB entries.
> space between nested and (.
Will do.
> > The main function combine_tlb() is not used here but in the next
On Thu, May 16, 2024, 5:34 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Add a semantic tag to paragraphs that appear *before* tagged
> > sections/members/features and those that appear after. This will control
> > how they are inlined when doc sections are merged and flattened.
>
>
On Thu, May 16, 2024 at 02:33:47PM +, Srivatsa Vaddagiri wrote:
> This adds support to launch hypervisor-assisted confidential guests,
> where guest's memory is protected from a potentially untrusted host.
> Hypervisor can setup host's page-tables so that it loses access to guest
> memory.
>
On 5/16/24 14:46, Cédric Le Goater wrote:
Let the callers do the error reporting. Add documentation while at it.
Reviewed-by: Eric Auger
Reviewed-by: Avihai Horon
Signed-off-by: Cédric Le Goater
---
Changes in v7:
- Fixed even more line wrapping of *dirty_bitmap() routines (Avihai)
Hi Salil,
On 5/16/24 19:05, Salil Mehta wrote:
From: Harsh Prateek Bora
Sent: Thursday, May 16, 2024 2:07 PM
Hi Salil,
On 5/16/24 17:42, Salil Mehta wrote:
> Hi Harsh,
>
>> From: Harsh Prateek Bora
>> Sent: Thursday, May 16, 2024 11:15 AM
>>
>> Hi Salil,
Hi Eric,
On Wed, May 15, 2024 at 02:27:45PM +0200, Eric Auger wrote:
> Hi Mostafa,
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> > class of events faults as:
> >
> > CLASS: The class of the operation that caused the fault:
> > -
On Thu, May 16, 2024, 2:18 AM Markus Armbruster wrote:
> John Snow writes:
>
> > When iterating all_sections, this is helpful to be able to distinguish
> > "members" from "features"; the only other way to do so is to
> > cross-reference these sections against QAPIDoc.args or QAPIDoc.features,
>
Hi Eric,
On Mon, May 13, 2024 at 01:47:44PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > For the following events (ARM IHI 0070 F.b - 7.3 Event records):
> > - F_TRANSLATION
> > - F_ACCESS
> > - F_PERMISSION
> > - F_ADDR_SIZE
> >
> > If fault occurs at
On Thu, May 09, 2024 at 07:00 PM +0200, Paolo Bonzini
wrote:
> Instead of mucking with css_migration_enabled(), add a property specific to
> the FLIC device, similar to what is done for TYPE_S390_STATTRIB.
>
> Signed-off-by: Paolo Bonzini
> ---
> include/hw/s390x/s390_flic.h | 1 +
>
Gunyah UAPI header file is provided for ease of use, until Gunyah kernel
driver is merged upstream. scripts/update-linux-headers.sh will be
updated via a separate patch after that for Qemu to pick up gunyah.h
UAPI header from Linux kernel sources.
This header file is based on the Gunyah driver
IRQFD function allows registering of an @eventfd and @irq. @irq will be
injected inside guest when @eventfd is written into.
IOEVENTFD function allows registering an @eventfd and a guest physical
address, @addr, along with optional data. A poll() on @eventfd will be
woken up when guest attempts
Add gunyah.rst that provide some informaiton on how to build and test
'gunyah' accelerator with open-source Gunyah hypervisor.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS| 1 +
docs/system/arm/gunyah.rst | 326 +
2 files changed, 327
Gunyah hypervisor supports emulation of a GICv3 compatible interrupt
controller. Emulation is handled by hypervisor itself, with Qemu being
allowed to specify some of the properties such as IO address at which
GICv3 should be mapped in guest address space. These properties are
conveyed to
These are some work-arounds required temporarily until some limitations
with Gunyah hypervisor are addressed.
Signed-off-by: Srivatsa Vaddagiri
---
include/sysemu/gunyah_int.h | 1 +
accel/gunyah/gunyah-all.c | 18 ++
hw/arm/boot.c | 17 -
* Srivatsa Vaddagiri [2024-05-16 14:33:08]:
> Appreciate any quick comments you have. This is v2 that I intend to publish on
> qemu lists. Main changes since v1 is adding support for protected VM.
Pls ignore this !
Complete the cpu execution loop. At this time, we recognize exits
associated with only MMIO access. Future patches will add support for
recognizing other exit reasons, such as PSCI calls made by guest.
Signed-off-by: Srivatsa Vaddagiri
---
include/sysemu/gunyah_int.h | 9 ++
Specify the location of device-tree and its size, as Gunyah requires the
device-tree to be parsed before VM can begin its execution.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS | 1 +
include/sysemu/gunyah.h | 2 ++
accel/stubs/gunyah-stub.c | 5 +
hw/arm/virt.c
Customize device-tree with Gunyah specific properties. Some of these
properties include specification of doorbells that need to be created
and associated with various interrupts.
Signed-off-by: Srivatsa Vaddagiri
---
include/sysemu/gunyah.h | 2 +
accel/stubs/gunyah-stub.c | 5 +++
Add a new accelerator, gunyah, with basic functionality of creating a
VM. Subsequent patches will add support for other functions required to
run a VM.
Signed-off-by: Srivatsa Vaddagiri
---
MAINTAINERS | 7 ++
docs/about/build-platforms.rst | 2 +-
meson.build
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