s disabled and debug property enabled as
usual.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab631500ac..4231f36c1b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -17
.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 5 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/debug.c | 30 +-
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c160b9216b..ab631500ac
Check if each element of array of pointers for itimer contains a non-null
pointer before freeing.
Signed-off-by: Himanshu Chauhan
---
target/riscv/debug.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e30d99cc2f
Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
all debug || ext_sdtrig references. All decisions are based on
debug flag alone
- Added null check before itimers are deleted. Without this check a
crash is observed.
Himanshu Chauhan (4):
target/riscv: Check for valid itimer pointer before free
target/riscv: Enable mcontrol6 triggers
Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 4 +-
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 2 +-
target/riscv/debug.c | 90 +-
4 files changed, 57 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target
a superset of debug specification, disable
the debug property when sdtrig is enabled. A warning is printed when this is
done.
By default, the sdtrig extension is disabled and debug property enabled as
usual.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 7 +++
1 file changed, 7
n
CPUs.
Changes from v4:
- Enable debug flag if sdtrig was enabled but debug was disabled.
- Other cosmetic changes.
Changes from v5:
- Addressed comments from Andrew Jones
Himanshu Chauhan (3):
target/riscv: Enable mcontrol6 triggers only when sdtrig is selected
target/riscv: Expose
.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 4 +-
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 2 +-
target/riscv/debug.c | 90 +-
target/riscv/machine.c | 2 +-
5 files changed, 58 insertions(+), 41 deletions(-)
diff --git
Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
a superset of debug specification, disable
the debug property when sdtrig is enabled. A warning is printed when this is
done.
By default, the sdtrig extension is disabled and debug property enabled as
usual.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 6 ++
1 file changed, 6
n
CPUs.
Changes from v4:
- Enable debug flag if sdtrig was enabled but debug was disabled.
- Other cosmetic changes.
Himanshu Chauhan (3):
target/riscv: Enable mcontrol6 triggers only when sdtrig is selected
target/riscv: Expose sdtrig ISA extension
target/riscv: Enable sdtrig for Ventan
> On 13-Mar-2024, at 6:19 PM, Andrew Jones wrote:
>
> On Wed, Mar 13, 2024 at 05:48:16PM +0530, Himanshu Chauhan wrote:
> ...
>>>>>> #ifndef CONFIG_USER_ONLY
>>>>>> +if (cpu->cfg.debug && cpu->cfg.ext_sdtrig) {
>>&
> On 13-Mar-2024, at 4:28 PM, Andrew Jones wrote:
>
> On Wed, Mar 13, 2024 at 03:50:16PM +0530, Himanshu Chauhan wrote:
>> On Wed, Mar 13, 2024 at 3:24 PM Andrew Jones
>> wrote:
>>
>>> On Wed, Mar 13, 2024 at 11:39:30AM +0530, Himanshu Chauhan wrote:
>
On Wed, Mar 13, 2024 at 3:24 PM Andrew Jones
wrote:
> On Wed, Mar 13, 2024 at 11:39:30AM +0530, Himanshu Chauhan wrote:
> > This patch adds "sdtrig" in the ISA string when sdtrig extension is
> enabled.
> > The sdtrig extension may or may not be implemen
Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
n
CPUs.
Himanshu Chauhan (3):
target/riscv: Enable mcontrol6 triggers only when sdtrig is selected
target/riscv: Expose sdtrig ISA extension
target/riscv: Enable sdtrig for Ventana's Veyron CPUs
target/riscv/cpu.c | 14 ++-
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 2
.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 4 +-
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 2 +-
target/riscv/debug.c | 92 +-
target/riscv/machine.c | 2 +-
5 files changed, 60 insertions(+), 41 deletions(-)
diff --git
a superset of debug specification, disable
the debug property when sdtrig is enabled. A warning is printed when this is
done.
By default, the sdtrig extension is disabled and debug property enabled as
usual.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 8
1 file changed, 8
property and replaces with ext_sdtrig.
A deprecation warning is displayed if debug property is used.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c| 37 ++---
target/riscv/cpu_cfg.h| 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c
Mark debug property as deprecated and replace internally with sdtrig
extension
- setting/unsetting debug property shows warning and sets/unsets ext_sdtrig
- sdtrig is added to ISA string as RISC-V debug specification is frozen
Himanshu Chauhan (2):
target/riscv: Mark debug property as deprecate
This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
The sdtrig extension may or may not be implemented in a system. Therefore, the
-cpu rv64,sdtrig=
option can be used to dynamically turn sdtrig extension on or off.
Signed-off-by: Himanshu Chauhan
-
> On 17-Jan-2024, at 10:29 PM, Daniel Henrique Barboza
> wrote:
>
>
>
> On 1/12/24 10:34, Rob Bradford wrote:
>> On Fri, 2024-01-12 at 13:52 +1000, Alistair Francis wrote:
>>> On Thu, Jan 11, 2024 at 5:20 AM Daniel Henrique Barboza
>>> wrote:
Himanshu,
We spoke
ted to ISA string when it is enabled.
Like so:
rv64imafdch_zicbom_*_x-sdtrig_*_sstc_svadu
Changes from v1:
- Replaced the debug property with ext_sdtrig
- Marked it experimenatal by naming it x-sdtrig
- x-sdtrig is added to ISA string
- Reversed the patch order
Himanshu Chauhan (2):
ta
This patch adds "x-sdtrig" in the ISA string when sdtrig extension is enabled.
The sdtrig extension may or may not be implemented in a system. Therefore, the
-cpu rv64,x-sdtrig=
option can be used to dynamically turn sdtrig extension on or off.
Signed-off-by: Himans
are accessed.
This patch removes the "debug" property and replaces it with ext_sdtrig
extension.
It also raises an illegal instruction exception when the extension is disabled
and
its CSRs are accessed.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c| 7 +++
target/riscv
When sdtrig is turned off by "sdtrig=false" option, raise
and illegal instruction exception on any read/write to
sdtrig CSRs.
Signed-off-by: Himanshu Chauhan
---
target/riscv/csr.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/csr.c b/target/r
This patch makes the debug trigger (sdtrig) capability
as an extension and exports it as an ISA string. The sdtrig
extension may or may not be implemented in a system. The
-cpu rv64,sdtrig=
option can be used to dynamicaly turn sdtrig extension
on or off.
Signed-off-by: Himanshu Chauhan
ted to ISA string when it is enabled.
Like so:
rv64imafdch_zicbom_*_sdtrig_*_sstc_svadu
Himanshu Chauhan (2):
target/riscv: Export sdtrig as an extension and ISA string
target/riscv: Raise an exception when sdtrig is turned off
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
ta
> On 19-Sep-2023, at 10:51 AM, Alistair Francis wrote:
>
> On Tue, Sep 19, 2023 at 3:08 PM Chang Alvin wrote:
>>
>>> -Original Message-
>>
>>> From: Alistair Francis
>>
>>> Sent: Tuesday, September 19, 2023 12:42 PM
>>
>>> To: Alvin Che-Chia Chang(張哲嘉)
>>
>>> Cc:
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan
---
target/riscv/cpu.c | 9 +
target/riscv/cpu_cfg.h | 2 +-
target/riscv/csr.c | 6
pmp_hart_has_privs_default at the end of the loop
Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when
address matches")
Signed-off-by: Himanshu Chauhan
---
target/riscv/pmp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/ris
Skip applying default rules when
address matches")
Signed-off-by: Himanshu Chauhan
---
target/riscv/pmp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 418738afd8..976b199156 100644
--- a/target/riscv/pmp.c
+++ b/ta
On an address match, skip checking for default permissions and return error
based on access defined in PMP configuration.
Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when
address matches")
Signed-off-by: Himanshu Chauhan
---
target/riscv/pmp.c | 5 +++
On 28/02/23 21:23, Daniel Henrique Barboza wrote:
Hey. Sorry for the delay, this patch went through the cracks :(
(CCing the reviewers)
(CCing qemu-devel as well)
On 2/3/23 01:24, Himanshu Chauhan wrote:
Smepmp is a ratified extension. This patch converts the existing epmp
support
On 13/02/23 09:52, LIU Zhiwei wrote:
On 2023/2/9 13:52, Himanshu Chauhan wrote:
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when
range
is found. It returns the index of the match PMP entry.
fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb)
Signed-off-by: Himanshu Chauhan
---
target/riscv/pmp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
I am not very sure about the place(s) we would need this. But I think
this is required. Please advise.
When having SVM enabled, the do_interrupt64 shouldn't be
called unless GIF is set otherwise this causes random behaviour
especially bad TR in case guest is running.
Signed-off-by: Himanshu
Hi,
I just cloned qemu-kvm, built and installed it. But the qemu-img fails
to create any disk image above 1G. The problem as I see is use of
ssize_t for image size. When size is 2G, the check if (sval 0)
succeeds and I get the error:
qemu-img: Invalid image size specified! You may use k, M, G
Everywhere else vect_addr[16] is returned on a read of default vector address
but updation is done only on default_addr in structure.
Signed-off-by: Himanshu Chauhan hschau...@nulltrace.org
---
hw/pl190.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pl190.c b/hw
Everywhere else vect_addr[16] is returned on a read of default vector address
but updation is done only on default_addr in structure.
Signed-off-by: Himanshu Chauhan hschau...@nulltrace.org
---
hw/pl190.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pl190.c b/hw
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