the
other
decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with
minimal
overhead for users that don't need this particular vendor decoder.
Signed-off-by: Huang Tao
Suggested-by: Christoph Muellner
Co-authored-by: LIU Zhiwei
On 2024/4/29 15:58, Huang Tao wrote:
On 2024/4/29 11:51, Alistair Francis wrote:
On Thu, Mar 14, 2024 at 7:23 PM Huang Tao
wrote:
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according
On 2024/4/29 11:51, Alistair Francis wrote:
On Thu, Mar 14, 2024 at 7:23 PM Huang Tao wrote:
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several
This patch enables XTheadVector for the c906.
Signed-off-by: Huang Tao
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 05652e8c87..e85aa51237 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
The instruction has the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 5 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 9 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 85 ++-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 17 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 25 +++-
target/riscv
sed. XTheadVector always use the
least-significant bits.
2. different tail elements process policy.
Signed-off-by: Huang Tao
---
.../riscv/insn_trans/trans_xtheadvector.c.inc | 59 ++-
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_tr
register, while vmv.x.s can only transfer the first element in a vector
register to a general register.
2. When SEW < XLEN, XTheadVector zero-extend the value, while RVV1.0
sign-extend the value.
3. different tail element process policy.
Signed-off-by: Huang Tao
---
.../riscv/insn_tr
The instruction has the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 5
.../riscv/insn_trans/trans_xtheadvector.c.inc | 27 ++-
target/riscv
The instruction has the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 5
.../riscv/insn_trans/trans_xtheadvector.c.inc | 29 +-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 4 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ++-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 2 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 2 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 31 ++-
target/riscv
[mlen], while RVV1.0 locates it in bit[i].
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 9
.../riscv/insn_trans/trans_xtheadvector.c.inc | 44 +++
target/riscv/xtheadvector_helper.c| 42 ++
3 files changed, 87
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h| 3 +++
target/riscv/insn_trans/trans_xtheadvector.c.inc | 4 +++-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 10
.../riscv/insn_trans/trans_xtheadvector.c.inc | 8 +--
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h| 7 +++
target/riscv/insn_trans/trans_xtheadvector.c.inc | 6 --
target/riscv
fractional lmul, so we can
use simpler check function.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33
.../riscv/insn_trans/trans_xtheadvector.c.inc | 27 +--
target/riscv/xtheadvector_helper.c| 76 +++
3 files changed, 128
Compared to RVV1.0, XTheadVector lacks .rtz and .rod instructions, which
specify the
rounding mode.
Except of lack of similar instructions, the instructions have the same function
as RVV1.0. Overall there are only general differences between XTheadVector and
RVV1.0.
Signed-off-by: Huang Tao
-by: Huang Tao
---
target/riscv/helper.h | 13 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 93 ++-
target/riscv/vector_helper.c | 5 +-
target/riscv/vector_internals.h | 3 +
target/riscv/xtheadvector_helper.c| 44
-by: Huang Tao
---
target/riscv/helper.h | 13
.../riscv/insn_trans/trans_xtheadvector.c.inc | 10 +++---
target/riscv/xtheadvector_helper.c| 33 +++
3 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 8 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 51 +++-
target/riscv
There is no similar instruction in RVV1.0 as th.vmford in XTheadVector.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 37 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 49 +++---
target/riscv/vector_helper.c | 18 ++--
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 19 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 14 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 13 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 10 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 4 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 46 ++-
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 17 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 +
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 49 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 34 ++---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h| 5 +
target/riscv/insn_trans/trans_xtheadvector.c.inc | 6 --
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 16 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 12 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 17 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 162 +-
target
. Different check policy. XTheadVector does not have fractional lmul, so we can
use simpler check function.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 16 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 113 +-
target/riscv/vector_helper.c
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 13 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 14 +
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 17 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 14 ---
target/riscv
There are no instructions similar to these instructions in RVV1.0. So we
implement them by writing their own functions instead of copying code from
RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 22 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 16
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 9 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 6 --
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 17 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 12 ---
target/riscv
In this patch, we add single-width saturating add and sub instructions to
show the way we implement XTheadVector fixed-point arithmetic instructions.
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang
off-by: Huang Tao
---
target/riscv/helper.h | 17 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 124 +-
target/riscv/xtheadvector_helper.c| 104 +++
3 files changed, 239 insertions(+), 6 deletions(-)
diff --git a/target/ri
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 22 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 16 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++--
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 19 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 14 ---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 +++--
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 57
.../riscv/insn_trans/trans_xtheadvector.c.inc | 69 +++---
target/riscv
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 13 +++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 99 +--
target
The difference between XTheadVector and RVV1.0 is same as the other patchs:
1. Different mask reg layout.
2. Different tail/masked elements process policy.
3. Simpler acceleration judgment logic.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 25
.../riscv
Add bitwise logical instructions by resuing macros define before,
Therefore, the difference depending on the macros which commited
in other patchs.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 25 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 20
not have this kind of situation.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 33
.../riscv/insn_trans/trans_xtheadvector.c.inc | 139 +-
target/riscv/xtheadvector_helper.c| 173 ++
3 files changed, 335 insertions(+), 10
as the single-
width operation patch mentions.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 49 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 197 --
target/riscv/vector_helper.c | 15 --
target/riscv/vector_internals.h
, keeping value or overwrite it
with 1s.
3. Different check policy. XTheadVector does not have fractional lmul, so
we can use simpler check function.
4. XTheadVector simplifies the judgment logic of whether to accelerate or
not for its lack of fractional LMUL and vta.
Signed-off-by: Huang Tao
In this patch, we add the vector amo instructions(Zvamo) for XTheadVector.
Zvamo is unsupported by RVV1.0.
The action of Zvamo is similar to Zaamo(atomic operations from the standard
A extension).
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 28
.../riscv
-stride load instructions,
as unit-stride fault-only-first instructions are the he special cases of
unit-stride load operations.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 22
.../riscv/insn_trans/trans_xtheadvector.c.inc | 57 +++--
target/riscv
process policy.
4. Different check policy.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 13 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 49 +--
target/riscv/xtheadvector_helper.c| 24 +
3 files changed, 82 insertions
up of a
different element width. While XTheadVector not.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 22 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 91 +--
target/riscv/vector_helper.c | 4 +-
target/risc
instruction, as
unit-stride is the special case of strided operations.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 26
.../riscv/insn_trans/trans_xtheadvector.c.inc | 59 +--
target/riscv/xtheadvector_helper.c| 31 ++
3
instruction, as
unit-stride is the special case of strided operations.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 44 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 84 --
target/riscv/xtheadvector_helper.c| 86
does not have fractional lmul and emul,
so we can use simpler check function.
Signed-off-by: Huang Tao
---
target/riscv/helper.h | 13 +
.../riscv/insn_trans/trans_xtheadvector.c.inc | 56 +--
target/riscv/xtheadvector_helper.c| 50
policy. XTheadVector keep the
masked element value and clear the tail elements. While RVV1.0 has vta
and vma to set the processing policy, keeping value or overwrite it with
1s.
4. Different check policy. XTheadVector does not have fractional lmul, so we
can use simpler check function
vl.
2. XTheadVector has different vtype encoding from RVV1.0.
Signed-off-by: Huang Tao
---
.../riscv/insn_trans/trans_xtheadvector.c.inc | 93 ++-
1 file changed, 91 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv
. There is no performance impact on standard decoding
because the decode_xtheadvector will not be added to decode function array
when ext_xtheadvector is false.
Signed-off-by: Huang Tao
---
.../riscv/insn_trans/trans_xtheadvector.c.inc | 384 +
target/riscv/meson.build
in DisasContext to indicate the mask bit and reduce the
calculation of mlen.
Signed-off-by: Huang Tao
---
target/riscv/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7eb8c9cd31..a22fdb59df 100644
--- a/target/riscv/translate.c
and the RISC-V standard.
Signed-off-by: Huang Tao
---
target/riscv/cpu.h | 36 +
target/riscv/cpu_bits.h | 18 +
target/riscv/csr.c | 42 +-
target/riscv/th_csr.c | 169 +++-
4 files changed, 243 insertions(+), 22 deletions
Add ext_xtheadvector properties.
In this patch, we add ext_xtheadvector in RISCVCPUConfig
for XTheadVector as a start. In rv64_thead_c906_cpu_init,
we make ext_xtheadvector equals false to avoid affecting
other extensions when it is not fully implemented.
Signed-off-by: Huang Tao
---
target
user-mode and system-mode vendor csrs.
Signed-off-by: Huang Tao
---
target/riscv/cpu.c | 2 +-
target/riscv/meson.build | 2 +-
target/riscv/th_csr.c| 21 +
3 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Christoph Müllner
The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
https://github.com/T-head-Semi/thead-extension-spec/pull/46
An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating
XTheadVector csrs.
Christoph Müllner (1):
riscv: thead: Add th.sxstatus CSR emulation
Huang Tao (64):
target/riscv: Reuse th_csr.c to add user-mode csrs
target/riscv: Add properties for XTheadVector extension
target/riscv: Override some csr ops for XTheadVector
target/riscv: Add mlen
This is a ping to the patch below.
https://patchew.org/QEMU/20240325021654.6594-1-eric.hu...@linux.alibaba.com/
On 2024/3/25 10:16, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set
This is a ping to the patch below.
https://patchew.org/QEMU/20240314092158.65866-1-eric.hu...@linux.alibaba.com/
On 2024/3/14 17:21, Huang Tao wrote:
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
.
Signed-off-by: Huang Tao
Suggested-by: Richard Henderson
Reviewed-by: LIU Zhiwei
---
Changes in v3:
- use "if (HOST_BIG_ENDIAN)" instead of "#if HOST_BIG_ENDIAN"
Changes in v2:
- Keep the api of vext_set_elems_1s
- Reduce the number of patches.
---
target/riscv/vec
On 2024/3/21 16:18, Richard Henderson wrote:
On 3/20/24 17:58, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set
to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the
element
agnostic policy.
However, this function can't deal
.
Signed-off-by: Huang Tao
Suggested-by: Richard Henderson
---
Changes in v2:
- Keep the api of vext_set_elems_1s
- Reduce the number of patches.
---
target/riscv/vector_internals.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/riscv/vector_internals.c b/target
I will rewrite the patch, and send a new version soon.
Thanks,
Huang Tao
On 2024/3/20 07:32, Richard Henderson wrote:
On 3/19/24 11:57, Daniel Henrique Barboza wrote:
This seems correct but a bit over complicated at first glance. I
wonder if we have
something simpler already done somewhere
the
other
decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with
minimal
overhead for users that don't need this particular vendor decoder.
Signed-off-by: Huang Tao
Suggested-by: Christoph Muellner
Co-authored-by: LIU Zhiwei
referencing env fields at
translation-time, when you really needed to generate tcg code to
reference the fields at runtime.
It also applies to the ArchCPU case.
Thanks to your review, I will adopt the other suggestions in the next
version.
Thanks,
Huang Tao
the
other
decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with
minimal
overhead for users that don't need this particular vendor deocder.
Signed-off-by: Huang Tao
Suggested-by: Christoph Muellner
Co-authored-by: LIU Zhiwei
I'm sorry for making this mistake and thank you for your patience.
In the next version, I will use GPtrArray you mentioned earlier to solve
the problem.
Thanks,
Huang Tao
On 2024/3/12 21:57, Richard Henderson wrote:
On 3/11/24 19:45, Huang Tao wrote:
+static void
the
other
decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with
minimal
overhead for users that don't need this particular vendor deocder.
Signed-off-by: Huang Tao
Suggested-by: Christoph Muellner
Co-authored-by: LIU Zhiwei
, as more and more
vendors join in, this approach will have scalability issues.
For example, if you add 10 vendors, it is not fair to treat the 10th
vendor with the lowest performance. Our approach works for most
scenarios, which are basic RV extensions + vendor-specific extensions.
Thanks,
Huang
Replace vext_set_elems_1s_le with vext_set_elems_1s for RVV and
vcrypto.
Signed-off-by: Huang Tao
---
target/riscv/vcrypto_helper.c | 32 ++--
target/riscv/vector_helper.c| 92 -
target/riscv/vector_internals.c | 8 +--
target/riscv
In RVV and vcrypto instructions, the element agnostic function vext_set_elems_1s
can't deal with the big endian host environment.
This patchset fixes the problem by implementing the right function to set
agnostic
elements.
Huang Tao (4):
target/riscv: Rename vext_set_elems_1s function
target
We add vext_set_elems_1s to set agnostic elements to 1s in both big
and little endian situation.
In the function vext_set_elems_1s. We using esz argument to get the first
element to set. 'cnt' is just idx * esz.
Signed-off-by: Huang Tao
---
target/riscv/vector_internals.c | 53
the
other
decoder guard functions when decoding.
Signed-off-by: Huang Tao
Suggested-by: Christoph Muellner
Co-authored-by: LIU Zhiwei
---
target/riscv/cpu.c | 20
target/riscv/cpu.h | 2 ++
target/riscv/cpu_decoder.h | 34
Delete vext_set_elems_1s_le.
Signed-off-by: Huang Tao
---
target/riscv/vector_internals.c | 13 -
target/riscv/vector_internals.h | 2 --
2 files changed, 15 deletions(-)
diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index 0166e81e02..4f24bd8516
, to indicate that it only
suits little endian situation.
Signed-off-by: Huang Tao
---
target/riscv/vcrypto_helper.c | 32 ++--
target/riscv/vector_helper.c| 92 -
target/riscv/vector_internals.c | 10 ++--
target/riscv/vector_internals.h | 6 +--
4 files
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