Hi Daniel,
I want to know if we can use the IOMMU and IOPMP at the same time.
The relationship between them is more similar to MMU and sPMP or to MMU
and PMP?
Thanks,
Zhiwei
On 2024/5/24 1:39, Daniel Henrique Barboza wrote:
Hi,
In this new version a lot of changes were made throughout all
Hi Alexandre,
I have sent the patch set about Zabha before last week.
https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
Welcome to review it and give comments.
Thanks,
Zhiwei
On 2024/5/28 13:45, Alexandre Ghiti wrote:
From: Gianluca Guida
Add Zabha
On 2024/5/27 1:16, Daniel Henrique Barboza wrote:
On 5/25/24 21:37, LIU Zhiwei wrote:
On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
Hi Zhiwei!
On 5/23/24 09:40, LIU Zhiwei wrote:
Zabha adds support AMO operations for byte and half word. If zacas
has been implemented,
zabha also
On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
Hi Zhiwei!
On 5/23/24 09:40, LIU Zhiwei wrote:
Zabha adds support AMO operations for byte and half word. If zacas
has been implemented,
zabha also adds support amocas.b and amocas.h.
More details is on the specification here:
https
Hi Daniel,
On 2024/5/24 17:46, Daniel Henrique Barboza wrote:
On 5/22/24 03:29, LIU Zhiwei wrote:
Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
Signed-off-by: LIU Zhiwei
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 41050246f3..849af82ddf 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6 +954,26 @@ typedef enum
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 21d4e36405..9ec03a1edc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -118,6 +118,7 @@ const RISCVIsaExtData isa_edata_arr
Signed-off-by: LIU Zhiwei
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8a4801d442..eee48f92d3 100644
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/translate.c| 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
b/target/riscv/insn_trans
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131
target/riscv/translate.c| 4 +-
4 files changed, 155 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rva.c.inc | 21 -
target/riscv/translate.c| 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv
is based on these two patch set:
1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
LIU Zhiwei (6):
target/riscv: Move gen_amo before implement Zabha
target/riscv: Add AMO instructions for Zabha
target
of RVWMO—i.e., it will execute atomically.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn_trans/trans_rva.c.inc | 42 ++---
target/riscv/insn_trans/trans_rvd.c.inc | 14
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei
---
disas
register.
In current implementation, C.MOP.n only has an check function, without any
other more behavior.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn16.decode | 1
Signed-off-by: LIU Zhiwei
---
disas/riscv.c | 100 ++
1 file changed, 100 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index e236c8b5b7..4cd769f165 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -906,6 +906,46 @@ typedef enum
initially are defined to simply write zero to x[rd],
but are designed to be redefined by later extensions to perform some
other action.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode
, which requires the Zca extension, has 8 instructions whose initial
behavior is reading the source register.
The more details on this specifcation is here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
LIU Zhiwei (4):
target/riscv: Add zimop extension
disas/riscv: Support
riv_ver >= PRIV_VERSION_1_13_0) {
+ wr_mask |= SMSTATEEN0_P1P13;
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
return write_mstateenh(env, csrno, wr_mask, new_val);
}
vlenb' instead of shifting 'vlen'") set
beforehand.
Cc: Akihiko Odaki
Cc: Alex Bennée
Reported-by: Robin Dapp
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/gdbst
nable RVG, RVJ and RVV that are disabled by default */
-riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
Reviewed-by: LIU Zhiwei
Zhiwei
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Hi,
It looks like Pointer Masking spec has reached v1.0 and been frozen,
I think one big feature that this patch set missing is lack of pointer
masking about the hypervisor load/store instructions.
Zhiwei
rebasing on
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e350e9bd8..b3b3a6275f 100644
---
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 13 +
2 files changed, 29
On 2024/5/13 20:35, LIU Zhiwei wrote:
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 5
target/riscv/cpu_helper.c | 58 +++
2 files changed
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 5
target/riscv/cpu_helper.c | 58 +++
2 files changed, 63 insertions(+)
diff --git
FLAGS, AXL);
ctx->cs = cs;
+ctx->addr_width = 0;
+ctx->addr_signed = false;
Reviewed-by: LIU Zhiwei
Zhiwei
ctx->ztso = cpu->cfg.ext_ztso;
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
On 2024/5/11 18:10, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 5
target/riscv/cpu_helper.c | 58 +++
2 files changed, 63 insertions(+)
diff --git
+const char *priv_spec_str = priv_spec_to_str(priv_ver);
+
+if (priv_spec_str == NULL) {
+g_assert_not_reached();
}
g_assert(priv_spec_str != NULL) or g_assert(priv_spec_str)
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
-g_assert_not_reached();
+return priv_
On 2024/5/10 14:58, Fea.Wang wrote:
Add RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 4 +++-
target/riscv/cpu_cfg.h | 1 +
target/riscv
On 2024/5/10 14:58, Fea.Wang wrote:
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
SMSTATEEN0 that controls access to the hedeleg.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 10 ++
2 files
d_zero, write_ignore,
+ .min_priv_ver = PRIV_VERSION_1_13_0 },
+[CSR_HEDELEGH]= { "hedelegh", any32, read_hedelegh, write_hedelegh,
Using hmode32 instead of any32.
Otherwise,
Reviewed-by: LIU Zhiwei
+ .min_
*/
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
+RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
Reviewed-by: LIU Zhiwei
Zhiwei
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
extensions[] = {
/* Vector cryptography extensions */
MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
Reviewed-
}
} else {
/* check U/S/M bit against current privilege level */
if ((ctrl >> 3) & BIT(env->priv)) {
+env->badaddr = pc;
return true;
}
}
Reviewed-by: LIU Zhiwei
Zhiwei
arg_ebreak *a)
if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
} else {
+tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+ offsetof(CPURISCVState, badaddr));
Review
i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+int csrno = th_csr_list[i].csrno;
+riscv_csr_operations *csr_ops = _csr_list[i].csr_ops;
+if (!th_csr_list[i].insertion_test(cpu))
+riscv_set_csr_ops(csrno, csr_ops);
+}
+}
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
cks */
+#endif
Reviewed-by: LIU Zhiwei
Zhiwei
memset(base + cnt, -1, tot - cnt);
}
vstart is being cleared in the end of the
execution, regardless of the path taken.
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ---
tar
nt8_t *)vd + H1(j - 1),
+ (uint8_t *)vs2 + H1(j - 1),
+ j - i);
+i = j;
+}
+
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
- maxsz - startb);
+ maxsz - i);
Reviewed-by: LIU Zhiwei
Zhiwei
env->vstart = 0;
}
' brconds, and that will also
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewd-by: LIU Zhiwei
Zhiwei
---
target/riscv/insn_trans/trans_rvv.
cis
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fe56c007d5..ca79571ae2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -478
));
Hi Yu-Ming,
The 128-bit CSR operations have the similar errors. Could you solve the
similar bug in this patch set?
Otherwise,
Reviewed-by: LIU Zhiwei
Thanks,
Zhiwei
On 2024/3/12 2:08, Daniel Henrique Barboza wrote:
The previous patch added an early vstart >= vl exit in all vector
helpers, most of them using the VSTART_CHECK_EARLY_EXIT() macro,
and now we're left with a lot of 'brcond' that has not use. The
pattern goes like this:
On 2024/3/10 4:43, Daniel Henrique Barboza wrote:
Change all code that updates tail elems to use vext_set_tail_elems_1s()
instead of vext_set_elems_1s().
Hi Daniel,
Notice vext_set_tail_elems_1s will use NF field, which is zero for most
vector instructions. Thus it will do nothing.
I think
Hi Daniel and Alistair,
Hope it is not too late. I think there are two bugs in this patch.
1) The first is for instruction vfmv.s.f. vfmv.s.f doesn't use helper
function. If we remove the over check, it will set the first element of
destination vector register, which is against the
: Alistair Francis
Reviewed-by: LIU Zhiwei
Zhiwei
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 67 ++
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4e8ac13b90c..a3d979c4c
On 2024/2/29 2:51, Atish Patra wrote:
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3
On 2024/2/29 2:51, Atish Patra wrote:
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one
/sync_i.adoc
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_xthead.c.inc | 10 --
1 file changed, 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index dbb6411239..22488412d4 100644
--- a/target/riscv/insn_trans
On 2024/1/30 19:43, Christoph Müllner wrote:
On Tue, Jan 30, 2024 at 12:12 PM LIU Zhiwei
wrote:
thead-c906 uses some flags in pte [60-63] bits. It has history reasons that
SVPBMT didn't exist when thead-c906 came to world.
We named this feature as xtheadmaee. this feature is controlled
riscv specification allows custom CSRs in decode area. So we should
register all vendor CSRs in cpu realize stage.
Signed-off-by: LIU Zhiwei
---
1) Use int index to quiet the Werror for "i < 0".
---
target/riscv/cpu.c | 3 +++
target/riscv/tcg/tcg-cpu.c | 18 +
as
xtheadmaee[1]. this feature is controlled by an custom CSR named mxstatus,
whose maee field encodes whether enable the pte [60-63] bits.
[1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
Signed-off-by: LIU Zhiwei
---
v1->v2:
1) Remove mxstatus user mode access
2)
/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
LIU Zhiwei (2):
target/riscv: Register vendors CSR
target/riscv: Support xtheadmaee for thead-c906
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 9 ++
target/riscv/cpu_bits.h| 6
target/riscv
On 2024/1/31 13:07, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+riscv_csr_operations th_csr_ops[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+ [CSR_TH_MXSTATUS] = { "th_mxstatus", th_maee_check,
read_th_mxstatus,
+ write_th_mxstatus
On 2024/1/31 13:06, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+/* This stub just works for making vendors array not empty */
+riscv_csr_operations stub_csr_ops[CSR_TABLE_SIZE];
+static inline bool never_p(const RISCVCPUConfig *cfg)
+{
+ return false;
+}
+
+void
.
The sections "5.2.2.1 Page table structure" and "15.1.7.1 M-mode extension
status register (MXSTATUS)" in document[1] give the detailed information
about its design.
[1]:https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699265191641/XuanTie-Openc906-UserManual.pdf
Signe
riscv specification allows custom CSRs in decode area. So we should
register all vendor CSRs in cpu realize stage.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 3 +++
target/riscv/tcg/tcg-cpu.c | 26 ++
target/riscv/tcg/tcg-cpu.h | 1 +
3 files changed
We first add a framework for vendor CSRs in patch 1. After that we add
one thead-c906 CSR mxstatus, which is used for mmu extension xtheadmaee.
This patch set fix the regression on kernel pointed by Björn Töpel in
https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.
LIU Zhiwei (2
vxrm and vxsat have been moved into a special register vcsr since
RVV v1.0. So remove them from FCSR for vector 1.0.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index
The real return value type has been converted to RISCVException,
but some function declarations still not. This patch makes all
csr operation declarations use RISCVExcetion.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 117 -
1 file changed, 74
On 2024/1/24 20:49, Björn Töpel wrote:
Hi!
I bumped the RISC-V Linux kernel CI to use qemu 8.2.0, and realized that
thead c906 didn't boot anymore. Bisection points to commit d6a427e2c0b2
("target/riscv/cpu.c: restrict 'marchid' value")
Reverting that commit, or the hack below solves the
If CPU does not implement the Vector extension, it usually means
mstatus vs hardwire to zero. So we should not allow write a
non-zero value to this field.
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c
According to the specification, the th.dcache.cvall1 can be executed
under all priviledges.
The specification about xtheadcmo located in,
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans
Hi Irina,
On 2023/12/1 19:53, Irina Ryapolova wrote:
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR
fields are only defined
for a subset of bit encodings, but allow any value to be written while
guaranteeing to return a legal
value whenever read (See
On 2023/11/28 21:04, Mark Cave-Ayland wrote:
On 01/09/2023 07:01, LIU Zhiwei wrote:
When memory region is ram, the lower TARGET_PAGE_BITS is not the
physical section number. Instead, its value is always 0.
Add comment and assert to make it clear.
Signed-off-by: LIU Zhiwei
---
accel/tcg
tcg: Fix the comment for CPUTLBEntryFull")
Signed-off-by: LIU Zhiwei
---
accel/tcg/cputlb.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index db3f93fda9..7a50a21a2e 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1
100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -323,7 +323,7 @@ RISC-V TCG CPUs
M: Palmer Dabbelt
M: Alistair Francis
M: Bin Meng
-R: Weiwei Li
+R: Weiwei Li
R: Daniel Henrique Barboza
R: Liu Zhiwei
L: qemu-ri...@nongnu.org
Reviewed-by: LIU Zhiwei
Zhiwei
misa_ext_mask &= ~bit;
-}
+riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit,
+ misa_cfg->enabled);
Reviewed-by: LIU Zhiwei
Zhiwei
}
}
}
r_set(bit) || !(profile->misa_ext & bit)) {
+continue;
+}
+
+riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
env->misa_ext_mask &= ~bit;
+}
}
}
}
@@ -989,6 +1001,7 @@ static void tcg_cpu_instance_init(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
+misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
Reviewed-by: LIU Zhiw
@@ -880,6 +937,8 @@ static void riscv_cpu_add_user_properties(Object *obj)
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
+riscv_cpu_add_profiles(obj);
+
Acked-by: LIU Zhiwei
Zhiwei
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
qdev_property_add_static(DEVICE(obj), prop);
}
ame);
+ }
Reviewed-by: LIU Zhiwei
Zhiwei
}
static int kvm_riscv_get_regs_core(CPUState *cs)
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
The rva22U64 profile, described in:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles
Contains a set of CPU extensions aimed for 64-bit userspace
applications. Enabling this set to be enabled via a single user
to memory_region_add_subregion().
Reviewed-by: LIU Zhiwei
Zhiwei
Philippe Mathieu-Daudé (6):
hw/ppc/pnv_xscom: Rename pnv_xscom_realize(Error **) ->
pnv_xscom_init()
hw/ppc/pnv_xscom: Move sysbus_mmio_map() call within pnv_xscom_init()
hw/ppc/pnv_xscom: Do not use SysBus API to map local MMIO region
On 2023/10/18 2:53, Akihiko Odaki wrote:
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.h | 3 +-
hw/riscv/boot.c| 2 +-
@ -573,11 +568,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
-riscv_cpu_validate_misa_mxl(cpu, _err);
-if (local_err != NULL) {
-error_propagate(errp, local_err);
-return false;
-}
+riscv_cpu_validate_misa_mxl(cpu);
+CC Richard
On 2023/10/17 11:37, Akihiko Odaki wrote:
On 2023/10/17 11:29, LIU Zhiwei wrote:
On 2023/10/12 13:42, Akihiko Odaki wrote:
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
On 2023/10/17 11:32, Alistair Francis wrote:
On Tue, Oct 17, 2023 at 12:14 PM LIU Zhiwei
wrote:
On 2023/10/16 9:51, Alistair Francis wrote:
On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza
wrote:
On 10/14/23 00:35, Akihiko Odaki wrote:
TARGET_RISCV64 does not have riscv-32bit
On 2023/10/12 13:42, Akihiko Odaki wrote:
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
On 2023/10/16 9:51, Alistair Francis wrote:
On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza
wrote:
On 10/14/23 00:35, Akihiko Odaki wrote:
TARGET_RISCV64 does not have riscv-32bit-cpu.xml so it shouldn't accept
MXL_RV32.
Signed-off-by: Akihiko Odaki
---
Reviewed-by: Daniel
On 2023/10/13 0:06, Richard Henderson wrote:
On 10/11/23 22:59, LIU Zhiwei wrote:
On 2023/10/11 13:31, Philippe Mathieu-Daudé wrote:
On 11/10/23 05:25, LIU Zhiwei wrote:
On 2023/10/11 1:04, Richard Henderson wrote:
On 10/9/23 05:42, LIU Zhiwei wrote:
On 2023/10/9 19:02, Philippe
On 2023/10/12 20:38, Rob Bradford wrote:
On Thu, 2023-10-12 at 17:05 +0800, LIU Zhiwei wrote:
On 2023/10/11 22:45, Rob Bradford wrote:
Using a mask instead of the number of PMU devices supports the
accurate
emulation of platforms that have a discontinuous set of PMU
a password via a file, or encrypted.
+CPU device properties
+'
+
+``pmu-num=x`` on RISC-V CPUs (since 8.2)
+
+
+In order to support more flexible counter configurations this has been
+replaced by a ``pmu-mask`` property
+
+
Acked-by:
On 2023/10/11 22:45, Rob Bradford wrote:
Using a mask instead of the number of PMU devices supports the accurate
emulation of platforms that have a discontinuous set of PMU counters.
Generate a warning if the old property changed from the default but
still go ahead and use it to generate the
We can always use the MAKE_64BIT_MASK instead of MAKE_32BIT_MASK. And
MAKE_32BIT_MASK only used in target/riscv. I am not sure whether this
patch will be accepted.
Acked-by: LIU Zhiwei
Zhiwei
/*
* To keep it simple, any event can be mapped to any programmable counters in
nt_idx);
-void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name);
+void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
Reviewed-by: LIU Zhiwei
Zhiwei
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
+192,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
base_csrno += 0x80;
}
ctr_index = csrno - base_csrno;
-if (!pmu_num || ctr_index >= pmu_num) {
+if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) {
Otherwise,
Reviewed-by:
On 2023/10/11 13:31, Philippe Mathieu-Daudé wrote:
On 11/10/23 05:25, LIU Zhiwei wrote:
On 2023/10/11 1:04, Richard Henderson wrote:
On 10/9/23 05:42, LIU Zhiwei wrote:
On 2023/10/9 19:02, Philippe Mathieu-Daudé wrote:
When CPUArchState* is available (here CPURISCVState*), we
can use
(void *priv);
-int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
+void riscv_pmu_init(RISCVCPU *cpu, Error **errp);
Reviewed-by: LIU Zhiwei
Zhiwei
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
On 2023/10/11 11:21, Philippe Mathieu-Daudé wrote:
Hi Zhiwei,
On 11/10/23 04:51, LIU Zhiwei wrote:
On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
macro to resolve target CPU types.
Hi Philippe,
I don't understand why should
On 2023/10/11 1:04, Richard Henderson wrote:
On 10/9/23 05:42, LIU Zhiwei wrote:
On 2023/10/9 19:02, Philippe Mathieu-Daudé wrote:
When CPUArchState* is available (here CPURISCVState*), we
can use the fast env_archcpu() macro to get ArchCPU* (here
RISCVCPU*). The QOM cast RISCV_CPU() macro
On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
macro to resolve target CPU types.
Hi Philippe,
I don't understand why should we use FOO_CPU_TYPE_NAME macro to resolve
target CPU types? In my opinion, we should pass the
CPU
9cf21c0c..374b813f20 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -31,6 +31,8 @@
#include "qapi/qapi-types-common.h"
#include "cpu-qom.h"
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
Reviewed-by: LIU Zhiwei
Zhiwei
+
#define TCG_GUEST_DEFAULT_MO 0
/*
_RISCV32)
+mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
+#elif defined(TARGET_RISCV64)
+mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
+#else
+#error unsupported target
+#endif
Reviewed-by: LIU Zhiwei
Zhiwei
mc->pci_allow_0_address = true;
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
, fwmaccbf16)
GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
-RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
Reviewed-by: LIU Zhiwei
Zhiwei
GEN_VEXT_VF(vfwmaccbf16_vf, 4)
static uint32_t fwnmacc16(uint16_t a, uint16_t b
On 2023/10/9 20:53, Richard W.M. Jones wrote:
On Mon, Oct 09, 2023 at 08:36:28PM +0800, LIU Zhiwei wrote:
On 2023/10/9 5:50, Richard W.M. Jones wrote:
RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled
this adds about 5% total overhead when emulating RV64 on x86-64 host
. Jones
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: LIU Zhiwei
By the way, does the community has the plan to support heterogeneous
architecture cpus in one soc?
If so, maybe we have to do this qom cast somewhere.
Zhiwei
---
target/riscv/internals.h | 8
1 file changed
oses ~ 5% overhead when
+ * QOM cast debugging is enabled, so use a direct cast instead.
+ */
+RISCVCPU *cpu = (RISCVCPU *)cs;
This function is very hot. Maybe we should cache the tbflags instead of
calculate it here. Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
RISCVExtStatu
On 2023/9/29 20:37, Thomas Huth wrote:
There are a bunch of RISC-V files that are currently not covered
by the "get_maintainers.pl" script. Add them to the right sections
in MAINTAINERS to fix this problem.
Signed-off-by: Thomas Huth
Reviewed-by: LIU Zhiwei
Zhiwei
---
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