[Qemu-devel] [PATCH] hw/mips_cpc: kick a VP when putting it into Run state

While testing mttcg I noticed that VP0 gets stuck in a loop waiting for other VPs to come up (which never actually happens). To fix this kick VPs while they are being powered up by Cluster Power Controller. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/misc/mips_cpc.c |

Re: [Qemu-devel] [PATCH 2/2] target-mips: reimplement SC instruction and use cmpxchg

On Wed, Sep 21, 2016 at 01:16:28PM -0700, Richard Henderson wrote: > On 09/21/2016 01:07 AM, Leon Alrae wrote: > >+tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); > >+tcg_temp_free(addr); > >+tcg_gen_movi_tl(t0, 0); > >+tcg_gen_br(done); &g

[Qemu-devel] [PATCH v3 2/2] target-mips: reimplement SC instruction and use cmpxchg

This patch completely rewrites conditional stores. Now we use cmpxchg and no longer need separate implementations for user and system emulation. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: Richard Henderson <r...@twiddle.net> --- linux-user/main.c

[Qemu-devel] [PATCH v3 1/2] target-mips: compare virtual addresses in LL/SC sequence

uce CP0_LLAddr which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 3 ++- target-mips/machine.c | 7 --- target-mips/op_helper.c | 29 + target-mips/transla

[Qemu-devel] [PATCH v3 0/2] target-mips: rework conditional stores for mttcg

to Richard's comments Leon Alrae (2): target-mips: compare virtual addresses in LL/SC sequence target-mips: reimplement SC instruction and use cmpxchg linux-user/main.c | 58 - target-mips/cpu.h | 7 +-- target-mips/helper.c| 6 +-- target-mips/helper.h

[Qemu-devel] [PULL 4/9] linux-user: Fix TARGET_F_GETOWN definition for Mips

e/uapi/asm/fcntl.h#L44. This patch also fixes some fcntl()-related LTP tests for Qemu user mode for Mips. Signed-off-by: Miodrag Dinic <miodrag.di...@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Laurent Vivier <laur...@vivier.eu>

[Qemu-devel] [PULL 3/9] linux-user: Fix TARGET_SIOCATMARK definition for Mips

o...@imgtec.com> Reviewed-by: Laurent Vivier <laur...@vivier.eu> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Acked-by: Riku Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/syscall_defs.h | 4 1 file changed

[Qemu-devel] [PULL 2/9] target-mips: generate fences

Make use of memory barrier TCG opcode in MIPS front end. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: Richard Henderson <r...@twiddle.net> --- target-mips/translate.c | 32 ++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --

[Qemu-devel] [PULL 9/9] linux-user: Add missing Mips syscalls items in strace.list

gt; Reviewed-by: Laurent Vivier <laur...@vivier.eu> Acked-by: Riku Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/strace.list | 114 + 1 file changed, 114 insertions(+) diff --git a/linux

[Qemu-devel] [PULL 7/9] linux-user: Fix certain argument alignment cases for Mips64

<laur...@vivier.eu> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Acked-by: Riku Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/syscall.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/sysc

[Qemu-devel] [PULL 5/9] linux-user: Fix structure target_flock definition for Mips

rkovic <aleksandar.marko...@imgtec.com> Reviewed-by: Laurent Vivier <laur...@vivier.eu> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Acked-by: Riku Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/syscall_defs.h | 6

[Qemu-devel] [PULL 8/9] linux-user: Add missing TARGET_EDQUOT error code for Mips

u Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/mips/target_syscall.h | 2 ++ linux-user/mips64/target_syscall.h | 2 ++ linux-user/syscall.c | 1 + 3 files changed, 5 insertions(+) diff --git a/linux-user/mips/targ

[Qemu-devel] [PULL 6/9] linux-user: Fix structure target_semid64_ds definition for Mips

ivier <laur...@vivier.eu> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Acked-by: Riku Voipio <riku.voi...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/mips/target_structs.h | 16 1 file changed, 16 insertions(+) diff --git

[Qemu-devel] [PULL 1/9] target-mips: add 24KEc CPU definition

From: André Draszik <g...@andred.net> Define a new CPU definition supporting 24KEc cores, similar to the existing 24Kc, but with added support for DSP instructions and MIPS16e (and without FPU). Signed-off-by: André Draszik <g...@andred.net> Signed-off-by: Leon Alrae <leon.a

[Qemu-devel] [PULL 0/9] target-mips queue

linux-user: Fix certain argument alignment cases for Mips64 linux-user: Add missing TARGET_EDQUOT error code for Mips linux-user: Add missing Mips syscalls items in strace.list André Draszik (1): target-mips: add 24KEc CPU definition Leon Alrae (1): target-mips: gen

[Qemu-devel] [PATCH] MAINTAINERS: update target-mips maintainers

Yongbok Kim takes over the target-mips maintenance from me. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- Hi, September is my last month in ImgTec, and therefore soon I won't be able to look after target-mips code. I would like to nominate Yongbok Kim as the new co-maintainer. Y

Re: [Qemu-devel] [PATCH v7 0/7] linux-user: Fix miscellaneous Mips-specific issues

On Wed, Sep 21, 2016 at 07:12:20PM +, Riku Voipio wrote: > On Wed, Sep 21, 2016 at 02:16:54PM +0100, Leon Alrae wrote: > > On Mon, Sep 19, 2016 at 01:44:37PM +0200, Aleksandar Markovic wrote: > > > From: Aleksandar Markovic <aleksandar.marko...@imgtec.com

Re: [Qemu-devel] [PATCH v7 0/7] linux-user: Fix miscellaneous Mips-specific issues

On Mon, Sep 19, 2016 at 01:44:37PM +0200, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > v6->v7: > > - Rebased to the latest code. > - Patch 1/1 expanded to act on alpha and sh4. > - Naming in patch 4/7 synced with kernel naming. > - Change

[Qemu-devel] QEMU dtc submodule

Hi, What's the procedure to update / who can update QEMU's dtc mirror git://git.qemu.org/dtc.git which is used as submodule? There's a patch series relying on the dtc v1.4.2 tag: https://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg01815.html but the dtc mirror is outdated and that tag is

[Qemu-devel] [PATCH 1/2] target-mips: compare virtual addresses in LL/SC sequence

uce CP0_LLAddr which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 3 ++- target-mips/machine.c | 7 --- target-mips/op_helper.c | 29 + target-mips/transla

[Qemu-devel] [PATCH 2/2] target-mips: reimplement SC instruction and use cmpxchg

This patch completely rewrites conditional stores. Now we use cmpxchg and no longer need separate implementations for user and system emulation. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/main.c | 58 -- target-mips/cpu.h

[Qemu-devel] [PATCH 0/2] target-mips: rework conditional stores for mttcg

this is a missing piece in atomic helpers rather than a problem in the code gen. v2: * improved and simplified SC implementation according to Richard's comments Leon Alrae (2): target-mips: compare virtual addresses in LL/SC sequence target-mips: reimplement SC instruction and use cmpxchg linux-user

Re: [Qemu-devel] [PATCH 2/2] target-mips: reimplement SC instruction and use cmpxchg

On Fri, Sep 16, 2016 at 09:48:51AM -0700, Richard Henderson wrote: > On 09/15/2016 01:44 AM, Leon Alrae wrote: > > /* Store conditional */ > >+static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, > >+int size) > > {

Re: [Qemu-devel] [PATCH v5 3/5] linux-user: Fix structure target_flock definition for Mips

On Mon, Sep 12, 2016 at 09:40:02PM +0200, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Structure flock is defined for Mips in a way different from any > other platform. For reference, see Linux kernel source code files: > >

[Qemu-devel] [PATCH 1/2] target-mips: compare virtual addresses in LL/SC sequence

uce CP0_LLAddr which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 3 ++- target-mips/machine.c | 7 --- target-mips/op_helper.c | 29 + target-mips/transla

[Qemu-devel] [PATCH 2/2] target-mips: reimplement SC instruction and use cmpxchg

This patch completely rewrites conditional stores. Now we use cmpxchg and no longer need separate implementations for user and system emulation. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/main.c | 58 - target-mips/cpu.h | 4 --

[Qemu-devel] [PATCH 0/2] target-mips: rework conditional stores for mttcg

this is a missing piece in atomic helpers rather than a problem in the code gen. Leon Alrae (2): target-mips: compare virtual addresses in LL/SC sequence target-mips: reimplement SC instruction and use cmpxchg linux-user/main.c | 58 - target-mips/cpu.h | 7

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

On Mon, Sep 12, 2016 at 09:13:10AM -0700, Richard Henderson wrote: > On 09/12/2016 12:59 AM, Leon Alrae wrote: > >On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote: > >>On 09/09/2016 07:46 AM, Leon Alrae wrote: > >>>Wouldn't it be useful if tcg.h pro

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote: > On 09/09/2016 07:46 AM, Leon Alrae wrote: > >Wouldn't it be useful if tcg.h provided also aliases for _le/_be atomic > >helpers (equivalent to helper_ret_X_mmu) so that in target-* code we wouldn't > &

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

On Sat, Sep 03, 2016 at 09:39:41PM +0100, Richard Henderson wrote: > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -1175,6 +1175,59 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, > target_ulong addr, > # define helper_ret_ldq_cmmu helper_le_ldq_cmmu > #endif > > +uint32_t

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

> +#define GEN_ATOMIC_HELPER(NAME, OP, NEW)\ > +static void * const table_##NAME[16] = {\ > +[MO_8] = gen_helper_atomic_##NAME##b, \ > +[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le,

Re: [Qemu-devel] [PATCH v3 05/34] int128: Add int128_make128

On Sat, Sep 03, 2016 at 09:39:33PM +0100, Richard Henderson wrote: > Allows Int128 to be used more generally, rather than having to > begin with 64-bit inputs and accumulate. > > Signed-off-by: Richard Henderson > --- > include/qemu/int128.h | 20 +++- > 1 file

Re: [Qemu-devel] [PATCH v2] target-mips: generate fences

On Thu, Sep 08, 2016 at 10:04:05AM -0700, Richard Henderson wrote: > > +static void gen_sync(int stype) > > +{ > > +TCGOrder tcg_mo = TCG_BAR_SC; > > + > > +switch (stype) { > > +case 0x4: /* SYNC_WMB */ > > +tcg_mo |= TCG_MO_ST_ST; > > +break; > > +case 0x10: /*

Re: [Qemu-devel] [PATCH v4 2/5] linux-user: Fix TARGET_F_GETOWN definition for Mips

On Mon, Sep 05, 2016 at 04:02:05PM +0200, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > For some reason, Qemu's TARGET_F_GETOWN constant for Mips does not > match the correct value of correspondant F_GETOWN. This patch fixes > this problem. > > For

Re: [Qemu-devel] [PATCH 0/7] MIPS Boston board support

On Thu, Sep 08, 2016 at 11:46:38AM +0100, Paul Burton wrote: > On 08/09/16 09:57, Leon Alrae wrote: > > On Fri, Aug 19, 2016 at 08:40:32PM +0100, Paul Burton wrote: > >> On 19/08/16 20:25, no-re...@patchew.org wrote: > >>> Hi, > >>> > >>>

[Qemu-devel] [PATCH v2] target-mips: generate fences

Make use of memory barrier TCG opcode in MIPS front end. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- v2: * generate weaker barriers according to stype --- target-mips/translate.c | 32 ++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff

Re: [Qemu-devel] [PATCH 0/7] MIPS Boston board support

On Fri, Aug 19, 2016 at 08:40:32PM +0100, Paul Burton wrote: > On 19/08/16 20:25, no-re...@patchew.org wrote: > > Hi, > > > > Your series failed automatic build test. Please find the testing commands > > and > > their output below. If you have docker installed, you can probably > > reproduce it

[Qemu-devel] [PATCH] target-mips: generate fences

Make use of memory barrier TCG opcode in MIPS front end. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- This patch complements the following series: https://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg03283.html --- target-mips/translate.c | 4 ++-- 1 file changed, 2 inse

Re: [Qemu-devel] [PATCH 4/7] target-mips: Provide function to test if a CPU supports an ISA

c.com> > --- > target-mips/cpu.h | 1 + > target-mips/translate.c | 10 ++ > 2 files changed, 11 insertions(+) Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

Re: [Qemu-devel] [PATCH 3/7] hw/mips_gic: Update pin state on mask changes

; 1 file changed, 31 insertions(+), 25 deletions(-) Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

Re: [Qemu-devel] [PATCH 2/7] hw/mips_gictimer: provide API for retrieving frequency

urton <paul.bur...@imgtec.com> > --- > hw/timer/mips_gictimer.c | 5 + > include/hw/timer/mips_gictimer.h | 1 + > 2 files changed, 6 insertions(+) Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

Re: [Qemu-devel] [PATCH 1/7] hw/mips_cmgcr: allow GCR base to be moved

; break; > diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h > index a209d91..31bda6a 100644 > --- a/include/hw/misc/mips_cmgcr.h > +++ b/include/hw/misc/mips_cmgcr.h > @@ -41,6 +41,9 @@ > #define GCR_L2_CONFIG_BYPASS_SHF20 > #define GCR_L2_

[Qemu-devel] [PULL 2/2] target-mips: fix EntryHi.EHINV being cleared on TLB exception

While implementing TLB invalidation feature we forgot to modify part of code responsible for updating EntryHi during TLB exception. Consequently EntryHi.EHINV is unexpectedly cleared on the exception. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/helper.c | 1 +

[Qemu-devel] [PULL 0/2] target-mips queue

:24:02 +0100) MIPS patches 2016-07-29 Changes: * bug fixes ---- Leon Alrae (1): target-mips: fix EntryHi.EHINV being cleared on TLB exception Paul Burton (

[Qemu-devel] [PULL 1/2] hw/mips_malta: Fix YAMON API print routine

previously incorrectly jump & wind up printing a continuous stream of the letter E. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Cc: Aurelien Jarno <aurel...@aurel32.net> Cc: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: Aurelien Jarno <aurel...@aurel32.net> Reviewed

[Qemu-devel] [PATCH] target-mips: fix EntryHi.EHINV being cleared on TLB exception

While implementing TLB invalidation feature we forgot to modify part of code responsible for updating EntryHi during TLB exception. Consequently EntryHi.EHINV is unexpectedly cleared on the exception. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/helper.c |1 + 1

Re: [Qemu-devel] [PATCH] tcg: Merge GETPC and GETRA

gt; target-mips/op_helper.c | 18 +- > translate-all.c | 1 + > 6 files changed, 24 insertions(+), 48 deletions(-) Looks good to me: Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Thanks, Leon

Re: [Qemu-devel] [PATCH] target-mips: add 24KEc CPU definition

On Tue, Jul 26, 2016 at 12:42:45AM +0100, André Draszik wrote: > Define a new CPU definition supporting 24KEc cores, similar to > the existing 24Kc, but with added support for DSP instructions > and MIPS16e (and without FPU). > > Signed-off-by: André Draszik > --- >

Re: [Qemu-devel] [PATCH] hw/mips_malta: Fix YAMON API print routine

t; indicating the configuration mismatch but QEMU would previously > incorrectly jump & wind up printing a continuous stream of the letter E. > > Signed-off-by: Paul Burton <paul.bur...@imgtec.com> > Cc: Aurelien Jarno <aurel...@aurel32.net> > Cc: Leon Alrae <leon

Re: [Qemu-devel] [PATCH 3/7] hw/mips: fix PCI bus initialization

on(+), 1 deletion(-) Acked-by: Leon Alrae <leon.al...@imgtec.com> Tested-by: Leon Alrae <leon.al...@imgtec.com> Thanks, Leon > > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 3f4523d..4811843 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_

[Qemu-devel] [PULL 08/11] target-mips: add ASID mask field and replace magic values

From: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: James Hogan <james.ho...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 2 ++ target-mips/helper.c| 10

[Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits

tec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 2 +- target-mips/helper.c| 4 ++-- target-mips/machine.c | 10 +- target-mips/op_helper.c | 8 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-mips/c

[Qemu-devel] [PULL 11/11] target-mips: enable 10-bit ASIDs in I6400 CPU

Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c43bdb7..39ed5c4 100644 --- a/target-mips/translate_init.c +++ b/targe

[Qemu-devel] [PULL 06/11] hw/mips_cmgcr: implement RESET_BASE register in CM GCR

execution. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/misc/mips_cmgcr.c | 54 +++- include/hw/misc/mips_cmgcr.h | 18 +++ 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_c

[Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer

; Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/timer/Makefile.objs | 1 + hw/timer/mips_gictimer.c | 142 +++ include/hw/timer/mips_gictimer.h | 46 + 3 files changed, 189 insertions(+) create mode 100644 hw/tim

[Qemu-devel] [PULL 02/11] hw/mips: implement Global Interrupt Controller

ok Kim <yongbok@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/intc/Makefile.objs | 1 + hw/intc/mips_gic.c | 460 + include/hw/intc/mips_gic.h | 216 + 3 files changed, 677 insertio

[Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU

Replace hardcoded 0xbfc0 with exception_base which is initialized with this default address so there is no functional change here. However, it is now exposed and consequently it will be possible to modify it from outside of the CPU. Signed-off-by: Leon Alrae <leon.al...@imgtec.

[Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit

From: Paul Burton <paul.bur...@imgtec.com> The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: James Hogan <james.ho...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- tar

[Qemu-devel] [PULL 00/11] target-mips queue

* implement RESET_BASE register in CM GCR ---- Leon Alrae (6): hw/mips/cps: create GIC block inside CPS target-mips: add exception base to MIPS CPU hw/mips_cpc: make VP correctly start from the reset vector hw/mips_cmgc

[Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS

Add GIC to CPS and expose its interrupt pins instead of CPU's. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/mips/cps.c| 25 ++--- hw/mips/mips_malta.c | 4 +--- hw/misc/mips_cmgcr.c | 33 + i

[Qemu-devel] [PULL 07/11] target-mips: replace MIPS64R6-generic with the real I6400 CPU model

MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename it to make it clear which MIPS processor it is supposed to emulate. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/translate_init.c | 20 +--- 1 file changed, 9 insertions(

[Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector

the CPU_INTERRUPT_HALT to halt a VP. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/misc/mips_cpc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index e6a35dd..6d34574 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips

Re: [Qemu-devel] [PULL 03/36] hw/pci: delay bus_master_enable_region initialization

Hi, This commit causes regressions in my MIPS tests. QEMU segfaults when booting Linux on Malta board; this can be easily reproduced with Aurelien's Debian images: wget https://people.debian.org/~aurel32/qemu/mipsel/vmlinux-3.2.0-4-5kc-malta wget

[Qemu-devel] [PATCH 4/4] target-mips: enable 10-bit ASIDs in I6400 CPU

Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c43bdb7..39ed5c4 100644 --- a/target-mips/translate_init.c +++ b/targe

[Qemu-devel] [PATCH 1/4] target-mips: add ASID mask field and replace magic values

From: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: James Hogan <james.ho...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 2 ++ target-mips/helper.c| 10

[Qemu-devel] [PATCH 2/4] target-mips: change ASID type to hold more than 8 bits

tec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/cpu.h | 2 +- target-mips/helper.c| 4 ++-- target-mips/machine.c | 10 +- target-mips/op_helper.c | 8 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-mips/c

[Qemu-devel] [PATCH 0/4] target-mips: add extended ASID support

. This series is based on the patch adding I6400 CPU: https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07604.html Thanks, Leon Leon Alrae (1): target-mips: enable 10-bit ASIDs in I6400 CPU Paul Burton (3): target-mips: add ASID mask field and replace magic values target-mips: change ASID

[Qemu-devel] [PATCH 3/4] target-mips: support CP0.Config4.AE bit

From: Paul Burton <paul.bur...@imgtec.com> The read-only Config4.AE bit set denotes extended 10 bits ASID. Signed-off-by: Paul Burton <paul.bur...@imgtec.com> Signed-off-by: James Hogan <james.ho...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- tar

[Qemu-devel] [PATCH] target-mips: replace MIPS64R6-generic with the real I6400 CPU model

MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename it to make it clear which MIPS processor it is supposed to emulate. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/translate_init.c | 20 +--- 1 file changed, 9 insertions(

[Qemu-devel] [PULL 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit

IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <tho...@codesourcery.com> Signed-off-by: Maciej W. Rozycki <ma...@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Tested-by: Bastian Koppelmann <kbast...@mail

[Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>

lt;aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- target-mips/translate.c | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/target-mips/translate

[Qemu-devel] [PULL 10/10] target-mips: Add FCR31's FS bit definition

From: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Add preprocessor definition of FCR31's FS bit, and update related code for setting this bit. Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Signed-

[Qemu-devel] [PULL 06/10] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA

, FMIN will now correctly detect and propagate NaNs. * FCLASS.D ans FCLASS.S will now correcty detect NaN flavors. Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.

[Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()

cture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: P

[Qemu-devel] [PULL 05/10] linux-user: Update preprocessor constants for Mips-specific e_flags bits

r.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h i

[Qemu-devel] [PULL 08/10] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

milar to the code from this patch. Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> [leon.al...@imgtec.com: * removed a statement from the description which caused slight confusion] Signed-off-by: Leon Alrae <

[Qemu-devel] [PULL 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities

Rozycki <ma...@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- linux-user/main.c| 14 ++ target-mips/cpu.h

[Qemu-devel] [PULL 02/10] softfloat: Clean code format in fpu/softfloat-specialize.h

format-wise, and hopefully easier to debug and maintain. Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- fpu/sof

[Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values

grammers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Reviewed-by: Peter Maydell <peter.mayd...

[Qemu-devel] [PULL 00/10] target-mips queue

Hi, This pull request contains patches from Aleksandar which unlock the IEEE 754-2008 support for MIPS. Thanks, Leon Cc: Peter Maydell Cc: Aurelien Jarno The following changes since commit c7288767523f6510cf557707d3eb5e78e519b90d: Merge

Re: [Qemu-devel] [PATCH v9 00/10] IEEE 754-2008 support for Mips

On Thu, Jun 23, 2016 at 04:46:14PM +0100, Peter Maydell wrote: > On 10 June 2016 at 10:57, Aleksandar Markovic > wrote: > > From: Aleksandar Markovic > > > > This patch series provides number of IEEE 754-2008-related features to > >

Re: [Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

On Fri, Jun 10, 2016 at 09:12:12PM +0100, Maciej W. Rozycki wrote: > On Fri, 10 Jun 2016, Aleksandar Markovic wrote: > > > The changes that make QEMU behavior the same as hardware behavior (in > > relation to CEIL, CVT, FLOOR, ROUND, TRUNC Mips instructions) are > > already contained in this

Re: [Qemu-devel] [PATCH v9 10/10] target-mips: Add FCR31's FS bit definition

rkovic <aleksandar.marko...@imgtec.com> > --- > target-mips/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

Re: [Qemu-devel] [PATCH v9 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit

+- > target-microblaze/op_helper.c | 6 +- > target-mips/cpu.h | 5 + > target-mips/helper.h | 4 +- > target-mips/msa_helper.c | 88 +++ > target-mips/op_helper.c | 17 +- > target-mips/translate.c | 5 +- > target-mips/tra

Re: [Qemu-devel] [PATCH v9 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities

ec.com> > --- > linux-user/main.c| 14 ++ > target-mips/cpu.h| 8 > target-mips/gdbstub.c| 8 +++- > target-mips/op_helper.c | 14 +++--- > target-mips/translate.c | 5 ++--- > target-mips/translate_

[Qemu-devel] [PATCH 3/3] hw/mips_cmgcr: implement RESET_BASE register in CM GCR

execution. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/misc/mips_cmgcr.c | 54 +++- include/hw/misc/mips_cmgcr.h | 18 +++ 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_c

[Qemu-devel] [PATCH 1/3] target-mips: add exception base to MIPS CPU

Replace hardcoded 0xbfc0 with exception_base which is initialized with this default address so there is no functional change here. However, it is now exposed and consequently it will be possible to modify it from outside of the CPU. Signed-off-by: Leon Alrae <leon.al...@imgtec.

[Qemu-devel] [PATCH 2/3] hw/mips_cpc: make VP correctly start from the reset vector

the CPU_INTERRUPT_HALT to halt a VP. Signed-off-by: Leon Alrae <leon.al...@imgtec.com> --- hw/misc/mips_cpc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index e6a35dd..6d34574 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips

[Qemu-devel] [PATCH 0/3] mips: support configurable exception vector base

: https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06223.html Thanks, Leon Leon Alrae (3): target-mips: add exception base to MIPS CPU hw/mips_cpc: make VP correctly start from the reset vector hw/mips_cmgcr: implement RESET_BASE register in CM GCR hw/misc/mips_cmgcr.c

Re: [Qemu-devel] [PATCH v8 9/9] target-mips: Implement FCR31's R/W bitmask and related functionalities

> @@ -110,9 +110,11 @@ struct CPUMIPSFPUContext { > #define FCR0_PRID 8 > #define FCR0_REV 0 > /* fcsr */ > +uint32_t fcr31_rw_bitmask; > uint32_t fcr31; > -#define FCR31_ABS2008 19 > -#define FCR31_NAN2008 18 > +#define FCR31_NAN2008 18 > +#define FCR31_ABS2008 19 Now the

Re: [Qemu-devel] [PATCH v8 6/9] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA

Markovic <aleksandar.marko...@imgtec.com> > --- > target-mips/translate_init.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Leon Alrae <leon.al...@imgtec.com>

Re: [Qemu-devel] [PATCH v8 5/9] linux-user: Update preprocessor constants for Mips-specific e_flags bits

ace fixes of other lines into the same patch: http://wiki.qemu.org/Contribute/SubmitAPatch#Don.27t_include_irrelevant_changes If you drop the adjustment of surrounding code then feel free to add: Reviewed-by: Leon Alrae <leon.al...@imgtec.com> Thanks, Leon > > Signe

Re: [Qemu-devel] [PATCH v6 6/9] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning

> diff --git a/target-mips/translate.c b/target-mips/translate.c > index e934884..2cdd2bd 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env) > env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; >

Re: [Qemu-devel] [PATCH v6 9/9] target-mips: Implement FCR31's R/W bitmask and related functionalities

> - Add preprocessor constants for all bits of FCR31 and related masks > for its subfields. Introducing all these constants for fcr31_rw_bitmask doesn't seem necessary or useful > > - Modify handling of CFC1 and CTC1 instructions (cases 25, 26, 28) > so that they utilize newly-defind

Re: [Qemu-devel] [PATCH v6 8/9] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>

. > > Related MSA instructions FTRUNC_S and FTINT_S already handle well > all cases, in the fashion similar to the code from this patch. > > Signed-off-by: Aleksandar Markovic <aleksandar.marko...@imgtec.com> > --- > target-mips/helper.h| 18 +-- > target-mips/op_helper.

[Qemu-devel] [PULL 1/2] target-mips: fix call to memset in soft reset code

t-size] This is indeed correct and due to a wrong usage of sizeof(). Fix that. Cc: Stefan Weil <s...@weilnetz.de> Cc: Leon Alrae <leon.al...@imgtec.com> Cc: qemu-sta...@nongnu.org LP: https://bugs.launchpad.net/qemu/+bug/1577841 Signed-off-by: Aurelien Jarno <aurel...@aurel32.net> Rev

[Qemu-devel] [PULL 2/2] hw/display: QOM'ify jazz_led.c

From: "xiaoqiang.zhao" <zxq_yx_...@163.com> * Drop the old SysBus init function and use instance_init * Move graphic_console_init into realize stage Signed-off-by: xiaoqiang zhao <zxq_yx_...@163.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed

[Qemu-devel] [PULL 0/2] target-mips queue

Hi, Just two patches in the first target-mips pullreq for 2.7. Thanks, Leon Cc: Peter Maydell Cc: Aurelien Jarno The following changes since commit bfc766d38e1fae5767d43845c15c79ac8fa6d6af: Update version for v2.6.0 release (2016-05-11

Re: [Qemu-devel] [Qemu-arm] [PATCH RESEND 2/5] hw/display: QOM'ify jazz_led.c

On Thu, May 05, 2016 at 01:46:13PM +0100, Peter Maydell wrote: > On 5 May 2016 at 04:04, xiaoqiang zhao wrote: > > * Drop the old SysBus init function and use instance_init > > * Move graphic_console_init into realize stage > > > > Signed-off-by: xiaoqiang zhao

Re: [Qemu-devel] [PATCH] target-mips: fix call to memset in soft reset code

tion by element size > [-Wmemset-elt-size] > > This is indeed correct and due to a wrong usage of sizeof(). Fix that. > > Cc: Stefan Weil <s...@weilnetz.de> > Cc: Leon Alrae <leon.al...@imgtec.com> > LP: https://bugs.launchpad.net/qemu/+bug/1577841 >

  1   2   3   4   5   6   7   8   9   10   >