ructions only have the AX, BX bits in
> > > there encoding, the lowest bit (usually TX) is marked as an invalid
> > > bit. We therefore can't decode them with GEN_XX2FORM, which decodes
> > > the two lowest bit.
> > >
> > > Introduce a new form GEN_XX2FORM, which
I agree that the comment is incorrect and should say sNaN square root.
On Thu, Feb 12, 2015 at 4:21 PM, Maciej W. Rozycki ma...@linux-mips.org
wrote:
On Wed, 7 Jan 2015, Alexander Graf wrote:
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 7f74466..81db60f 100644
---
On 12/19/2014 4:20 AM, Fam Zheng wrote:
On Thu, 12/18 10:34, Tom Musta wrote:
Add the supervisory Transactional Memory instructions treclaim. and
trechkpt. The implementation is a degenerate one that simply
checks privileged state, TM availability and then sets CR[0] to
0b, just like
.
Tom Musta (9):
target-ppc: Introduce Instruction Type for Transactional Memory
target-ppc: Introduce Feature Flag for Transactional Memory
target-ppc: Introduce tm_enabled Bit to CPU State
target-ppc: Power8 Supports Transactional Memory
target-ppc: Introduce TEXASRU Bit Fields
target
Add a flag (POWERPC_FLAG_TM) for the Transactional Memory
Facility introduced in Power ISA 2.07.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/cpu.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3510083..38176c0
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other available bits in the MSR (FP,
VSX, etc.).
NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc
Provide a degenerate implementation of the tbegin instruction. This
implementation always fails the transaction, recording the failure
per Book II Section 5.3.2 of the Power ISA V2.07.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/helper.h |2 ++
target-ppc/mem_helper.c
The Power8 processor implements the Transactional Memory Facility
as defined in Power ISA 2.07. Update the initialization code to
indicate this.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate_init.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git
Add a degenerate implementation of the Transaction Check (tcheck)
instruction. Since transaction always immediately fail, this
implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1
and MSR[TS] == 0.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 17
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/cpu.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 068fcb2..3510083
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
---
target-ppc/cpu.h | 20
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 38176c0..91a03f6 100644
---
Add the supervisory Transactional Memory instructions treclaim. and
trechkpt. The implementation is a degenerate one that simply
checks privileged state, TM availability and then sets CR[0] to
0b, just like the unprivileged noops.
---
target-ppc/translate.c | 38
MSR[TS] is always 0b00.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 38 ++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cddfc36..f468a5d 100644
--- a/target-ppc
On 12/18/2014 11:02 AM, Alexander Graf wrote:
On 18.12.14 17:34, Tom Musta wrote:
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
This is missing an SoB line.
Alex
Sorry about that. I will publish a V2 but may wait a day
On 12/18/2014 12:29 PM, Alexander Graf wrote:
On 18.12.14 19:10, Tom Musta wrote:
On 12/18/2014 11:02 AM, Alexander Graf wrote:
On 18.12.14 17:34, Tom Musta wrote:
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
This is missing
On 11/20/2014 8:14 AM, Alexander Graf wrote:
On 12.11.14 22:46, Tom Musta wrote:
The Floating Point Move instructions (fmr., fabs., fnabs., fneg.,
and fcpsgn.) incorrectly copy FPSCR[FPCC] instead of [FX,FEX,VX,OX].
Furthermore, the current code does this via a call to gen_compute_fprf
the aligned word of storage.
Fix the generators for these instruction to properly perform this
truncation.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate.c b
The Move to Vector Status and Control Register (mtvscr) instruction
uses VRB as the source register. Fix the code generator to correctly
decode the VRB field. That is, use rB(ctx-opcode) instead of
rD(ctx-opcode).
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c |2
?
V2 Reworked patches to pick up the gen_set_cr1_from_fpscr() utility that
was recently added by Paolo Bonzini.
Tom Musta (6):
target-ppc: VXSQRT Should Not Be Set for NaNs
target-ppc: Fix Floating Point Move Instructions That Set CR1
target-ppc: mffs. Should Set CR1 from FPSCR Bits
to void. Update the name of the local variable ret to
fprf, which now makes more sense.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 56 +-
target-ppc/helper.h |2 +-
target-ppc/translate.c |8 +--
3 files
The set_fprf argument to the gen_compute_fprf() utility is no longer
needed -- gen_compute_fprf() is now called only when FPRF is actually
computed and set. Eliminate the obsolete argument.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 38
macro to the top of the file so that it can be
re-used.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 29 +
1 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 7f74466
the gen_set_cr1_from_fpscr utility.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 50 ---
1 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 910ce56
Eliminate the set_rc argument from the gen_compute_fprf utility and
the corresponding (and incorrect) implementation. Replace it with
calls to the gen_set_cr1_from_fpscr() utility.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 55
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
On 11/8/2014 6:22 PM, Andreas Färber wrote:
Am 06.11.2014 um 20:43 schrieb Tom Musta:
When computing the upper address of a program segment, do not subtract the
offset from the virtual address; instead compute the sum of the virtual
address
and the memory size.
Note that this reads a bit
a
proper
target_timer_id typedef that is s32, just like Linux has it. It also changes
the
magic offset to a value that makes all timer ids be positive.
Reported-by: Tom Musta tommu...@gmail.com
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- Abort when magic
a
proper
target_timer_id typedef that is s32, just like Linux has it. It also changes
the
magic offset to a value that makes all timer ids be positive.
Reported-by: Tom Musta tommu...@gmail.com
Signed-off-by: Alexander Graf ag...@suse.de
---
v1 - v2:
- Abort when magic is missing
On 11/5/2014 2:04 PM, Michael Roth wrote:
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 2.2 release. This release is meant
for testing purposes and should not be used in a production environment.
When computing the upper address of a program segment, do not subtract the
offset from the virtual address; instead compute the sum of the virtual address
and the memory size.
Signed-off-by: Tom Musta tommu...@gmail.com
---
Please include this patch in QEMU 2.2.
Commit
On 11/5/2014 2:32 AM, Alexander Graf wrote:
On 05.11.14 08:13, Aravinda Prasad wrote:
This patch adds FWNMI support in qemu for powerKVM
guests by handling the ibm,nmi-register rtas call.
Whenever OS issues ibm,nmi-register RTAS call, the
machine check notification address is saved and
the gen_compute_fprf()
utility.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d03daea..7775bf4 100644
--- a/target-ppc/translate.c
+++ b
soon?
Tom Musta (7):
target-ppc: VXSQRT Should Not Be Set for NaNs
target-ppc: Introduce gen_set_cr1_from_fpscr
target-ppc: Fix Floating Point Move Instructions That Set CR1
target-ppc: mffs. Should Set CR1 from FPSCR Bits
target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
target-ppc
macro to the top of the file so that it can be
re-used.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 29 +
1 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index da93d12
the newly added gen_set_cr1_from_fpscr
utility.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 20 +++-
1 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7775bf4..9653ba9 100644
The set_fprf argument to the gen_compute_fprf() utility is no longer
needed -- gen_compute_fprf() is now called only when FPRF is actually
computed and set. Eliminate the obsolete argument.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 38
Eliminate the set_rc argument from the gen_compute_fprf utility and
the corresponding (and incorrect) implementation. Replace it with
calls to the gen_set_cr1_from_fpscr() utility.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 55
to void. Update the name of the local variable ret to
fprf, which now makes more sense.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 56 +-
target-ppc/helper.h |2 +-
target-ppc/translate.c |8 +--
3 files
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
Fix the implementation of Vector Compare Bounds Single Precision.
Specifically, fix the case where the operands are unordered -- since
the result is non-zero, the CR[6] field should be set to zero.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/int_helper.c |2 +-
1 files changed
Correct the opcodes for the vrfim, vrfin and vrfiz instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4a00935..c064cc9
Fix the implementation of the Altivec shift left and shift right
instructions (vsl, vsr) which erroneously inverts shift direction
on big endian hosts.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/int_helper.c | 13 ++---
1 files changed, 2 insertions(+), 11 deletions
On 10/9/2014 3:36 AM, Magnus Reftel wrote:
This patch introduces the -seed command line option and the
QEMU_RAND_SEED environment variable for setting the random seed, which
is used for the AT_RANDOM ELF aux entry.
This is an updated version of the patch, addressing review comments
from
kvm_regs regs;
struct kvm_sregs sregs;
-uint32_t cr;
int i, ret;
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, regs);
Otherwise ...
Reviewed-by: Tom Musta tommu...@gmail.com
);
}
Reviewed-by: Tom Musta tommu...@gmail.com
);
}
#endif
Reviewed-by: Tom Musta tommu...@gmail.com
On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
These two functions will group together four CR bits into a single
value, once we change the representation of condition registers.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
linux-user/main.c| 2 +-
target-ppc/cpu.h |
-opcode)], t1, zero,
+ true_op, cpu_gpr[rB(ctx-opcode)]);
+tcg_temp_free(t1);
tcg_temp_free_i32(t0);
+tcg_temp_free(zero);
}
/* cmpb: PowerPC 2.05 specification */
Reviewed-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu...@gmail.com
On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
This makes comparisons much smaller and faster. The speedup is
approximately 10% on user-mode emulation on x86 host, 3-4% on PPC.
Note that CRF_* constants are flipped to match PowerPC's big
bit-endianness. Previously, the CR register was
On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
Do not go through the loop when we're setting the four CR fields to
separate constants or conditions. This is clearer than putting together
4-bit value and passing it.
I guess clearer is in the eye of the beholder :)
In general, replacing a
On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
Patches 1-3 speed up softmmu emulation by avoiding TLB flushes on changes
to IR/DR.
Patches 4-14 speed up emulation in general by rewriting the handling of
condition registers.
Paolo Bonzini (14):
ppc: do not look at the MMU index to detect
On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
PowerPC TCG flushes the TLB on every IR/DR change, which basically
means on every user-kernel context switch. Encode IR/DR in the
MMU index.
This brings the number of TLB flushes down from ~90 to ~5
for starting up the Debian installer,
comments
Reviewed-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu...@gmail.com
On 9/11/2014 2:17 PM, Pierre Mallard wrote:
This patch series enable floating point instruction in 440x5 CPUs
which have the capabilities to have optional APU FPU in double precision mode.
1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
2) Create a new 440x5
On 9/12/2014 9:28 AM, Tom Musta wrote:
On 9/11/2014 2:17 PM, Pierre Mallard wrote:
This patch remove limitation for fc[tf]id[*] on 32 bits targets and
add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64
---
target-ppc/cpu.h|5 -
target-ppc/fpu_helper.c
On 9/11/2014 2:17 PM, Pierre Mallard wrote:
This patch add a new processor type 440x5wDFPU for Virtex 5 PPC440
with an external APU FPU in double precision mode
---
target-ppc/cpu-models.c |3 +++
target-ppc/translate_init.c | 38 ++
2 files
On 9/10/2014 5:43 PM, Pierre Mallard wrote:
On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta tommu...@gmail.com
mailto:tommu...@gmail.com wrote:
(1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer
Conversion instructions.
There is also fcfids and fcfidus which
On 9/10/2014 4:18 AM, Alexander Graf wrote:
On 10.09.14 07:03, Pierre Mallard wrote:
This patch declare a new floating point instruction flag PPC_FLOAT_64 to be
used
by fcfid, fctid[z] operations. Note that due to limited number of bit,
FSEL and FRES points now to same value, and
On 9/10/2014 4:19 AM, Alexander Graf wrote:
On 10.09.14 07:03, Pierre Mallard wrote:
Apply the new PPC_FLOAT_64 flag to fctid[z] and fcfid.
May also be applyed to fctidu[z] and fcfid[su][z], but since they are not
mentionned in xilinx documentation it might not be needed yet.
On 9/10/2014 4:20 AM, Alexander Graf wrote:
On 10.09.14 07:03, Pierre Mallard wrote:
This patch series enable floating point instruction in 440x5 CPUs
which have the capabilities to have optional APU FPU.
1) Add floating point standard insns flag to 440x5 in case there is an apu
fpu.
Adjust the IVOR mask for generic Book E implementation to support bit 59.
This is consistent with the Power ISA.
Signed-off-by: Tom Musta tommu...@gmail.com
Reported-by: Pierre Mallard mallard.pie...@gmail.com
---
target-ppc/translate_init.c |2 +-
1 files changed, 1 insertions(+), 1
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
This makes comparisons much smaller and faster. The speedup is
approximately 10% on user-mode emulation on x86 host, 3-4% on PPC.
Note that CRF_* constants are flipped to match PowerPC's big
bit-endianness. Previously, the CR register was
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
These two functions will group together four CR bits into a single
value, once we change the representation of condition registers.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
linux-user/elfload.c | 2 +-
linux-user/main.c|
On 9/4/2014 2:13 PM, Alexander Graf wrote:
Am 04.09.2014 um 20:38 schrieb Peter Maydell peter.mayd...@linaro.org:
On 4 September 2014 18:19, Alexander Graf ag...@suse.de wrote:
Hi Peter,
This is my current patch queue for ppc. Please pull.
Hi. I'm afraid this doesn't build (x86,
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
Match the idiom used by linux-user/signal.c and
linux-user/elfload.c.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-ppc/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/gdbstub.c
) {
-cr = 2;
+cr = 1 CRF_EQ;
}
*r = result;
Reviewed-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu...@gmail.com
) {
env-crf[0] = 0x2;
}
Reviewed-by: Tom Musta tommu...@gmail.com
-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu...@gmail.com
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-ppc/helper.h | 3 +++
target-ppc/int_helper.c | 22 ++
target-ppc/translate.c | 31 ---
3 files changed, 29 insertions(+), 27
@@ -2968,7 +2968,7 @@ static target_long monitor_get_ccr (const struct
MonitorDef *md, int val)
u = 0;
for (i = 0; i 8; i++)
-u |= env-crf[i] (32 - (4 * i));
+u |= env-crf[i] (32 - (4 * (i + 1)));
return u;
}
Reviewed-by: Tom Musta tommu...@gmail.com
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-ppc/translate.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0a85a23..afbd336 100644
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
This patch does not compile for 64 bit targets when TCG debug is enabled --
there are several places in this patch that need to be more explicit about the
i32-ness of variables. There is also a leak
On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
target-ppc/translate.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 67f13f7..48c7b66
); \
+gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(rs); \
Reviewed-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu
-by: Tom Musta tommu...@gmail.com
Tested-by: Tom Musta tommu...@gmail.com
On 8/28/2014 3:37 AM, Alexander Graf wrote:
On 28.08.14 08:38, Aravinda Prasad wrote:
On Wednesday 27 August 2014 04:07 PM, Alexander Graf wrote:
On 25.08.14 15:45, Aravinda Prasad wrote:
This patch adds FWNMI support in qemu for powerKVM
guests by handling the ibm,nmi-register rtas
On 8/28/2014 12:14 PM, Paolo Bonzini wrote:
Hi everyone,
these patches provide a speedup around 20% when running PPC softmmu
emulation on x86 machines (10% for user-mode emulation). There are
actually two separate speedups here:
* avoiding TLB flushing on every kernel-user transition
On 8/24/2014 4:42 AM, Stefan Weil wrote:
Am 24.08.2014 11:21, schrieb Michael Tokarev:
Applied to -trivial, thank you!
But I've a small concern - should we really do this on external sources,
and divirge from upstream needlessly?
Thanks,
/mjt
In general, I agree. In this case, the code
This series follows up my previous series of bug fixes to Power fixed point
instructions
(http://lists.nongnu.org/archive/html/qemu-ppc/2014-08/msg00068.html).
Richard Henderson provided additional feedback after the patches had been taken
into Aleg Graf's ppc-next tree.
Tom Musta (6):
target
The special case of rlwimi where MB = ME and SH = 31-ME can be implemented
with a single TCG deposit operation. This replaces the less general case
of SH = MB = 0 and ME = 31.
Signed-off-by: Tom Musta tommu...@gmail.com
Suggested-by: Richard Henderson r...@twiddle.net
---
target-ppc/translate.c
Optimize the special case of rlwinm where MB=0 and ME=31. This can
be implemented as a 32-bit ROTL.
Signed-off-by: Tom Musta tommu...@gmail.com
Suggested-by: Richard Henderson r...@twiddle.net
---
target-ppc/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git
Optimize mulldo by using the muls2_i64 operation rather than a helper.
Eliminate
the obsolete helper code.
Signed-off-by: Tom Musta tommu...@gmail.com
Suggested-by: Richard Henderson r...@twiddle.net
---
target-ppc/helper.h |1 -
target-ppc/int_helper.c | 27
Optimize the special case of rlwnm where MB=0 and ME=31. This can
be implemented using a ROTL.
Suggested-by: Richard Henderson r...@twiddle.net
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 56 +--
1 files changed, 34
Simplify the implementation of mullwo. For 64 bit CPUs, the result is
the concatenation of the upper and lower parts of the muls2_i32 operation,
which may be slightly better than deposit. For 32 bit CPUs, the lower part
of the muls_i32 operation is moved into the target GPR.
Signed-off-by: Tom
Eliminate the unecessary ext32s TCG operation and make the multiplication
operation explicitly 32 bit.
Signed-off-by: Tom Musta tommu...@gmail.com
Suggested-by: Richard Henderson r...@twiddle.net
---
target-ppc/translate.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff
On 8/15/2014 3:05 PM, Richard Henderson wrote:
On 08/11/2014 09:23 AM, Tom Musta wrote:
Also fix the special case of MB=31 and ME=0 to copy the entire contents
of the source GPR.
Err, that's not what you did.
if (likely(sh == 0 mb == 0 me == 31)) {
+#if defined(TARGET_PPC64
On 8/13/2014 7:31 AM, Riku Voipio wrote:
On Tue, Aug 12, 2014 at 01:53:40PM -0500, Tom Musta wrote:
The ELF V2 ABI for PPC64 defines MINSIGSTKSZ as 4096 bytes whereas it was
2048 previously.
fails to build - need to make get_ppc64_abi a properly exported function.
Riku:
Sorry about
).
That series has gone into Alex's ppcnext branch for QEMU 2.2.
V2: Addressing review comments from Peter Maydell.
V3: Included linux-user: Move get_ppc64_abi so that this series applies
cleanly
to the current git master.
Tom Musta (13):
linux-user: PPC64 semid_ds Doesnt Include _unused1 and _unused2
The 64 bit PowerPC platforms eliminate the _unused1 and _unused2
elements of the semid_ds structure from sys/sem.h. So eliminate
these from the target_semid_ds structure.
Signed-off-by: Tom Musta tommu...@gmail.com
---
linux-user/syscall.c |4
1 files changed, 4 insertions(+), 0
When the ipc system call is used to wrap a semctl system call,
the ptr argument to ipc needs to be dereferenced prior to passing
it to the semctl handler. This is because the fourth argument to
semctl is a union and not a pointer to a union.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2
and 0x2, respectively)
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Per Peter Maydell's review, added a complete set of TARGET_MCL_*
macros in the various linux-user/$ARCH/syscall.h files.
linux-user/aarch64/syscall.h|2 ++
linux-user/alpha/syscall.h |2 ++
linux-user/arm
The msgsnd system call takes an argument that describes the message
size (msgsz) and is of type size_t. The system call should set
errno to EINVAL in the event that a negative message size is passed.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
this for syscalls with standard return values.
Add special case code for clock_nanosleep to handle CR0 properly.
Signed-off-by: Tom Musta tommu...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
V2: Eliminated redundant #if defined condition per Peter Maydell's
review.
linux
The get_ppc64_abi is used to determine the ELF ABI (i.e. V1 or V2). This
routine is currently implemented in the linux-user/elfload.c file but
is useful in other scenarios. Move the routine to a more generally
available location (linux-user/ppc/target_cpu.h).
Signed-off-by: Tom Musta tommu
-by: Tom Musta tommu...@gmail.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
V2: Use bool instead of int for bad_address per Peter Maydell's review.
linux-user/syscall.c | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux
The ELF V2 ABI for PPC64 defines MINSIGSTKSZ as 4096 bytes whereas it was
2048 previously.
Signed-off-by: Tom Musta tommu...@gmail.com
---
V2: Define and use TARGET_MINSIGSTKSZ constants from the various
linux-user/$ARCH/syscall.h files (per Peter Maydell's review).
linux-user/aarch64/syscall.h
On 8/11/2014 10:06 PM, David Gibson wrote:
On Mon, Aug 11, 2014 at 02:23:21PM -0500, Tom Musta wrote:
These patches fix assorted bugs in the emulation of Power Fixed Point Unit
instructions.
All instructions have been thorougly tested by running millions of random
patterns through actual
.
V2: Added example data patterns to commit messages (no functional change from
V1).
Tom Musta (8):
target-ppc: Bug Fix: rlwinm
target-ppc: Bug Fix: rlwnm
target-ppc: Bug Fix: rlwimi
target-ppc: Bug Fix: mullw
target-ppc: Bug Fix: mullwo
target-ppc: Bug Fix: mulldo OV Detection
target
: A6212433228F41DC (without this patch)
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4904665..61fa42d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc
, padding with
zeroes in the most significant bits.
Fix the code to properly implement this ROTL32 operation.
Example:
R3 = 0002
R4 = 7FFF
rlwnm 3,3,4,31,16
R3 expected : 00010001
R3 actual : 0001 (without this patch)
Signed-off-by: Tom Musta tommu
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