On 6/15/23 08:21, Nicholas Piggin wrote:
On Wed Jun 14, 2023 at 3:51 PM AEST, Anushree Mathur wrote:
On 5/30/23 18:55, Nicholas Piggin wrote:
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running
On Wed Jun 14, 2023 at 3:51 PM AEST, Anushree Mathur wrote:
>
> On 5/30/23 18:55, Nicholas Piggin wrote:
> > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> > after cpu_ldl_code(). This corrects DSISR bits in alignment
> > interrupts when running in little endian mode.
> >
> >
On 5/30/23 18:55, Nicholas Piggin wrote:
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
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