On 5/30/23 18:55, Nicholas Piggin wrote:
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
On 6/11/23 18:00, Peter Maydell wrote:
Convert the ASIMD load/store single structure insns to decodetree.
Signed-off-by: Peter Maydell
Message-id:20230602155223.2040685-20-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 34 +
target/arm/tcg/translate-a64.c | 219
On 6/11/23 18:00, Peter Maydell wrote:
Convert the load/store register pair insns (LDP, STP,
LDNP, STNP, LDPSW, STGP) to decodetree.
Signed-off-by: Peter Maydell
Message-id:20230602155223.2040685-12-peter.mayd...@linaro.org
---
This was reviewed in v1, but the underlying code
changed enough in
On Tue Jun 6, 2023 at 12:57 AM AEST, Cédric Le Goater wrote:
> On 6/4/23 01:36, Nicholas Piggin wrote:
> > diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> > new file mode 100644
> > index 00..04ef703e0f
> > --- /dev/null
> > +++ b/hw/ppc/pnv_chiptod.c
> > @@ -0,0 +1,488 @@
> >
On 6/11/23 18:00, Peter Maydell wrote:
In the recent refactoring we missed a few places which should be
calling finalize_memop_asimd() for ASIMD loads and stores but
instead are just calling finalize_memop(); fix these.
For the disas_ldst_single_struct() and disas_ldst_multiple_struct()
cases,
On 6/11/23 18:00, Peter Maydell wrote:
In disas_ldst_reg_imm9() we missed one place where a call to
a gen_mte_check* function should now be passed the memop we
have created rather than just being passed the size. Fix this.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 2 +-
On 6/13/23 15:33, Philippe Mathieu-Daudé wrote:
Since we*might* have user emulation with softmmu,
use the clearer 'CONFIG_SYSTEM_ONLY' key to check
for system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build| 4 ++--
accel/qtest/meson.build
On 6/13/23 15:33, Philippe Mathieu-Daudé wrote:
We use the CONFIG_USER_ONLY key to describe user emulation,
and the CONFIG_SOFTMMU key to describe system emulation. Alias
it as 'CONFIG_SYSTEM_ONLY' for parity with user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 1 +
1
On 6/13/23 15:33, Philippe Mathieu-Daudé wrote:
Since cpu_mmu_index() is well-defined for user-only,
we can remove the surrounding #ifdef'ry entirely.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/tcg/translate.c | 3 ---
1 file changed, 3 deletions(-)
On Tue Jun 6, 2023 at 11:59 PM AEST, Cédric Le Goater wrote:
> On 6/4/23 01:36, Nicholas Piggin wrote:
> > This adds support for chiptod and core timebase state machine models in
> > the powernv POWER9 and POWER10 models.
> >
> > This does not actually change the time or the value in TB registers
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Since commit 139c1837db ("meson: rename included C source files
to .c.inc"), QEMU standard procedure for included C files is to
use *.c.inc.
Besides, since commit 6a0057aa22 ("docs/devel: make a statement
about includes") this is documented as the
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/tcg/vec_helper.c
@@ -19,12 +19,15 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h"
#include "qemu/int128.h"
#include
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/helper.c
@@ -26,6 +26,11 @@
#include "qapi/error.h"
#include "qemu/guest-random.h"
#ifdef CONFIG_TCG
+
+#define HELPER_H "helper.h"
+#include "exec/helper-gen.h.inc"
+#undef HELPER_H
Why is this here? helper-gen is for
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/tcg/translate.c
@@ -37,6 +37,11 @@
#include "exec/helper-gen.h.inc"
#undef HELPER_H
+#define HELPER_H "tcg/helper-m.h.inc"
+#include "exec/helper-proto.h.inc"
+#include "exec/helper-gen.h.inc"
+#undef HELPER_H
You don't
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
helper.h is used by all units, but not all require the
M-profile definitions. Move them to a new header; the next
commit will remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 17
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
No need to have the v8m_stackcheck() helper in the generic
op_helper.c, move it with the rest of the M-profile helpers.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/m_helper.c | 16
target/arm/tcg/op_helper.c | 16
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-a64.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 4
target/arm/tcg/helper-a64.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-sme.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sme_helper.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-mve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 2 --
target/arm/tcg/mve_helper.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-sve.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h| 1 -
target/arm/tcg/sve_helper.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-neon.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/neon_helper.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
Instead of including helper-vfp.h.inc via helper.h which
is included by all TCG files, restrict it to the few files
that require it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/helper.h | 1 -
target/arm/tcg/mve_helper.c
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
helper.h is used by all units, but not all require the VFP
definitions. Move them to a new header; the next commit will
remove it from the common helper.h.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO check recpe/rsqrte/rint* are VFP
Yep.
Hi, I want to add ACK and PWR leds support in the qemu raspi machine so
from the terminal of emulated raspi I should able to control these leds, I
coudn't able to understand the hardware level controlling of this leds , so
if any can help me to start on that then it would be great .
Thanks &
On 6/14/23 03:19, Alistair Francis wrote:
The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
Merge tag 'pull-ppc-20230610' ofhttps://gitlab.com/danielhb/qemu into
staging (2023-06-10 07:25:00 -0700)
are available in the Git repository at:
)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/misc-20230613
for you to fetch changes up to b0182e537e5aba38031a5009cb16d5e924342458:
exec/memory: Introduce RAM_NAMED_FILE flag (2023-06-13 11:28:58 +0200
On 6/13/23 21:34, Lucas Dietrich wrote:
This commit addresses a bug in the AVR interrupt handling code.
The modification involves replacing the usage of the ctz32 function
with ctz64 to ensure proper handling of interrupts above 33 in the AVR
target.
Previously, timers 3, 4, and 5 interrupts
On 6/12/23 02:10, Vikram Garhwal wrote:
Found the fix. QTest adds 'accel = qtest' and xen machines already have "accel = xen"
option by default. Adding this xenpvh machine to skip fixed the issue, other xen machines
are already in skip list. I am running the gitlab-ci locally to see if there
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> After previous changes the hypercall handling in 7xx and 74xx
> exception handlers can be folded into one if statement to simpilfy
> this code.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/excp_helper.c | 26
On 6/8/23 19:49, ~jhogberg wrote:
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, and require the explicit use of cache
management instructions as well as an instruction
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
> the unused define as well.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/translate.c | 1 -
> 1 file changed, 1 deletion(-)
>
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Improve readability by shortening some long comments, removing
> comments that state the obvious and dropping some empty lines so they
> don't distract when reading the code.
Some changes are a matter of taste, but in the interest of
On Tue, 13 Jun 2023, David Hildenbrand wrote:
> On 13.06.23 10:26, Kasireddy, Vivek wrote:
> >> On 12.06.23 09:10, Kasireddy, Vivek wrote:
> >>> Sorry for the late reply; I just got back from vacation.
> >>> If it is unsafe to directly use the subpages of a hugetlb page, then
> >>> reverting
> >>>
On 6/12/23 16:46, Alex Bennée wrote:
Richard Henderson writes:
Use a shared driver and backends for i386, aarch64, ppc64, riscv64.
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/test-aes.c| 58
tests/tcg/i386/test-aes.c | 68 +
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Use the env_cpu function to get the CPUState for cpu_abort. These are
> only needed in case of fatal errors so this allows to avoid casting
> and storing CPUState in a local variable wnen not needed.
I don't entirely mind keeping cs
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> All powerpc exception handlers share some code when handling machine
> check exceptions. Move this to a common function.
>
> Signed-off-by: BALATON Zoltan
Hah, I just did very similar to improve some checkstop code (but I can
rebase my
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> CPUState is rarely needed by this function (only for logging a fatal
> error) and it's easy to get from the env parameter so passing it
> separately is not necessary.
>
> Signed-off-by: BALATON Zoltan
Caller does have env already, but
Currently, we use the current env->xl as the xlen for address. However, the
xlen for data address should be changed to the xlen related to MPP when MPRV=1.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream
Weiwei Li (2):
target/riscv: Add additional
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
> ---
> target/ppc/excp_helper.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index
As specified in privilege spec:"When MPRV=1, load and store memory
addresses are treated as though the current XLEN were set to MPP’s
XLEN". So the xlen for address may be different from current xlen.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.h| 49
Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
should also take MPRV into consideration. As pointer mask for instruction
is not supported currently, so we can directly update cur_pmbase/pmmask
based on address related mode and xlen affected by MPRV now.
Signed-off-by: Weiwei
> On Mon, May 29, 2023 at 08:30:44PM +0800, Zhao Liu wrote:
> > Date: Mon, 29 May 2023 20:30:44 +0800
> > From: Zhao Liu
> > Subject: [PATCH v2 00/17] Support smp.clusters for x86
> > X-Mailer: git-send-email 2.34.1
> >
> > From: Zhao Liu
> >
> > Hi list,
> >
> > This is the our v2 patch series,
在 2023/6/13 下午8:55, Philippe Mathieu-Daudé 写道:
On 13/6/23 14:32, Tianrui Zhao wrote:
Supplement LoongArch cpu topology arguments, including support socket
and threads per core.
Base-on:
https://patchew.org/QEMU/20230613122613.2471743-1-zhaotian...@loongson.cn/
^ FYI this tag ...
From: Weiwei Li
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Message-Id: <20230524015933.17349-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
From: Daniel Henrique Barboza
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel
From: Weiwei Li
We no longer need the pmp_index for matched PMP entry now.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20230517091519.34439-5-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/pmp.h| 8
From: Sunil V L
pflash devices can be used in virt machine for different
purposes like for ROM code or S-mode FW payload. Add a
section in the documentation on how to use pflash devices
for different purposes.
Signed-off-by: Sunil V L
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair
From: Weiwei Li
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them
From: Daniel Henrique Barboza
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
From: Weiwei Li
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: LIU Zhiwei
Message-Id: <20230524015933.17349-3-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Weiwei Li
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-Id: <20230517091519.34439-11-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
From: Weiwei Li
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
From: Xiao Wang
There's no code using MTYPE, which was a concept used in older vector
implementation.
Signed-off-by: Xiao Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Message-Id: <20230608053517.4102648-1-xiao.w.w...@intel.com>
Signed-off-by: Alistair Francis
---
From: Weiwei Li
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20230526072124.298466-4-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Sunil V L
Currently, pflash devices can be configured only via -pflash
or -drive options. This is the legacy way and the
better way is to use -blockdev as in other architectures.
libvirt also has moved to use -blockdev method.
To support -blockdev option, pflash devices need to be
created
From: Weiwei Li
We initialize cur_pmmask as -1(UINT32_MAX/UINT64_MAX) and regard it
as if pointer mask is disabled in current implementation. However,
the addresses for vector load/store will be adjusted to zero in this
case and -1(UINT32_MAX/UINT64_MAX) is valid value for pmmask when
pointer
From: Philippe Mathieu-Daudé
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination. This
is in preparation of adding the OpenTitan machine type to
this array in a pair of commits.
From: Weiwei Li
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and
From: Weiwei Li
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20230526072124.298466-5-liwei...@iscas.ac.cn>
From: Weiwei Li
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-Id: <20230523093539.203909-6-liwei...@iscas.ac.cn>
Signed-off-by:
From: Ivan Klokov
Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
Signed-off-by: Ivan Klokov
Reviewed-by: Alistair Francis
Message-Id: <20230410124451.15929-2-ivan.klo...@syntacore.com>
Signed-off-by: Alistair Francis
---
include/hw/core/cpu.h | 2 ++
From: Weiwei Li
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Message-Id: <20230523093539.203909-8-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 201
From: Weiwei Li
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Message-Id: <20230523093539.203909-9-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
From: Sunil V L
Currently, virt machine supports two pflash instances each with
32MB size. However, the first pflash is always assumed to
contain M-mode firmware and reset vector is set to this if
enabled. Hence, for S-mode payloads like EDK2, only one pflash
instance is available for use. This
From: Weiwei Li
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Message-Id: <20230517091519.34439-10-liwei...@iscas.ac.cn>
Signed-off-by:
From: Xiao Wang
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added an extra check for LMUL fragmentation,
intended for setting the "rest tail elements" in the last register for a
segment load insn.
Actually, the max_elements derived in
From: Philippe Mathieu-Daudé
Expand the DEFINE_MACHINE() macro, converting the class_init()
handler.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230520054510.68822-5-phi...@linaro.org>
Signed-off-by: Alistair Francis
From: Weiwei Li
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang
From: Mayuresh Chitale
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20230518175058.2772506-4-mchit...@ventanamicro.com>
Signed-off-by: Alistair
From: Weiwei Li
Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then remove
pmp_update_rule() since it become unused.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-Id: <20230523093539.203909-5-liwei...@iscas.ac.cn>
Signed-off-by:
From: Himanshu Chauhan
On an address match, skip checking for default permissions and return error
based on access defined in PMP configuration.
v3 Changes:
o Removed explicit return of boolean value from comparision
of priv/allowed_priv
v2 Changes:
o Removed goto to return in place when
From: Philippe Mathieu-Daudé
QOM type names are usually defined as TYPE_FOO.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230520054510.68822-4-phi...@linaro.org>
Signed-off-by: Alistair Francis
---
From: Mayuresh Chitale
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
and check for it when accessing the fcsr register and its fields.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Currently only the rule addr of the same index of pmpaddr is updated
when pmpaddr CSR is modified. However, the rule addr of next PMP entry
may also be affected if its A field is PMP_AMATCH_TOR. So we should
also update it in this case.
Write to pmpaddr CSR will not affect the
From: Tommy Wu
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu
Reviewed-by:
From: Daniel Henrique Barboza
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by:
From: Weiwei Li
Return the result directly for short cut, since We needn't do the
following check on the PMP entries if there is no PMP rules.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20230517091519.34439-4-liwei...@iscas.ac.cn>
From: Weiwei Li
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair
From: Philippe Mathieu-Daudé
OpenTitanState is the 'machine' (or 'board') state: it isn't
a SysBus device, but inherits from the MachineState type.
Correct the instance size.
Doing so we avoid leaking an OpenTitanState pointer in
opentitan_machine_init().
Fixes: fe0fe4735e ("riscv: Initial
From: Weiwei Li
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-Id:
From: Weiwei Li
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-Id:
From: Daniel Henrique Barboza
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tweak first. When
From: Yin Wang
Command "qemu-system-riscv64 -machine virt
-m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
would trigger this problem.Backtrace with:
#0 0x55b5b1a4 in riscv_numa_get_default_cpu_node_id at
../hw/riscv/numa.c:211
#1 0x558ce510 in machine_numa_finish_cpu_init
From: Weiwei Li
Access will fail if access is partially inside the PMP entry.
However,only setting ret = false doesn't really mean pmp violation
since pmp_hart_has_privs_default() may return true at the end of
pmp_hart_has_privs().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
From: Weiwei Li
Split RISCVCPUConfig declarations to prepare for passing it to disas.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230523093539.203909-3-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Mayuresh Chitale
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
From: Daniel Henrique Barboza
The function is a no-op if 'vta' is zero but we're still doing a lot of
stuff in this function regardless. vext_set_elems_1s() will ignore every
single time (since vta is zero) and we just wasted time.
Skip it altogether in this case. Aside from the code
From: Daniel Henrique Barboza
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-Id: <20230517135714.211809-4-dbarb...@ventanamicro.com>
From: Daniel Henrique Barboza
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every
From: Philippe Mathieu-Daudé
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Daniel
From: Daniel Henrique Barboza
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make
From: Weiwei Li
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair
From: Daniel Henrique Barboza
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled
From: Weiwei Li
The addr and size parameters in pmp_hart_has_privs_default() are unused.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20230517091519.34439-7-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/pmp.c | 9
From: Weiwei Li
PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x8008~0x800F, R) and PMP1 (0x8000~
0x8FFF, RWX), write access to 0x8000 will
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