On Fri, Jun 23, 2023 at 8:41 AM Peter Maydell wrote:
>
> In handle_interrupt() we use level as an index into the interrupt_vector[]
> array. This is safe because we have checked it against env->config->nlevel,
> but Coverity can't see that (and it is only true because each CPU config
> sets its
On 23/6/23 14:37, Cédric Le Goater wrote:
On 6/23/23 11:10, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
ppc has always silently ignored access to real (physical) addresses
with nothing behind it, which can make debugging difficult at times.
It looks like the
On 24/6/23 01:08, Philippe Mathieu-Daudé wrote:
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the QEMU deprecation policy, we shouldn't remove it before
QEMU
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort
HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark
HAXM in QEMU as deprecated"), released in v8.0.0.
Per the QEMU deprecation policy, we shouldn't remove it before
QEMU release v8.2.0. However per the latest HAXM release
On 2/10/20 13:36, Alex Bennée wrote:
From: Thomas Huth
We do not support Debian 9 in QEMU anymore, and the Debian 9 containers
are now no longer used in the gitlab-CI. Time to remove them.
Signed-off-by: Thomas Huth
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Reviewed-by:
On 23/6/23 19:25, Peter Maydell wrote:
When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
ldwr3,0(r4)
results on an x86 host in the TCG IR
qemu_ld_a32_i32
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1725
This fix is implemented by having the vCont handler set the value of
`gdbserver_state.c_cpu` if any threads are to be resumed. The specific CPU
is picked arbitrarily from the ones to be resumed, but it should be okay, as all
GDB cares
On Intel CPUs there are certain bits in MSR_ARCH_CAPABILITIES that
indicates if the CPU is not affected by a vulnerability. Without these
bits guests may try to deploy the mitigation even if the CPU is not
affected.
Export the bits to guests that indicate immunity to hardware
vulnerabilities.
On 6/23/2023 2:25 PM, Steven Sistare wrote:
> On 6/21/2023 4:28 PM, Peter Xu wrote:
>> On Wed, Jun 21, 2023 at 03:15:42PM -0400, Steven Sistare wrote:
>>> On 6/20/2023 5:46 PM, Peter Xu wrote:
On Thu, Jun 15, 2023 at 01:26:39PM -0700, Steve Sistare wrote:
> Migration of a guest in the
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's
SUN Type 4, 5 and 5c keyboards have dip switches to choose the language layout
of the keyboard. Solaris makes an ioctl to query the value of the dipswitches
and uses that value to select keyboard layout. Also the SUN bios like the one
in the file ss5.bin uses this value to support at least
On 6/21/2023 4:28 PM, Peter Xu wrote:
> On Wed, Jun 21, 2023 at 03:15:42PM -0400, Steven Sistare wrote:
>> On 6/20/2023 5:46 PM, Peter Xu wrote:
>>> On Thu, Jun 15, 2023 at 01:26:39PM -0700, Steve Sistare wrote:
Migration of a guest in the suspended state is broken. The incoming
On 22.06.2023 20:45, Maciej S. Szmigiero wrote:
On 22.06.2023 14:52, David Hildenbrand wrote:
On 22.06.23 14:14, Maciej S. Szmigiero wrote:
On 22.06.2023 14:06, David Hildenbrand wrote:
On 22.06.23 13:17, Maciej S. Szmigiero wrote:
On 22.06.2023 13:15, David Hildenbrand wrote:
On 22.06.23
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
>
> Hi,
>
> On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> > From: qianfan Zhao
> >
> > Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> > and a Mali400 MP2 GPU from ARM. It's also known as the
On Sun, Jun 18, 2023 at 08:40:28AM +0800, qianfan wrote:
>
> 在 2023/6/18 0:29, Guenter Roeck 写道:
> > Hi,
> >
> > On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> > > From: qianfan Zhao
> > >
> > > Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> > >
When we generate code for guest loads and stores, at the moment they
end up being requests for a host-endian access. So for target-system-nios2
(little endian) a load like
ldwr3,0(r4)
results on an x86 host in the TCG IR
qemu_ld_a32_i32 r3,loc2,al+leul,0
but on s390 it is
Hi Peter,
On 2/28/23 10:36, Eric Auger wrote:
> Some registers whose 'cooked' writefns induce TLB maintenance do
> not have raw_writefn ops defined. If only the writefn ops is set
> (ie. no raw_writefn is provided), it is assumed the cooked also
> work as the raw one. For those registers it is
On Fri, 23 Jun 2023, Fabiano Rosas wrote:
Nicholas Piggin writes:
From: BALATON Zoltan
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Maybe Machine Check is simple enough, but this kind of sharing of code
has
Peter Maydell writes:
> On Fri, 23 Jun 2023 at 16:21, Alex Bennée wrote:
>>
>>
>> Peter Maydell writes:
>>
>> > The xkb official name for the Arabic keyboard layout is 'ara'.
>> > However xkb has for at least the past 15 years also permitted it to
>> > be named via the legacy synonym 'ar'.
Richard Henderson writes:
> Test for invalid, integer overflow, and inexact.
> Test for proper result, modulo 2**64.
>
> Signed-off-by: Richard Henderson
Acked-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> This is a perfectly natural occurrence for x86 "rep movb",
> where the "rep" prefix forms a counted loop of the one insn.
>
> During the tests/tcg/multiarch/memory test, this logging is
> triggered over 35 times. Within the context of cross-i386-tci
> build,
In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
On 23/6/23 14:21, Nicholas Piggin wrote:
VOF is the new lightweight fast pseries bios. Add a Linux boot test
using VOF.
More tests could be moved to use VOF becasue it's much faster, but
Typo "because".
just dip one toe in the water first here. SLOF should continue to be
tested too.
On 23/5/23 20:59, David Hildenbrand wrote:
Let's fixup the documentation (e.g., removing traces of the ram_addr
parameter that no longer exists) and move it to the header file while at
it.
Suggested-by: Igor Mammedov
Acked-by: Igor Mammedov
Reviewed-by: Peter Xu
Signed-off-by: David
On Fri, 23 Jun 2023 at 16:21, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > The xkb official name for the Arabic keyboard layout is 'ara'.
> > However xkb has for at least the past 15 years also permitted it to
> > be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
> >
On 6/23/23 03:26, Michael S. Tsirkin wrote:
On Mon, May 22, 2023 at 11:31:57PM +0700, Bui Quang Minh wrote:
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to
Cédric Le Goater writes:
> Hello Anushree,
>
> On 6/23/23 13:09, Anushree Mathur wrote:
>> Hi everyone,
>> I was trying to boot rhel9.3 image with upstream qemu-system-ppc64
>> -smp 2 option and observed a segfault (qemu crash).
>> qemu command line used:
>> qemu-system-ppc64 -name
Peter Maydell writes:
> The xkb official name for the Arabic keyboard layout is 'ara'.
> However xkb has for at least the past 15 years also permitted it to
> be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
> synoynm was removed, which breaks compilation of QEMU:
Queued
On 23/6/23 16:44, Peter Maydell wrote:
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
the address of the local variable htx. This means it can never be
NULL, but later in the code we check it for NULL anyway. Coverity
complains about this (CID 1507683) because the NULL
On 23/6/23 14:20, Alex Bennée wrote:
From: Marcin Juszkiewicz
Update prebuilt firmware images to have TF-A with FEAT_FGT support
enabled. This allowed us to enable test for "max" cpu in sbsa-ref
machine.
Signed-off-by: Marcin Juszkiewicz
Message-Id:
On Fri, Jun 23, 2023 at 10:51:53AM -0400, Peter Xu wrote:
> On Fri, Jun 23, 2023 at 09:23:18AM +0100, Daniel P. Berrangé wrote:
> > On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > > On Thu, Jun 22, 2023 at 10:59:58AM +0100, Daniel P. Berrangé wrote:
> > > > I've mentioned several
On 23/6/23 14:20, Alex Bennée wrote:
This is yet another make target you usually run in the top level of
the source directory.
Signed-off-by: Alex Bennée
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, Jun 22, 2023 at 7:48 PM Michael S. Tsirkin wrote:
>
> On Thu, Jun 22, 2023 at 05:46:40PM +0200, Julia Suvorova wrote:
> > On Thu, Jun 22, 2023 at 12:34 PM Ani Sinha wrote:
> > >
> > > PCI Express ports only have one slot, so PCI Express devices can only be
> > > plugged into slot 0 on a
On Fri, Jun 23, 2023 at 09:23:18AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > On Thu, Jun 22, 2023 at 10:59:58AM +0100, Daniel P. Berrangé wrote:
> > > I've mentioned several times before that the user should never need to
> > > set this
Dear Daniel,
Thanks for your comments. Incorporated the same and updated the patch set as
v3.
https://lists.gnu.org/archive/html/qemu-riscv/2023-06/msg00570.html
Regards,
Lakshmi
-Original Message-
From: Daniel Henrique Barboza
Sent: Friday, June 23, 2023 12:16 AM
To: Lakshmi Bai
On Thu, 2 Mar 2023 at 12:50, Paolo Bonzini wrote:
>
> From: David Woodhouse
>
> If I advertise XENFEAT_hvm_pirqs then a guest now boots successfully as
> long as I tell it 'pci=nomsi'.
>
> [root@localhost ~]# cat /proc/interrupts
>CPU0
> 0: 52 IO-APIC 2-edge timer
In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
the address of the local variable htx. This means it can never be
NULL, but later in the code we check it for NULL anyway. Coverity
complains about this (CID 1507683) because the NULL check comes after
a call to clock_adjtime()
On Fri, 23 Jun 2023 06:05:28 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Jun 07, 2023 at 03:57:16PM -0500, Suravee Suthikulpanit wrote:
> > Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> > (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> >
On Fri, Jun 23, 2023 at 08:17:46AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 22, 2023 at 03:20:01PM -0400, Peter Xu wrote:
> > On Thu, Jun 22, 2023 at 05:33:29PM +0100, Daniel P. Berrangé wrote:
> > > On Thu, Jun 22, 2023 at 11:54:43AM -0400, Peter Xu wrote:
> > > > I can try to move the todo
From: Lakshmi Bai Raja Subramanian
fdt_load_addr is declared as uint32_t which is not matching with the
return data type of riscv_compute_fdt_addr. Modified fdt_load_addr data type
to uint64_t to match the riscv_compute_fdt_addr() return data type. This fix
also helps in calculating the right
On 6/23/23 06:58, Andrew Jones wrote:
On Thu, Jun 22, 2023 at 10:56:57AM -0300, Daniel Henrique Barboza wrote:
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM.
On 6/23/23 06:38, Andrew Jones wrote:
On Thu, Jun 22, 2023 at 10:56:53AM -0300, Daniel Henrique Barboza wrote:
...
+#define KVM_MISA_CFG(_bit, _reg_id) \
+{.offset = _bit, .kvm_reg_id = _reg_id}
+
+/* KVM ISA extensions */
+static KVMCPUConfig kvm_misa_ext_cfgs[] = {
+
On Fri, Jun 23, 2023 at 8:45 AM Michael S. Tsirkin wrote:
> On Wed, May 24, 2023 at 11:13:32AM +0200, Albert Esteve wrote:
> > Add new vhost-user protocol message
> > `VHOST_USER_BACKEND_SHARED_OBJECT`. This new
> > message is sent from vhost-user back-ends
> > to interact with the virtio-dmabuf
Hello Anushree,
On 6/23/23 13:09, Anushree Mathur wrote:
Hi everyone,
I was trying to boot rhel9.3 image with upstream qemu-system-ppc64 -smp 2
option and observed a segfault (qemu crash).
qemu command line used:
qemu-system-ppc64 -name Rhel9.3.ppc64le -smp 2 -m 16G -vga none -nographic
On Thu, 6 Apr 2023 at 17:25, Woodhouse, David wrote:
>
> On Thu, 2023-04-06 at 16:48 +0100, Peter Maydell wrote:
> > On Thu, 2 Mar 2023 at 12:37, Paolo Bonzini wrote:
> > >
> > > From: David Woodhouse
> > >
> > > The way that Xen handles MSI PIRQs is kind of awful.
> >
> > > Now that this is
This patch refactors vhost_vdpa_net_load_rx() to
restore the packet receive filtering state in relation to
VIRTIO_NET_F_CTRL_RX_EXTRA feature at device's startup.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
This series enables shadowed CVQ to intercept rx commands related to
VIRTIO_NET_F_CTRL_RX_EXTRA feature through shadowed CVQ, update the virtio
NIC device model so qemu send it in a migration, and the restore of
that rx state in the destination.
To test this patch series, I modify the
Enable SVQ with VIRTIO_NET_F_CTRL_RX_EXTRA feature.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 9b929762c5..cdfe8e454e 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -100,6 +100,7 @@
On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
>
> From: Jonathan Cameron
>
> This Data Object Exchange Mailbox allows software to query the
> latency and bandwidth between ports on the switch. For now
> only provide information on routes between the upstream port and
> each downstream
On Thu, 22 Jun 2023 13:41:32 +0200
Thomas Huth wrote:
> It's good style to clean up temporary directories when they
> are not needed anymore.
>
> Signed-off-by: Thomas Huth
Acked-by: Jonathan Cameron
> ---
> tests/qtest/cxl-test.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
Nicholas Piggin writes:
> From: BALATON Zoltan
>
> All powerpc exception handlers share some code when handling machine
> check exceptions. Move this to a common function.
>
Maybe Machine Check is simple enough, but this kind of sharing of code
has historically caused pain when people want to
WBNOINVD is the same as INVD or WBINVD as far as TCG is concerned,
since there is no cache in TCG and therefore no invalidation side effect
in WBNOINVD.
With respect to SVM emulation, processors that do not support WBNOINVD
will ignore the prefix and treat it as WBINVD, while those that support
XSAVEERPTR is actually a fix for an errata; TCG does not have the issue.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc4246223d4..bce0cb73e85
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4
target/i386/tcg/translate.c | 9 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 695e01582bf..978d24b5ec7 100644
---
Suggested-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 0de068d4b79..4ef45bbd71e 100644
--- a/target/i386/tcg/translate.c
+++
AMD supports both 32-bit and 64-bit SYSCALL/SYSRET, but the TCG only
exposes it for 64-bit targets. For system emulation just reuse the
helper; for user-mode emulation the ABI is the same as "int $80".
The BSDs does not support any fast system call mechanism in 32-bit
mode so add to bsd-user the
RDPID corresponds to a RDMSR(TSC_AUX); however, it is unprivileged
so for user-mode emulation we must provide the value that the kernel
places in the MSR. For Linux, it is a combination of the current CPU
and the current NUMA node, both of which can be retrieved with getcpu(2).
Also try
TCG implements RDSEED, and in fact uses qcrypto_random_bytes which is
secure enough to match hardware behavior. Expose it to guests.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
In preparation for supporting named CPU models for user-mode emulation,
add a few TCG features that are actually already implemented, or that
are easy to implement. The most important (and most relevant to user-mode
emulation) are RDSEED, RDPID, and for 32-bit processors SYSCALL as well.
Paolo
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index ed4016f554b..a20b5af71e7 100644
--- a/target/i386/tcg/translate.c
+++
Due to a typo or perhaps a brain fart, the INVD vmexit was never generated.
Fix it (but not that fixing just the typo would break both INVD and WBINVD,
due to a case of two wrongs making a right).
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a20b5af71e7..66800392bb9 100644
--- a/target/i386/tcg/translate.c
The AMD prefetch(w) instructions have not been deprecated together with the rest
of 3DNow!, and in fact are even supported by newer Intel processor. Mark them
as supported by TCG, as it supports all of 3DNow!.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c |
On Fri, 26 May 2023 at 16:32, Eugenio Pérez wrote:
>
> QEMU v8.0 is able to switch dynamically between vhost-vdpa passthrough
> and SVQ mode as long as the net device does not have CVQ. The net device
> state followed (and migrated) by CVQ requires special care.
>
> A pre-requisite to add CVQ to
spapr_machine_reset gets a random number to populate the device-tree
rng seed with. When loading a snapshot for record-replay, the machine
is reset again, and that tries to consume the random event record
again, crashing due to inconsistent record
Fix this by saving the seed to populate the
This thing seems to have fallen by the wayside. This quick hack gets
it vaguely working with the current format. It was some use in fixing
rr support for ppc, so maybe others will find it useful too.
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py | 89
Timebase save uses a random number for a legacy vmstate field, which
makes rr snapshot loading unbalanced. The easiest way to deal with this
is just to skip the rng if record-replay is active.
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c | 11 +--
1 file changed, 9 insertions(+), 2
This the ppc64 record-replay test is able to replay the full kernel boot
so try enabling it.
Signed-off-by: Nicholas Piggin
---
tests/avocado/replay_kernel.py | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
pseries can run reverse-debugging well enough to pass basic tests.
There is strangeness with reverse-continue possibly relating to a bp
being set on the first instruction or on a snapshot, that causes
the PC to be reported on the first instruction rather than last
breakpoint, so a workaround is
ppc only migrates reserve_addr, so the destination machine can get a
valid reservation with an incorrect reservation value of 0. Prior to
commit 392d328abe753 ("target/ppc: Ensure stcx size matches larx"),
this could permit a stcx. to incorrectly succeed. That commit
inadvertently fixed that bug
When the machine is reset to load a new snapshot while being debugged
with replay-record, it is done from another thread, so the CPU does
not run the register setting operations. Set CPU registers directly in
machine reset.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 20
Hi, this is a bit of an RFC patch, I may need to send patches to
different trees to merge but they kind of go together.
The primary motivation is to fix migrating larx reservations,
previously discussed here:
https://lists.gnu.org/archive/html/qemu-ppc/2023-06/msg00452.html
It turns out a
On 23.05.23 20:59, David Hildenbrand wrote:
Following up on my previous work to make virtio-mem consume multiple
memslots dynamically [1] that requires precise accounting between used vs.
reserved memslots, I realized that vhost makes this extra hard by
filtering out some memory region sections
On 23.05.23 20:30, David Hildenbrand wrote:
Let's separate plug and unplug handling to prepare for future changes
and make the code a bit easier to read -- working on block states
(plugged/unplugged) instead of on a bitmap.
Cc: "Michael S. Tsirkin"
Cc: Gavin Shan
Signed-off-by: David
On Fri, 16 Dec 2022 at 20:51, Taylor Simpson wrote:
>
> From: Anton Johansson
>
> Signed-off-by: Alessandro Di Federico
> Signed-off-by: Paolo Montesel
> Signed-off-by: Anton Johansson
> Signed-off-by: Taylor Simpson
> Reviewed-by: Taylor Simpson
> Message-Id:
As recent CVE-2023-2861 once again showed, the 9p 'proxy' fs driver is in
bad shape. Using the 'proxy' backend was already discouraged for safety
reasons before and we recommended to use the 'local' backend (preferably
in conjunction with its 'mapped' security model) instead, but now it is
time to
Let's use our new helper. We'll add the subregion to system RAM now
earlier. That shouldn't matter, because the system RAM memory region should
already be alive at that point.
Cc: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
hw/arm/virt.c | 9
Let's use our new helper and stop always allocating ms->device_memory.
Once allcoated, we're sure that the size > 0 and that the base was
initialized.
Adjust the code in pc_memory_init() to check for machine->device_memory
instead of pcmc->has_reserved_memory and machine->device_memory->base.
Essentially a resend with ACKs/RBs. If I don't get any more comments
I'll queue this to my mem-next tree next week.
Working on adding multi-memslot support for virtio-mem (teaching memory
device code about memory devices that can consume multiple memslots), I
have some preparatory cleanups in my
Let's move memory_device_check_addable() and basic checks out of
memory_device_get_free_addr() directly into memory_device_pre_plug().
Separating basic checks from address assignment is cleaner and
prepares for further changes.
As all memory device users now use memory_devices_init(), and that
Let's intrduce a new helper that we will use to replace existing memory
device setup code during machine initialization. We'll enforce that the
size has to be > 0.
Once all machines were converted, we'll only allocate ms->device_memory
if the size > 0.
Reviewed-by: Philippe Mathieu-Daudé
Let's unify the error messages, such that we can simply stop allocating
ms->device_memory if the size would be 0 (and there are no memory
devices ever).
The case of "not supported by the machine" should barely pop up either
way: if the machine doesn't support memory devices, it usually doesn't
Let's avoid iterating over all devices and simply track it in the
DeviceMemoryState.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Hildenbrand
---
hw/mem/memory-device.c | 22 +++---
include/hw/boards.h| 2 ++
2 files changed, 5 insertions(+), 19 deletions(-)
There are no remaining users in the tree. Libvirt never used that
property and a quick internet search revealed no other users.
Further, we renamed that property already in commit f2ffbe2b7dd0
("pc: rename "hotplug memory" terminology to "device memory"") without
anybody complaining.
So let's
Let's use our new helper and stop always allocating ms->device_memory.
There is no difference in common memory-device code anymore between
ms->device_memory being NULL or the size being 0. So we only have to
teach spapr code that ms->device_memory isn't always around.
We can now modify two
Let's use our new helper. While at it, use VIRT_HIGHMEM_BASE.
Cc: Xiaojuan Yang
Cc: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Song Gao
Signed-off-by: David Hildenbrand
---
hw/loongarch/virt.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git
We're already looking at machine->device_memory when calling
build_srat_memory(), so let's simply avoid going via
PC_MACHINE_DEVMEM_REGION_SIZE to get the size and rely on
machine->device_memory directly.
Once machine->device_memory is set, we know that the size > 0. The code now
looks much more
From: Shashi Mallela
Create ITS as part of SBSA platform GIC initialization.
GIC ITS information is in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
Signed-off-by: Shashi Mallela
Signed-off-by: Marcin Juszkiewicz
Message-id:
From: Richard Henderson
Handle GPC Fault types in arm_deliver_fault, reporting as
either a GPC exception at EL3, or falling through to insn
or data aborts at various exception levels.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230620124418.805717-16-richard.hender...@linaro.org
Signed-off-by: Peter
On 6/23/23 11:10, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 09:21, Nicholas Piggin wrote:
ppc has always silently ignored access to real (physical) addresses
with nothing behind it, which can make debugging difficult at times.
It looks like the way to handle this is implement the
From: Richard Henderson
Add input and output space members to S1Translate. Set and adjust
them in S1_ptw_translate, and the various points at which we drop
secure state. Initialize the space in get_phys_addr; for now leave
get_phys_addr_with_secure considering only secure vs non-secure spaces.
From: Richard Henderson
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS,
RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20230620124418.805717-5-richard.hender...@linaro.org
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Message-id: 20230622143046.1578160-1-richard.hender...@linaro.org
[PMM: fixed typo; note experimental status in emulation.rst too]
Signed-off-by: Peter Maydell
---
docs/system/arm/cpu-features.rst | 23
From: Richard Henderson
Add an x-rme cpu property to enable FEAT_RME.
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
for testing various possible configurations.
We're not currently completely sure whether FEAT_RME will
be OK to enable purely as a CPU-level property, or if it will
need
On 22.06.23 22:13, Michael S. Tsirkin wrote:
On Tue, May 30, 2023 at 01:38:28PM +0200, David Hildenbrand wrote:
Working on adding multi-memslot support for virtio-mem (teaching memory
device code about memory devices that can consume multiple memslots), I
have some preparatory cleanups in my
From: Philippe Mathieu-Daudé
Per commit 067109a11c ("docs/devel: mention the spacing requirement
for QOM"):
For a storage structure the first declaration should always be
called “parent_obj” and for a class structure the first member
should always be called “parent_class”
Adapt the QOM
'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k
into staging (2023-06-22 10:18:32 +0200)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230623
for you to fetch changes up
From: Richard Henderson
While Root and Realm may read and write data from other spaces,
neither may execute from other pa spaces.
This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
The xkb official name for the Arabic keyboard layout is 'ara'.
However xkb has for at least the past 15 years also permitted it to
be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
synoynm was removed, which breaks compilation of QEMU:
FAILED: pc-bios/keymaps/ar
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