On 28/10/23 21:45, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 56 ++--
1 file changed, 38 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Richard,
On 28/10/23 21:45, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 41 +++
1 file changed, 41 insertions(+)
@@ -1053,6 +1071,14 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond
cond, TCGReg
On Fri Nov 17, 2023 at 3:39 AM AEST, Alex Bennée wrote:
> The reason the ppc64 and s390x test where failing was because gdb
> hides them although they are still accessible via regnum. We can
> re-arrange the test a little bit and include these two arches in our
> test.
>
> We still don't
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a
From: Zhuocheng Ding
As module-level topology support is added to X86CPU, now we can enable
the support for the cluster parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,clusters=*,cores=*,threads=*.
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "clusters" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the
module level width in APIC ID, which can be calculated by
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
Reviewed-by: Yanan Wang
Tested-by: Babu Moger
Tested-by: Yongwei Ma
Acked-by: Michael S. Tsirkin
From: Zhuocheng Ding
Introduce cluster-id other than module-id to be consistent with
CpuInstanceProperties.cluster-id, and this avoids the confusion
of parameter names when hotplugging.
Following the legacy smp check rules, also add the cluster_id validity
into x86_cpu_pre_plug().
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]:
The number of
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
And since maximum_processor_id (original
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf
with
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone
to confusion and
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using APIC ID offset (like L3 topology
From: Zhuocheng Ding
smp command has the "clusters" parameter but x86 hasn't supported that
level. "cluster" is a CPU topology level concept above cores, in which
the cores may share some resources (L2 cache or some others like L3
cache tags, depending on the Archs) [1][2]. For x86, the resource
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology
From: Zhuocheng Ding
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are
completed.
module_id can be
From: Zhao Liu
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core, but is
-Original Message-
From: Nabih Estefan
Sent: Saturday, October 28, 2023 1:55 AM
To: peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing
; wuhao...@google.com; jasonw...@redhat.com; IS20 Avi
Fishman ; nabiheste...@google.com; CS20 KWLiu
; IS20 Tomer
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
enumeration values.
Though
From: Zhao Liu
Hi list,
This is the our v6 patch series, rebased on the master branch at the
commit 34a5cb6d8434 (Merge tag 'pull-tcg-20231114' of
https://gitlab.com/rth7680/qemu into staging).
Because the first four patches of v5 [1] have been merged, v6 contains
the remaining patches and
On Fri Nov 17, 2023 at 4:11 AM AEST, Thomas Huth wrote:
> On 16/11/2023 12.53, Nicholas Piggin wrote:
> > Let's try enable reverse_debugging.py in gitlab CI.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> > Maybe we could try this again at some point? The bug might have been
> > noticed
Hello everyone! I am working on implementing a tool to assess the
complexity of CPU architecture porting. It primarily focuses on RISC-V
architecture porting. In fact, the tool may have an average estimate of various
architecture porting efforts.My focus is on the overall workload and
On 17/11/23 00:26, Gavin Shan wrote:
Hi Phil,
On 11/17/23 02:20, Philippe Mathieu-Daudé wrote:
On 16/11/23 14:35, Philippe Mathieu-Daudé wrote:
I'm queuing patches 1-3 & 5-23 to my cpus-next tree. No need to
repost them, please base them on my tree. I'll follow up with the
branch link when I
The 'stm32vldiscovery' machine ignores the CPU type requested by
the command line. This might confuse users, since the following
will create a machine with a Cortex-M3 CPU:
$ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1
Set the MachineClass::valid_cpu_types field (introduced in
From: Gavin Shan
Constify MachineClass::valid_cpu_types[i], as suggested by Richard
Henderson.
Suggested-by: Richard Henderson
Signed-off-by: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[PMD: Constify HPPA machines,
restrict valid_cpu_types to
Series fully reviewed.
Hi,
While reviewing this [*] series from Arnaud and Inès,
I realized STM32 based boards don't check the requested
CPU type is correct, and ignore it. Possibly confusing
users.
Since these simple boards code is used as template,
I took the opportunity to sanitize it a bit,
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
CPU type requested by the command line. This might confuse users,
since the following will create a machine with a Cortex-M4 CPU:
$ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
Set the MachineClass::valid_cpu_types field
The 'netduino2' machine ignores the CPU type requested by the
command line. This might confuse users, since the following will
create a machine with a Cortex-M3 CPU:
$ qemu-system-arm -M netduino2 -cpu cortex-a9
Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48
See commit 9ba1caf510 ("MAINTAINERS: Mark the Nios II CPU as orphan"),
last contribution from Chris was in 2012 [1] and Marek in 2018 [2].
[1]
https://lore.kernel.org/qemu-devel/1352607539-10455-2-git-send-email-crwu...@gmail.com/
[2]
On 2023/11/17 下午2:35, Cédric Le Goater wrote:
Hello,
On 11/17/23 02:14, maobibo wrote:
Thomas,
Linux 6.7-rc1 has already released, LoongArch KVM is supported in this
version. LoongArch qemu KVM function depends on linux-headers and I do
not know whether LoongArch qemu KVM can be merged
On 17/11/2023 02.14, maobibo wrote:
Thomas,
Linux 6.7-rc1 has already released, LoongArch KVM is supported in this
version. LoongArch qemu KVM function depends on linux-headers and I do not
know whether LoongArch qemu KVM can be merged in 8.2 cycle.
QEMU is in hard freeze now, see:
Hello,
On 11/17/23 02:14, maobibo wrote:
Thomas,
Linux 6.7-rc1 has already released, LoongArch KVM is supported in this version.
LoongArch qemu KVM function depends on linux-headers and I do not know whether
LoongArch qemu KVM can be merged in 8.2 cycle.
It's too late for 8.2. See
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Thursday, November 16, 2023 1:19 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.ng
> Subject: RE: [RFC
The KVM_ARM_VCPU_PMU_V3_FILTER provide the ability to let the VMM decide
which PMU events are provided to the guest. Add a new option
`pmu-filter` as -accel sub-option to set the PMU Event Filtering.
The `pmu-filter` has such format:
pmu-filter="{A,D}:start-end[;{A,D}:start-end...]"
The A
-Original Message-
From: Nabih Estefan
Sent: Saturday, October 28, 2023 1:55 AM
To: peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing
; wuhao...@google.com; jasonw...@redhat.com; IS20 Avi
Fishman ; nabiheste...@google.com; CS20 KWLiu
; IS20 Tomer
On 2023/11/16 22:19, Juan Quintela wrote:
Zongmin Zhou wrote:
Since socket_parse() will allocate memory for 'saddr',and its value
will pass to 'addr' that allocated by migrate_uri_parse(),
then 'saddr' will no longer used,need to free.
But due to 'saddr->u' is shallow copying the contents of
At present qemu creates a device tree automatically with the 'virt' generic
virtual platform. This is very convenient in most cases but there is not
much control over what is generated.
Add a way to provide a device tree binary file with additional properties
to add before booting. This provides
On Fri, Nov 17, 2023 at 12:49 AM David Woodhouse wrote:
>
> On Tue, 2023-11-14 at 11:09 +0800, Jason Wang wrote:
> > The following changes since commit 69680740eafa1838527c90155a7432d51b8ff203:
> >
> > Merge tag 'qdev-array-prop' of https://repo.or.cz/qemu/kevin into staging
> > (2023-11-11
-Original Message-
From: Nabih Estefan
Sent: Saturday, October 28, 2023 1:55 AM
To: peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; CS20 KFTing
; wuhao...@google.com; jasonw...@redhat.com; IS20 Avi
Fishman ; nabiheste...@google.com; CS20 KWLiu
; IS20 Tomer
-Original Message-
From: CS20 KFTing
Sent: Tuesday, November 14, 2023 4:56 PM
To: Nabih Estefan ; peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; wuhao...@google.com;
jasonw...@redhat.com; IS20 Avi Fishman ; CS20 KWLiu
; IS20 Tomer Maimon ; IN20 Hila
-Original Message-
From: CS20 KFTing
Sent: Tuesday, November 14, 2023 1:14 PM
To: Nabih Estefan ; peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; wuhao...@google.com;
jasonw...@redhat.com; IS20 Avi Fishman ; CS20 KWLiu
; IS20 Tomer Maimon ; IN20 Hila
-Original Message-
From: CS20 KFTing
Sent: Tuesday, November 14, 2023 9:24 AM
To: Nabih Estefan ; peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; wuhao...@google.com;
jasonw...@redhat.com; IS20 Avi Fishman ; CS20 KWLiu
; IS20 Tomer Maimon ; IN20 Hila
-Original Message-
From: CS20 KFTing
Sent: Monday, November 13, 2023 11:49 AM
To: Nabih Estefan ; peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; wuhao...@google.com;
jasonw...@redhat.com; IS20 Avi Fishman ; CS20 KWLiu
; IS20 Tomer Maimon ; IN20 Hila
-Original Message-
From: CS20 KFTing
Sent: Monday, November 13, 2023 10:23 AM
To: Nabih Estefan ; peter.mayd...@linaro.org
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; wuhao...@google.com;
jasonw...@redhat.com; IS20 Avi Fishman ; CS20 KWLiu
; IS20 Tomer Maimon ; IN20 Hila
-Original Message-
From: Peter Maydell
Sent: Friday, November 17, 2023 12:25 AM
To: CS20 KFTing
Cc: Nabih Estefan ; qemu-...@nongnu.org;
qemu-devel@nongnu.org; wuhao...@google.com; IS20 Avi Fishman
; CS20 KWLiu ; IS20 Tomer Maimon
; IN20 Hila Miranda-Kuzi
Subject: Re: [PATCH v5
Thomas,
Linux 6.7-rc1 has already released, LoongArch KVM is supported in this
version. LoongArch qemu KVM function depends on linux-headers and I do
not know whether LoongArch qemu KVM can be merged in 8.2 cycle.
Regards
Bibo Mao
On 2023/11/16 下午9:19, Thomas Huth wrote:
On 15/11/2023
On 11/16/23 09:52, Peter Maydell wrote:
On Tue, 7 Nov 2023 at 10:24, wrote:
From: Marc-André Lureau
If a display is backed by a specialized VC, allow to override the
default "vc:80Cx24C".
As suggested by Paolo, if the display doesn't implement a VC (get_vc()
returns NULL), use a fallback
-mem2,num-dc-regions=2,nonvolatile-dc-memdev=cxl-dc-mem2,id=cxl-dev2,lsa=cxl-lsa2,sn=2
-device
cxl-type3,bus=hb1rp1,memdev=cxl-mem3,num-dc-regions=2,nonvolatile-dc-memdev=cxl-dc-mem3,id=cxl-dev3,lsa=cxl-lsa3,sn=3
...
Ira
[1]
https://lore.kernel.org/all/20231116-fix-cdat-devm-free-v1-1-b148b4070.
Hi Phil,
On 11/17/23 02:20, Philippe Mathieu-Daudé wrote:
On 16/11/23 14:35, Philippe Mathieu-Daudé wrote:
I'm queuing patches 1-3 & 5-23 to my cpus-next tree. No need to
repost them, please base them on my tree. I'll follow up with the
branch link when I finish my testing and push it.
Here
Hi Phil,
On 11/17/23 02:08, Philippe Mathieu-Daudé wrote:
On 15/11/23 00:56, Gavin Shan wrote:
From: Philippe Mathieu-Daudé
For all targets, the CPU class returned from CPUClass::class_by_name()
and object_class_dynamic_cast(oc, CPU_RESOLVING_TYPE) need to be
compatible. Lets apply the check
On Wed, 2023-11-15 at 23:34 +0100, Cédric Le Goater wrote:
> On 11/15/23 17:37, Miles Glenn wrote:
> > On Wed, 2023-11-15 at 08:28 +0100, Cédric Le Goater wrote:
> > > On 11/14/23 20:56, Glenn Miles wrote:
> > > > The Power Hypervisor code expects to see a pca9552 device
> > > > connected
> > > >
On Thu, 16 Nov 2023, Kevin Wolf wrote:
Am 16.11.2023 um 11:33 hat Mark Cave-Ayland geschrieben:
This series adds a simple implementation of legacy/native mode switching for PCI
IDE controllers and updates the via-ide device to use it.
The approach I take here is to add a new
> -Original Message-
> From: Brian Cain
> Sent: Thursday, November 16, 2023 10:25 AM
> To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid
> Manning ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng
> Subject: RE: [RFC
On 16 November 2023 13:22:28 GMT-05:00, Peter Maydell
wrote:
>This reverts commit 1bec1cc0da497e55c16e2a7b50f94cdb2a02197f. This
>commit changed the behaviour of the "-display none" option, so that
>it now creates a QEMU monitor on the terminal. "-display none"
>should not be tangled up with
I believe you forgot to add your Signed-off-by tag. Without it we can't accept
the patch hehe
Since you'll need to send another version with the S-o-b, please change the
commit
title to
"riscv: Fix SiFive E CLINT clock frequency"
That way other people will quickly identify which sub-tree this
Hi Eric,
Eric Blake 于2023年10月30日周一 22:53写道：
>
> On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> > To configure the zoned format feature on the qcow2 driver, it
> > requires settings as: the device size, zone model, zone size,
> > zone capacity, number of conventional zones, limits on
This reverts commit 1bec1cc0da497e55c16e2a7b50f94cdb2a02197f. This
commit changed the behaviour of the "-display none" option, so that
it now creates a QEMU monitor on the terminal. "-display none"
should not be tangled up with whether we create a monitor or a serial
terminal; it should purely
Juan Quintela writes:
> Peter Xu wrote:
>> On Thu, Nov 09, 2023 at 01:58:56PM -0300, Fabiano Rosas wrote:
>>> We cannot operate on the multifd semaphores outside of the multifd
>>> channel thread
>>> because multifd_save_cleanup() can run in parallel and
>>> attempt to destroy the mutexes,
On 16/11/2023 12.53, Nicholas Piggin wrote:
Let's try enable reverse_debugging.py in gitlab CI.
Signed-off-by: Nicholas Piggin
---
Maybe we could try this again at some point? The bug might have been
noticed sooner.
They only take a couple of seconds to run so should not take too much
It's failing very often, so don't run this by default anymore
until it gets fixed.
Message-ID: <20231114153019.295131-1-th...@redhat.com>
Reviewed-by: Peter Maydell
Signed-off-by: Thomas Huth
---
tests/avocado/replay_kernel.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Philippe Mathieu-Daudé
In a perfect world we'd have reproducible tests,
but then we'd be sure we run the same binaries.
If a binary artifact isn't hashed, we have no idea
what we are running. Therefore enforce hashing for
all our artifacts.
With this change, unhashed artifacts produce:
From: Nicholas Piggin
Let's try enable reverse_debugging.py in gitlab CI.
Signed-off-by: Nicholas Piggin
Message-ID: <20231116115354.228678-3-npig...@gmail.com>
Signed-off-by: Thomas Huth
---
tests/avocado/reverse_debugging.py | 7 ---
1 file changed, 7 deletions(-)
diff --git
assertEquals() has been removed in Python 3.12 and should be replaced by
assertEqual(). See: https://docs.python.org/3.12/whatsnew/3.12.html#id3
Message-ID: <20231114134326.287242-1-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
docs/devel/testing.rst
The "edid" feature has been added to vhost-user-gpu in commit
c06444261e20 ("contrib/vhost-user-gpu: implement get_edid feature"),
so waiting for "features: +virgl -edid" in the test does not work
anymore, it's "+edid" instead of "-edid" now!
While we're at it, move the expected string to the
The intel_iommu test is currently succeeding with annoying warnings.
Add the proper asset hashes to avoid those.
Message-ID: <20231114143531.291820-1-th...@redhat.com>
Reviewed-by: Eric Auger
Signed-off-by: Thomas Huth
---
tests/avocado/intel_iommu.py | 6 --
1 file changed, 4
From: Nicholas Piggin
Like replay_linux.py, reverse_debugging.py starts the vm with console
set but does not interact with it (e.g., with wait_for_console_pattern).
In this situation, the console should have a drainer attached so the
socket does not fill. replay_linux.py has a drainer, but it is
assertEquals() has been removed in Python 3.12 and should be replaced by
assertEqual(). See: https://docs.python.org/3.12/whatsnew/3.12.html#id3
Message-ID: <20231116061956.14676-1-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Ani Sinha
Signed-off-by: Thomas Huth
---
The multiprocess test is currently succeeding with an annoying warning:
(1/2) tests/avocado/multiprocess.py:Multiprocess.test_multiprocess_x86_64:
WARN: Test passed but there were warnings during execution. Check
the log for details
In the log, you can find an entry like:
WARNI|
From: Philippe Mathieu-Daudé
assertRegexpMatches() has been removed in Python 3.12 and should be replaced by
assertRegex(). See: https://docs.python.org/3.12/whatsnew/3.12.html#id3
Inspired-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Message-ID:
The following changes since commit 34a5cb6d8434303c170230644b2a7c1d5781d197:
Merge tag 'pull-tcg-20231114' of https://gitlab.com/rth7680/qemu into staging
(2023-11-15 08:05:25 -0500)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2023-11-16
for
Markus Armbruster 于2023年11月3日周五 17:08写道：
>
> Eric Blake writes:
>
> > On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> >> To configure the zoned format feature on the qcow2 driver, it
> >> requires settings as: the device size, zone model, zone size,
> >> zone capacity, number of
Stefan Hajnoczi 于2023年11月3日周五 11:24写道：
>
> On Mon, Oct 30, 2023 at 08:18:45PM +0800, Sam Li wrote:
> > +typedef struct Qcow2ZoneListEntry {
> > +QLIST_ENTRY(Qcow2ZoneListEntry) exp_open_zone_entry;
> > +QLIST_ENTRY(Qcow2ZoneListEntry) imp_open_zone_entry;
> > +
On 16/11/2023 14.24, Daniel P. Berrangé wrote:
On Thu, Nov 16, 2023 at 02:14:54PM +0100, Thomas Huth wrote:
QOM names currently don't have any enforced naming rules. This
can be problematic, e.g. when they are used on the command line
for the "-device" option (where the comma is used to
On Tue, 7 Nov 2023 at 10:24, wrote:
>
> From: Marc-André Lureau
>
> If a display is backed by a specialized VC, allow to override the
> default "vc:80Cx24C".
>
> As suggested by Paolo, if the display doesn't implement a VC (get_vc()
> returns NULL), use a fallback that will use a muxed console
On Thu, Nov 16, 2023 at 05:28:20PM +, Alex Bennée wrote:
> As 32 bit x86 become rarer we are starting to run into problems with
> search paths. Although we switched to a Debian container we still
> favour the native CC on a Bookworm host. As a result we have a broken
> cross compile setup
Hi,
I haven't written here in a while :) but I have something small that I
would like to discuss.
Using qemu-img to convert an image and writing the result directly to
stdout is a question that has already been raised in the past (see
[1] for an example) and it's clear that it's generally not
The reason the ppc64 and s390x test where failing was because gdb
hides them although they are still accessible via regnum. We can
re-arrange the test a little bit and include these two arches in our
test.
We still don't explicitly fail for registers that just disappear like
in the ARM case:
As 32 bit x86 become rarer we are starting to run into problems with
search paths. Although we switched to a Debian container we still
favour the native CC on a Bookworm host. As a result we have a broken
cross compile setup which then fails to build with:
BUILD i386-linux-user guest-tests
The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from
ic{c,v}_fullprio_mask should technically also remove any
bit above 7 as these are marked reserved (read 0) and should
therefore should not be written as anything other than 0.
This was noted during a run of a proprietary test system and
Hi Philippe,
On 2023-11-16 16:44, Philippe Mathieu-Daudé wrote:
Hi Francisco,
On 16/11/23 15:17, Francisco Iglesias wrote:
Hi Philippe, good catch!
Well this was fuzzed by Qiang Liu.
On 2023-11-15 16:17, Philippe Mathieu-Daudé wrote:
Per
On 11/16/2023 10:14 AM, Markus Armbruster wrote:
> Steven Sistare writes:
>> On 11/15/2023 11:15 AM, Markus Armbruster wrote:
>>> Steven Sistare writes:
On 11/15/2023 3:41 AM, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
>> On Fri, Nov 03, 2023 at 03:51:00PM -0400,
On Thu, 2023-11-09 at 11:45 +, David Woodhouse wrote:
> On Thu, 2023-11-09 at 19:34 +0800, Stefan Hajnoczi wrote:
> > On Thu, 9 Nov 2023 at 19:10, David Woodhouse wrote:
> > >
> > > On Tue, 2023-11-07 at 14:15 +0400, marcandre.lur...@redhat.com wrote:
> > > > From: Marc-André Lureau
> > > >
On 11/16/23 08:37, Philippe Mathieu-Daudé wrote:
Add a helper to return a machine default CPU type.
If this machine is restricted to a single CPU type,
use it as default, obviously.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/boards.h | 6 ++
hw/core/machine.c | 8
On Tue, 2023-11-14 at 11:09 +0800, Jason Wang wrote:
> The following changes since commit 69680740eafa1838527c90155a7432d51b8ff203:
>
> Merge tag 'qdev-array-prop' of https://repo.or.cz/qemu/kevin into staging
> (2023-11-11 11:23:25 +0800)
>
> are available in the git repository at:
>
>
On 11/15/23 15:21, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (6):
hw/arm/stm32f405: Report error when incorrect CPU is used
hw/arm/stm32f205: Report error when incorrect CPU is used
hw/arm/stm32f100: Report error when incorrect CPU is used
hw/arm/msf2: Simplify setting
On Tue, 14 Nov 2023 at 17:23, Ben Dooks wrote:
>
> On 14/11/2023 17:14, Peter Maydell wrote:
> > On Tue, 14 Nov 2023 at 16:54, Ben Dooks wrote:
> >>
> >> The ICC_PMR_ELx bit msak returned from icc_fullprio_mask
> >> should technically also remove any bit above 7 as these
> >> are marked reserved
Add a helper to return a machine default CPU type.
If this machine is restricted to a single CPU type,
use it as default, obviously.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/boards.h | 6 ++
hw/core/machine.c | 8
system/vl.c | 2 +-
3 files changed, 15
Using direct pointer dereferencing can allow for unaligned accesses,
which was seen during execution with sanitizers enabled.
Reviewed-by: Chris Rauer
Reviewed-by: Peter Foley
Signed-off-by: Patrick Venture
Cc: qemu-sta...@nongnu.org
---
v2: changed commit mesage to be more accurate and
On Wed, 15 Nov 2023 at 01:35, kft...@nuvoton.com wrote:
> Peter Maydell wrote:
> On Tue, 14 Nov 2023 at 01:24, kft...@nuvoton.com wrote:
> > Signed-off-by: Tyrone Ting
>
> Hi; can you clarify what you mean with this Signed-off-by: tag?
> Generally we use those where either you're the author of
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Wednesday, November 15, 2023 4:03 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.ng
> Subject: RE: [RFC
On 16/11/23 14:35, Philippe Mathieu-Daudé wrote:
Hi Gavin,
On 15/11/23 00:55, Gavin Shan wrote:
There are two places where the user specified CPU type is checked to see
if it's supported or allowed by the board: machine_run_board_init() and
mc->init(). We don't have to maintain two duplicate
On 15/11/23 00:56, Gavin Shan wrote:
From: Philippe Mathieu-Daudé
For all targets, the CPU class returned from CPUClass::class_by_name()
and object_class_dynamic_cast(oc, CPU_RESOLVING_TYPE) need to be
compatible. Lets apply the check in cpu_class_by_name() for once,
instead of having the
Fabiano Rosas wrote:
> This is being shadowed but the assignments at
> multifd_channel_connect() and multifd_tls_channel_connect() .
>
> Signed-off-by: Fabiano Rosas
Reviewed-by: Juan Quintela
Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
>> Peter Xu writes:
>>
>>> On Thu, Nov 09, 2023 at 01:58:56PM -0300, Fabiano Rosas wrote:
>> I think we historically stumbled upon the fact that qemu_thread_join()
>> is not the same as pthread_join(). The former takes a pointer and is not
>> safe
Richard Henderson wrote:
> On 11/9/23 11:28, Philippe Mathieu-Daudé wrote:
>> @@ -436,6 +438,24 @@ static const VMStateDescription vmstate_pl011_clock = {
>> }
>> };
>> +static bool pl011_xmit_fifo_state_needed(void *opaque)
>> +{
>> +PL011State* s = opaque;
>> +
>> +return
On 16/11/23 14:14, Thomas Huth wrote:
Type names should not contain special characters like ":" (so that
they are easier to use with QAPI and other parts). We are going to
forbid such names in an upcoming patch. Thus let's replace the ":"
here with a "-".
Signed-off-by: Thomas Huth
---
On 16/11/23 14:14, Thomas Huth wrote:
Type names should not contain special characters like ":". Let's
remove the whole prefix here since it does not really seem to be
helpful to have such a prefix here. The type name is only used
internally for an interface, so the renaming should not affect
Fabiano Rosas wrote:
> Peter Xu writes:
>
>> On Thu, Nov 09, 2023 at 01:58:56PM -0300, Fabiano Rosas wrote:
>>> We cannot operate on the multifd semaphores outside of the multifd
>>> channel thread
>>> because multifd_save_cleanup() can run in parallel and
>>> attempt to destroy the mutexes,
Hi Francisco,
On 16/11/23 15:17, Francisco Iglesias wrote:
Hi Philippe, good catch!
Well this was fuzzed by Qiang Liu.
On 2023-11-15 16:17, Philippe Mathieu-Daudé wrote:
Per
https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Message-Format
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