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On Tue, Apr 20, 2010 at 05:16:10PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 8:12 AM, Mika Westerberg wrote:
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller
found
in EP93xx chips (EP9301, EP9302, EP9307, EP9312 and EP9315).
Signed-off-by:
On Tue, Apr 20, 2010 at 08:52:26PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 6:10 PM, Martin Guy wrote:
I have noticed on card insertion, the last line of:
mmc0: problem reading switch capabilities, performance might suffer.
mmc0: host does not support reading read-only
On Tue, Apr 20, 2010 at 12:24:26PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 8:12 AM, Mika Westerberg wrote:
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller
found
in EP93xx chips (EP9301, EP9302, EP9307, EP9312 and EP9315).
Signed-off-by:
On Tue, Apr 20, 2010 at 08:52:26PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 6:10 PM, Martin Guy wrote:
Not easily, but it seems a likely cause.
To prevent card deselection mid-message I think we would need to
handle multi-transfer messages by making the start of transfers
On Wed, Apr 21, 2010 at 11:47:13AM -0500, H Hartley Sweeten wrote:
On Wednesday, April 21, 2010 12:16 AM, Mika Westerberg wrote:
I think it is more readable to do:
ep93xx_spi_select_device(espi, msg-spi);
and
ep93xx_spi_deselect_device(espi, msg-spi);
It can be seen from
On Tuesday, April 20, 2010 11:37 PM, Mika Westerberg wrote:
On Tue, Apr 20, 2010 at 05:16:10PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 8:12 AM, Mika Westerberg wrote:
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller
found
in EP93xx chips (EP9301,
On Wednesday, April 21, 2010 3:47 AM, Mika Westerberg wrote:
On Tue, Apr 20, 2010 at 08:52:26PM -0500, H Hartley Sweeten wrote:
On Tuesday, April 20, 2010 6:10 PM, Martin Guy wrote:
Not easily, but it seems a likely cause.
To prevent card deselection mid-message I think we would need to
Mika,
I have added some debug messages to the driver trying to figure out
how to chain the transfers in a message together in order to keep
the SFRM signal asserted for the entire message. I still haven't
worked out a good solution but I did notice something else.
First, every spi transaction,
On Wed, Apr 21, 2010 at 01:00:56PM -0500, H Hartley Sweeten wrote:
Same results are your v4 driver. But, I think your on the right track.
Thanks for testing.
I think the problem is in the ep93xx_spi_read_write routine. That function
returns 0 as long as there is still data left in the
On Wed, Apr 21, 2010 at 09:47:14PM -0500, H Hartley Sweeten wrote:
[...]
First, every spi transaction, including a single byte transfer, is
going to generate at least two interrupts. One when the interrupts
are first enabled because the TX FIFO is empty. And a second when
that byte has been
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