Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng :
>Sometimes EFI GOP support may be not wanted (e.g. because the operating
>system cannot operate well with it) even if video support in U-Boot is
>needed.
Which OS has which problem?
Why don't you fix the OS?
Best regards
Heinrich
>
>Allow
From: wesleywesley
AQA (Admin Queue Attributes) register is a dword size with
lower word of ASQS, and higher word of ACQS.
The code set the variable aqa twice, but it is redundant.
Signed-off-by: wesleywesley
---
drivers/nvme/nvme.c | 1 -
1 file changed, 1 deletion(-)
diff --git
From: wesleywesley
Each prp is 8 bytes, calculate the number of prps
per page should just divide page size by 8
there is no need to minus 1
Signed-off-by: wesleywesley
---
drivers/nvme/nvme.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvme/nvme.c
On Tue, Jun 15, 2021 at 08:38:39PM -0300, Fabio Estevam wrote:
> Re-sync the defconfig by doing:
>
> make smegw01_defconfig
> make savedefconfig
> cp defconfig configs/smegw01_defconfig
>
> Signed-off-by: Fabio Estevam
> ---
> configs/smegw01_defconfig | 2 +-
> 1 file changed, 1
On Tue, Jun 15, 2021 at 08:38:38PM -0300, Fabio Estevam wrote:
> On the Yocto image there is a single partition and the kernel
> and dtb are present in the 'boot' directory.
>
> Change it accordingly so that the board can boot the Yocto
> image by default.
>
> Use the generic 'load' command
On Tue, Jun 15, 2021 at 10:11:43AM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the fix for the Marvell Turris boards:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
From: qianfan Zhao
The address of sun8i_r40's phyctrl is 0x01c13404, also fixed
enable_pmu and dual_route.
Signed-off-by: qianfan Zhao
---
drivers/phy/allwinner/phy-sun4i-usb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
From: qianfan Zhao
bpi-m2u has a hardware usb_otg, let's enable it in dts.
Signed-off-by: qianfan Zhao
---
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 4
arch/arm/dts/sun8i-r40.dtsi | 13 +
2 files changed, 17 insertions(+)
diff --git
From: qianfan Zhao
R40 has 8 user-configurable endpoints and 8KB FIFO for EPs.
Signed-off-by: qianfan Zhao
---
drivers/usb/musb-new/sunxi.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/sunxi.c
From: qianfan Zhao
Since the usb otg driver support R40 device, we enable usb gadget
functions and ums.
Signed-off-by: qianfan Zhao
---
configs/Bananapi_M2_Ultra_defconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/Bananapi_M2_Ultra_defconfig
Fix typo in clock-snapdragon.c
Signed-off-by: Sheep Sun
---
arch/arm/mach-snapdragon/clock-snapdragon.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c
b/arch/arm/mach-snapdragon/clock-snapdragon.c
index
On Fri, Jun 11, 2021 at 12:16:16PM +0800, Sean Anderson wrote:
> Now that the k210 clock driver does not depend on CCF, we should no longer
> imply it (and probably should not have in the first place). We can also
> reduce the pre-relocation malloc arena back to something sensible.
>
>
On Fri, Jun 11, 2021 at 12:16:15PM +0800, Sean Anderson wrote:
> Linux has had some stability issues when using AISRAM with a different
> frequency from SRAM. Mirror their change here now that we relocate into
> AISRAM.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v3:
> - Add
On Fri, Jun 11, 2021 at 12:16:14PM +0800, Sean Anderson wrote:
> Now that we have only one clock driver, we don't need to have our own
> subdirectory. Move the driver back with the rest of the clock drivers.
>
> The MAINTAINERS for kendryte pinctrl is also fixed since it has always been
> wrong.
On Fri, Jun 11, 2021 at 12:16:13PM +0800, Sean Anderson wrote:
> This driver no longer serves a purpose now that we have moved away from
> CCF. Drop it.
>
> Signed-off-by: Sean Anderson
> ---
>
> (no changes since v1)
>
> drivers/clk/kendryte/Makefile | 2 +-
> drivers/clk/kendryte/bypass.c
On Fri, Jun 11, 2021 at 12:16:12PM +0800, Sean Anderson wrote:
> This speeds up boot by preventing multiple reconfigurations of the PLLs.
>
> Signed-off-by: Sean Anderson
> ---
>
> (no changes since v1)
>
> drivers/clk/kendryte/clk.c | 15 ---
> 1 file changed, 8 insertions(+), 7
On Fri, Jun 11, 2021 at 12:16:11PM +0800, Sean Anderson wrote:
> This adds support for setting clock rates, which was left out of the
> initial CCF expunging. There are several tricky bits here, mostly related
> to the PLLS:
>
> * The PLL's bypass is broken. If the PLL is reconfigured, any child
On Fri, Jun 11, 2021 at 12:16:10PM +0800, Sean Anderson wrote:
> Since we are no longer using CCF we cannot use the default soc_clk_dump.
> Instead, implement our own.
>
> Signed-off-by: Sean Anderson
> ---
>
> (no changes since v1)
>
> drivers/clk/kendryte/clk.c | 68
On Fri, Jun 11, 2021 at 12:16:09PM +0800, Sean Anderson wrote:
> Now that there no separate PLL driver, we can no longer make the PLL
> functions static. By moving the PLL driver in with the rest of the clock
> code, we can make these functions static again. We still keep the pll
> header for unit
On Fri, Jun 11, 2021 at 12:16:08PM +0800, Sean Anderson wrote:
> This is effectively a complete rewrite to remove all dependency on CCF.
> The code is now smaller, and so is the binary. It also takes up less memory
> at runtime (since we don't have to create 40 udevices). In general, I am
> much
On Wed, Jun 16, 2021 at 12:34:14AM +0800, Dimitri John Ledkov wrote:
> Set default fdtfile names for unleashed and unmatched boards, as used
> in the upstream Linux kernel. This allows sysboot command to find and
> load appropriate dtb for the matching kernel from universal stock
> Ubuntu RISCV
On Mai 27 2021, Green Wan wrote:
> +/* List of clock controls provided by the PRCI */
> +struct __prci_clock __prci_init_clocks_fu740[] = {
> + [PRCI_CLK_COREPLL] = {
> + .name = "corepll",
> + .parent_name = "hfclk",
> + .ops = _fu740_prci_wrpll_clk_ops,
>
Select the CMD_UNZIP option so that the 'gzwrite' command
can be used to flash .gz image into the eMMC.
Signed-off-by: Fabio Estevam
---
configs/smegw01_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index
Re-sync the defconfig by doing:
make smegw01_defconfig
make savedefconfig
cp defconfig configs/smegw01_defconfig
Signed-off-by: Fabio Estevam
---
configs/smegw01_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
On the Yocto image there is a single partition and the kernel
and dtb are present in the 'boot' directory.
Change it accordingly so that the board can boot the Yocto
image by default.
Use the generic 'load' command instead, which is able to
read from an ext4 partition.
Signed-off-by: Fabio
A gentle ping.
What is the current review status?
Who will take care of this patch?
-Takahiro Akashi
On Mon, May 24, 2021 at 03:23:17PM -0500, Alexandru Gagniuc wrote:
> Host tool features, such as mkimage's ability to sign FIT images were
> enabled or disabled based on the target configuration.
Sometimes EFI GOP support may be not wanted (e.g. because the operating
system cannot operate well with it) even if video support in U-Boot is
needed.
Allow to disable EFI GOP support with a Kconfig option.
Signed-off-by: Icenowy Zheng
---
lib/efi_loader/Kconfig | 8
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main
From: Chris Morgan
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Additionally, a possible errata was found
From: Chris Morgan
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan
---
From: Chris Morgan
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/dts/px30.dtsi | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index
From: Chris Morgan
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/px30/px30.c | 64 ++
1 file changed, 64 insertions(+)
diff --git
From: Chris Morgan
Changes from v3:
- Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
driver to fix potential issue on hardware. Note I never noticed
this issue while testing, so I cannot test if it fixed any specific
issue for me.
- Updated of-compatible string
Set default fdtfile names for unleashed and unmatched boards, as used
in the upstream Linux kernel. This allows sysboot command to find and
load appropriate dtb for the matching kernel from universal stock
Ubuntu RISCV rootfs images based on fdtdir setting in extlinux.conf.
Signed-off-by: Dimitri
Hi, this patch is still not pulled into master. It still applies
cleanly onto master.
Can this patch please be pulled in? It fixes a crash of uboot.
Without this patch upstream, people who build their own uboot cannot
boot stock Ubuntu images.
What can I do, for this patch to be applied?
On
On Fri, Jun 04, 2021 at 01:51:12PM +0800, Bin Meng wrote:
> All the device nodes that refer to plic0 as their interrupt parent
> have 2 cells encoded in their interrupts property, but plic0 only
> provides 1 cell in #interrupt-cells which is incorrect.
>
> Signed-off-by: Bin Meng
> ---
>
>
On Fri, Jun 04, 2021 at 01:51:11PM +0800, Bin Meng wrote:
> PLIC nodes don't have child nodes, so #address-cells is not needed.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 --
> arch/riscv/dts/ae350_64.dts | 2 --
> 2 files changed, 4 deletions(-)
Reviewed-by: Leo
On Fri, Jun 04, 2021 at 01:51:10PM +0800, Bin Meng wrote:
> There are two spaces before "debug' in bootargs. Drop one.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 +-
> arch/riscv/dts/ae350_64.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware
Earlier, the region 0x701C to 0x701D was firewalled off because of
a bug in SYSFW. In the v2021.05 release of SYSFW this bug has been fixed
and this region can now be used for other allocations.
Therefore, move TF-A's load address to 0x701C4000 and update its location
in the device tree
The following series of patches,
- Update the location of TF-A
- Indicate reserved locations for DMSC code and secure proxy
Aswath Govindraju (2):
configs: am64x_evm_a53_defconfig: Move TF-A load address to 0x701c4000
arm: dts: k3-am64-main: Indicate the memory reserved for DMSC-lite
On 6/15/21 1:21 PM, Zhengxun Li wrote:
> Hi Michal,
>
> Sean Anderson 於 2021年6月11日 週五 下午3:07寫道：
>>
>>
>>
>> On 6/11/21 11:10 AM, Zhengxun wrote:
>> > Add the devicetree binding for the xilinx clocking wizard.
>> >
>> > Signed-off-by: Zhengxun
>> > ---
>> >
On Tue, Jun 15, 2021 at 10:45 AM wrote:
>
> From: weichangzheng
>
> This adds platform code and the device tree for the Phytium Pomelo Board.
> The initial support comprises the UART and the PCIE.
>
> Signed-off-by: weichangzheng
> ---
> arch/arm/Kconfig | 8 ++
>
On Tue, Jun 15, 2021 at 05:44:35PM +0800, nicholas_zh...@outlook.com wrote:
> From: weichangzheng
>
> This adds platform code and the device tree for the Phytium Pomelo Board.
> The initial support comprises the UART and the PCIE.
>
> Signed-off-by: weichangzheng
This looks better, thanks.
On Tue, Jun 15, 2021 at 08:40:30AM +0300, Ivaylo Dimitrov wrote:
> Hi,
>
> On 22.05.21 г. 0:36 ч., Pali Rohár wrote:
> > On Friday 21 May 2021 10:44:18 Tom Rini wrote:
> > > On Wed, May 19, 2021 at 11:52:03AM -0400, Tom Rini wrote:
> > > > On Wed, May 19, 2021 at 03:27:48PM +0200, Pali Rohár
This information will be maintained in the device tree instead.
Signed-off-by: Anders Dellien
Change-Id: I279399d4a0ea1a3330de5b58e8c9af78e48ba04c
---
configs/total_compute_defconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/total_compute_defconfig
When printing full help output from patman, we should be able to handle
a PAGER variable which includes arguments, e.g. PAGER='less -F'.
Signed-off-by: Paul Barker
---
tools/patman/main.py | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tools/patman/main.py
From: weichangzheng
This adds platform code and the device tree for the Phytium Pomelo Board.
The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng
---
arch/arm/Kconfig | 8 ++
arch/arm/dts/Makefile| 1 +
Hi,
On 22.05.21 г. 0:36 ч., Pali Rohár wrote:
On Friday 21 May 2021 10:44:18 Tom Rini wrote:
On Wed, May 19, 2021 at 11:52:03AM -0400, Tom Rini wrote:
On Wed, May 19, 2021 at 03:27:48PM +0200, Pali Rohár wrote:
On Tuesday 18 May 2021 21:26:40 Tom Rini wrote:
This board has not been
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by:
This commit add support to FriendlyARM ZeroPi board.
Board Schematic:
http://wiki.friendlyarm.com/wiki/images/7/71/ZeroPi_20190731_Schematic.pdf
- v1
. fix trailing whitespace
Yu-Tung Chang (1):
sunxi: h3: Add initial ZeroPi support
arch/arm/dts/Makefile| 3 +-
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by:
This commit adds support to FriendlyARM ZeroPi board.
Board Schematic:
http://wiki.friendlyarm.com/wiki/images/7/71/ZeroPi_20190731_Schematic.pdf
- v1
. fix trailing whitespace
Yu-Tung Chang (1):
sunxi: h3: Add initial ZeroPi support
arch/arm/dts/Makefile| 3 +-
Hi Anders,
Looks good to me.
On 15/06/2021 11:28, Anders Dellien wrote:
This information will be maintained in the device tree instead.
Signed-off-by: Anders Dellien
Change-Id: I279399d4a0ea1a3330de5b58e8c9af78e48ba04c
---
configs/total_compute_defconfig | 3 +--
1 file changed, 1
Hi Michal,
Sean Anderson 於 2021年6月11日 週五 下午3:07寫道：
>
>
>
> On 6/11/21 11:10 AM, Zhengxun wrote:
> > Add the devicetree binding for the xilinx clocking wizard.
> >
> > Signed-off-by: Zhengxun
> > ---
> > .../clock/xlnx,clocking-wizard.txt| 43 +++
> > 1 file
From: litchipi
Fix mmc_rpmb_route_frames() implementation to comply with most MMC
drivers that expect some alignment of MMC data frames in memory.
When called from drivers/tee/optee/rpmb.c, the address passed is not
aligned properly. OP-TEE OS inserts a 6-byte header before a raw RPMB
frame
Hi Timorthee,
On 6/15/21 4:29 PM, Timothée Cercueil wrote:
> From: litchipi
>
Could you change to subject as "mmc: rpmb: fix "?
> Fix mmc_rpmb_route_frames() implementation to comply with most MMC
> drivers that expect some alignment of MMC data frames in memory.
>
> When called from
[...]
> > > > > Yes.
> > > > > We may have different *firmware* for different software components
> > > > > and different devices. For example,
> > > > > You have firmare like U-Boot binary and default variable storage
> > > > > in different partitions.
> > > > > On the other hand, you have an
Hi Tom,
please pull the fix for the Marvell Turris boards:
- Turris: Fix bootcmd_rescue (Pali)
Here the Azure build without any issues:
On 14.06.21 16:45, Marek Behún wrote:
From: Pali Rohár
One of the points of putting the rescue boot command into default
environment is that user can invoke it without physical access to the
board (without having to press the factory reset button), by running
run bootcmd_rescue
in U-Boot's
In DFU v1.1 specification [1] the DFU_UPLOAD (Short Frame)
is handled only in dfuUPLOADIDLE state:
- Figure A.1 Interface state transition diagram
- the state description in chapter A.2
A.2.3 State 2 dfuIDLE
on Receipt of the DFU_UPLOAD request,and bitCanUpload = 1
the Next State is
Update U-Boot's version of scripts/get_maintainer.pl to sync it up with the
latest changes to the Linux kernel's version of the same script.
The last sync was with Linux kernel version v4.16. The commits to the kernel's
get_maintainer.pl since then (starting with the most recent) are:
From: litchipi
Fix mmc_rpmb_route_frames() implementation to comply with most MMC
drivers that expect some alignment of MMC data frames in memory.
When called from drivers/tee/optee/rpmb.c, the address passed is not
aligned properly. OP-TEE OS inserts a 6-byte header before a raw RPMB
frame
On Tue, Jun 15, 2021 at 09:56:10AM +0300, Ilias Apalodimas wrote:
> > > >
>
> [...]
>
> > > > They are fixing "different" problems relating ESRT generation.
> > > > That is my point.
> > > >
> > >
> > > Sure, but it's a minor clean up really. As I said the current code works
> > > fine. So I
> > >
[...]
> > > They are fixing "different" problems relating ESRT generation.
> > > That is my point.
> > >
> >
> > Sure, but it's a minor clean up really. As I said the current code works
> > fine. So I dont really mind the fact that it breaks a sentence of the spec.
> > Hence I
On Tue, Jun 15, 2021 at 09:22:31AM +0300, Ilias Apalodimas wrote:
> On Tue, Jun 15, 2021 at 02:55:38PM +0900, AKASHI Takahiro wrote:
> > On Tue, Jun 15, 2021 at 08:23:35AM +0300, Ilias Apalodimas wrote:
> > > On Tue, Jun 15, 2021 at 01:44:58PM +0900, AKASHI Takahiro wrote:
> > > > On Tue, Jun 15,
If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled,
wherever original env is placed anywhere, it should be relocated to
the right address.
Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in
setup_reloc() and env address gd->env_addr is relocated by the offset in
On Tue, Jun 15, 2021 at 02:55:38PM +0900, AKASHI Takahiro wrote:
> On Tue, Jun 15, 2021 at 08:23:35AM +0300, Ilias Apalodimas wrote:
> > On Tue, Jun 15, 2021 at 01:44:58PM +0900, AKASHI Takahiro wrote:
> > > On Tue, Jun 15, 2021 at 06:55:50AM +0300, Ilias Apalodimas wrote:
> > > > Akashi-san,
> >
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