Enable OSPI related configs to boot using OSPI
Signed-off-by: Manorit Chawdhry
---
configs/j721s2_evm_a72_defconfig | 3 +++
configs/j721s2_evm_r5_defconfig | 3 +++
2 files changed, 6 insertions(+)
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index
Enable ospi0 node for all boot stages
Signed-off-by: Manorit Chawdhry
---
arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
R5 being a 32-bit processor can't understand the 64-bit mapping being
done in ospi node. Override the ospi node for 32-bit register ranges and
the fss node ( the parent node of ospi ) to map the ranges for the
updated child node correctly.
Signed-off-by: Manorit Chawdhry
---
From: Pratyush Yadav
On DTR capable flashes like Micron Xcella the writes cannot start or end
at an odd address in DTR mode. Extra 0xff bytes need to be prepended or
appended respectively to make sure both the start and end addresses are
even.
Signed-off-by: Pratyush Yadav
Reviewed-by: Vignesh
The series enables ospi boot for j721s2.
Test logs: https://gist.github.com/manorit2001/6bb91885c608e3a8cb0267ab2c614781
Signed-off-by: Manorit Chawdhry
---
Manorit Chawdhry (3):
arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode
arch: arm: dts:
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> Enable support for the DWC3 USB controller and required dependencies for
> Qualcomm boards, specifically the DB845c:
> * IOMMU / SMMU
> * USB high-speed PHYs
> * Mass storage and ACM gadgets
>
> Signed-off-by: Caleb Connolly
> ---
>
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> Qualcomm FDTs are on the larger size, and with the addition of DT
> modifications during board_init() it makes sense to enable OF_LIVE
> globally. The cost of building the tree should be offset by the
> increased efficiency at which we can
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
> This is incorrectly modelled in Linux where only the PCIe dependency is
> expressed. The correct way to handle this will be through a
> usb-connector node, but for
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> Make sure we power on any boot-on or always-on regulators. These are
> used for peripherals like USB on some platforms.
>
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/board.c | 2 ++
> 1 file changed, 2 insertions(+)
>
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> We don't support the RPM(h)PD power domains in U-Boot, and we don't need
> to - the necessary resources are on, and we aren't going to enter any
> low power modes.
>
> We could try using a no-op device, but this requires adding a compatible
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> We don't support USB super-speed in U-Boot yet, we lack the SS PHY
> drivers, however from my testing even with a PHY driver there seem to be
> other issues when talking to super-speed peripherals.
>
> In pursuit of maintaining upstream DT
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> From: Bhupesh Sharma
>
> Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
> driver, notable the SM8250 SoC which will gain U-Boot support in
> upcoming patches.
>
> Introduce a driver based on the Linux driver.
>
>
On Thu, 28 Mar 2024 at 23:29, Caleb Connolly wrote:
>
> From: Bhupesh Sharma
>
> The Snapdragon 845 and several other Qualcomm SoCs feature this
> USB high-speed phy. Add a driver for it based on the Linux driver, with
> support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
>
There are situations where we may want to let U-Boot modify the FDT
nand partitions for the kernel, such as when supporting multiple
sizes of NAND chips.
Signed-off-by: James Hilliard
---
Changes v1 -> v2:
- move partition fixups to board/xilinx/common/board.c
---
board/xilinx/common/board.c
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
No changes in v2
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2 +-
Hi Ye Li,
On Sun, Mar 31, 2024 at 10:33 PM Ye Li wrote:
>
> Since the event callback imx9_probe_mu is re-defined, update
> its prototype.
>
> Signed-off-by: Ye Li
> ---
> Changes in v2:
> Fix imx93_var_som and phycore_imx93 as well
Thanks for the fix, but please submit it as part of a series
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2 +-
On 2024-04-01 01:41, Jonas Karlman wrote:
On 2024-04-01 01:30, Dragan Simic wrote:
On 2024-04-01 01:14, Jonas Karlman wrote:
On 2024-04-01 00:53, Dragan Simic wrote:
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux
On 2024-04-01 01:30, Dragan Simic wrote:
> On 2024-04-01 01:14, Jonas Karlman wrote:
>> On 2024-04-01 00:53, Dragan Simic wrote:
>>> Please see my comments below.
>>>
>>> On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI
On 2024-04-01 01:14, Jonas Karlman wrote:
On 2024-04-01 00:53, Dragan Simic wrote:
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y,
Hi Dragan,
On 2024-04-01 00:53, Dragan Simic wrote:
> Hello Jonas,
>
> Please see my comments below.
>
> On 2024-03-31 22:28, Jonas Karlman wrote:
>> Sync rk3399-rock-pi-4 related device tree from linux v6.8.
>>
>> Add SPI flash related options to support booting from SPI flash.
>>
>> Add
Hello Jonas,
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA
boot.
As we
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-pinephone-pro device tree from linux v6.8.
Add SPI flash related node and options to support booting from SPI
flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-pinebook-pro device tree from linux v6.8.
Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rockpro64 device tree from linux v6.8.
Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media
Signed-off-by: Eugene Uriev
---
common/mcheck_core.inc.h | 16
include/mcheck.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index 2f11ac567f..6902140992 100644
---
My tests have been run on an U-Boot (of older version)
for ARM (64bits).
Signed-off-by: Eugene Uriev
---
common/mcheck_core.inc.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h
index
The using of pre-reloc/malloc_simple heap is
too hard to follow after the relocation.
So lets drop it from the pedantic registry
and switch to dlmalloc, when moved.
The offset is ignored, but kept in the API
for the probable case, when that early
heap is relocated too.
Signed-off-by: Eugene
The pedantic mode is run-time contolled, so
appropriate registry take place everytime.
Maybe it's worth to use compile-time control only.
So, the registry could be optimized out by an #ifdef.
Signed-off-by: Eugene Uriev
---
common/dlmalloc.c| 12
common/mcheck_core.inc.h
Signed-off-by: Eugene Uriev
---
common/dlmalloc.c| 7 ++-
common/mcheck_core.inc.h | 20 ++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 8de15d7193..73c04af2a3 100644
--- a/common/dlmalloc.c
+++
The core part of mcheck, but without memalign.
memalign - to be added in ensuing commits.
Signed-off-by: Eugene Uriev
---
common/mcheck_core.inc.h | 220 +++
include/mcheck.h | 42
2 files changed, 262 insertions(+)
create mode 100644
This changes are probable worth to be generalized in a
separate .h-file so, making it able to cover
libc-mallocs and others, without too much copy-paste.
But the malloc<=>mALLOc substitutions interfere
with an elegant way to do this.
Signed-off-by: Eugene Uriev
---
common/dlmalloc.c | 67
Signed-off-by: Eugene Uriev
---
The file contradicts U-Boot code style a lot; so I preserve
original style, according to recommendations.
common/dlmalloc.c | 66 +--
1 file changed, 41 insertions(+), 25 deletions(-)
diff --git a/common/dlmalloc.c
These fast helpers sometimes breach mem-chunk boundaries.
Thus they trigger mcheck alarm. Standard ones are accurate though.
Signed-off-by: Eugene Uriev
---
common/dlmalloc.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index
There was no "mcheck" for U-Boot before.
Since U-Boot has only 1 thread, and normally makes 4000+ - 6000+
mallocs, it's better to use havier canaries to protect heap-chunks.
My variant uses 2x8 = 16byte-long protector. And
the multiplier could be changed to tune speed/protection tradeoff.
This
Sync rk3399-pinebook-pro device tree from linux v6.8.
Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using
the pwr button on the board.
Remove SPL_TINY_MEMSET=y to use
Sync rk3399-pinephone-pro device tree from linux v6.8.
Add SPI flash related node and options to support booting from SPI flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for serial console.
Remove SPL_TINY_MEMSET=y to use
Sync rk3399-rockpro64 device tree from linux v6.8.
Add SF_DEFAULT_SPEED=1000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB
after faster boot media has been evaluated.
Add CMD_POWEROFF=y to
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure
Sync rk3399-khadas related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe
Sync rk3399-rock960 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256
Sync rk3399-nanopi-4 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Add ROCKCHIP_IODOMAIN=y to configure io-domain
Sync rk3399-roc-pc related device tree from linux v6.8.
Add SF_DEFAULT_SPEED=3000 and SPI_FLASH_SFDP_SUPPORT=y to improve
support for booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add
Sync rk3399-orangepi device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to
Sync rk3399-firefly device tree from linux v6.8.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add
Sync rk3399-evb device tree from linux v6.8.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on
cpuid read from eFUSE.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use
Sync rk3399-leez-p710 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y
Sync rk3399-eaidk-610 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y
Sync rk3399-rock-pi-n10 related device tree from linux v6.8.
Remove SPL_GPIO=y, board does not use gpio in SPL.
Change to SPL_MAX_SIZE=0x4, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add
Sync rk3399-puma related device tree from linux v6.8.
SPL_MAX_SIZE is not adjusted to the now common 0x4 (256 KiB) due to
TPL+SPL combined (idbloader.img) is limited to max 224 KiB because of:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 instead of
Sync rk3399-gru related device tree from linux v6.8.
The spi_flash symbol is no longer part of upstream DT, it is re-defined
to allow exising use in related u-boot.dtsi-files.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3399-gru-bob.dts | 8 +-
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 -
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will
be restored in board specific .dts-files. There is no other intended
change with this patch.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3399-op1-opp.dtsi
The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix
reference clock period configuration.
Also replace use of 2400 with the OSC_HZ constant.
Signed-off-by: Jonas Karlman
---
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the
SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF already handles
setting correct parent once the clock gets enabled. And 100 MHz is the
default rate used for this clock.
Add dummy support for
rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to
400 MHz using an assigned-clock-rates prop of the CRU node.
U-Boot does not use or need this clock so add dummy support for getting
and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an
updated rk3399.dtsi.
Sync rk3399-cru.h with one from linux v6.2+ and fix use of the
SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3399-u-boot.dtsi| 2 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +-
include/dt-bindings/clock/rk3399-cru.h | 30
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl",
and
Move this to rk3399-u-boot.dtsi and make this default for boards
currently missing a u-boot,spl-boot-order prop.
The _flash reference has been dropped from spl-boot-order now that
boot source id is cached and
Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay
support on all RK3399 boards.
Signed-off-by: Jonas Karlman
---
arch/arm/mach-rockchip/Kconfig| 1 +
configs/rock-4c-plus-rk3399_defconfig | 1 -
configs/rock-4se-rk3399_defconfig | 1 -
The TPL and/or SPL control FDT on RK3399 boards does not contain any
node with a compatible that is supported by driver/misc/ drivers.
Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused
efuse driver in TPL and/or SPL.
Signed-off-by: Jonas Karlman
---
The RK3399 SoC contain a crypto engine block that can generate random
numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the
random generator on all RK3399 boards.
Signed-off-by: Jonas Karlman
---
arch/arm/mach-rockchip/Kconfig | 2 ++
Imply support for GbE PHY status parsing and configuration when support
for onboard ethernet is enabled.
Signed-off-by: Jonas Karlman
---
arch/arm/mach-rockchip/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8
crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto
extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and
Sort imply statements under ROCKCHIP_RK3399 alphabetically.
Signed-off-by: Jonas Karlman
---
arch/arm/mach-rockchip/Kconfig | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index
The rk3399-ficus board is only using SPL and not TPL+SPL like all other
RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any
technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow
for more options to be
Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399
boards, this mean that SPL is loaded to and run from SRAM instead of
DRAM. The SPL and U-Boot payload is loaded from SPI flash.
The U-Boot payload is located at 0x4 (256 KiB) offset in SPI flash
and because the BROM only
This series adds support for new clocks used in linux v6.8 device trees,
enables use of FIT signature check for checksum validation and fixes
loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use
OF_UPSTREAM in a future
In case the system has resumed successfully, the PSCI suspend resume
code has to jump to the 'ep' successful resume entry point code path,
otherwise the code has to jump to content of the LR register, which
points to failed resume code path.
To implement this distinction, rewrite LR register
On Sat, Mar 30, 2024 at 04:40:31PM -0300, Fabio Estevam wrote:
> Hi Tom,
>
> Please pull this material for next from u-boot-imx, thanks.
>
> The following changes since commit 6e2228fb052b68c84688d5baff06e2ebc787a4a5:
>
> Merge patch series "Clean up arm linker scripts" (2024-03-29 10:39:38
70 matches
Mail list logo
