There are can be situations when the registers cannot be emulated to its full
functionality. This can be due to the complexity involved. In such cases, we can
emulate those registers as RAZ/WI.
A suitable example of this is DBGDTRTX_EL0 (on Arm64) and DBGDTRTXINT(on Arm32).
As this register is not optional, guests may try to access this. Currently, this
would result in a crash. With this patch, Xen will emulated this as RAZ/WI and
the crash will be avoided.
Such partial emulations will be enclosed within CONFIG_PARTIAL_EMULATION.
Also "CONFIG_PARTIAL_EMULATION" is default to y, so that Xen does not need to be
rebuilt in order to prevent guest from crashing while accessing registers like
DBGDTRTX_EL0.
Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com>
---
Changes from v1:-
1. New patch introduced in v2.
xen/arch/arm/Kconfig | 8 ++++++++
xen/arch/arm/arm64/vsysreg.c | 3 +++
xen/arch/arm/vcpreg.c | 2 ++
3 files changed, 13 insertions(+)
diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 50e9bfae1a..8f25d9cba0 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -225,6 +225,14 @@ config STATIC_EVTCHN
This option enables establishing static event channel communication
between domains on a dom0less system (domU-domU as well as domU-dom0).
+config PARTIAL_EMULATION
+ bool "Enable partial emulation for registers"
+ default y
+ help
+ This option enabled partial emulation for registers to avoid guests
+ crashing when accessing registers which are not optional but has not been
+ emulated to its complete functionality.
+
endmenu
menu "ARM errata workaround via the alternative framework"
diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index ebeb83dd65..0fa8716884 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -188,10 +188,13 @@ void do_sysreg(struct cpu_user_regs *regs,
return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 0,
1U << 29);
}
+#ifdef CONFIG_PARTIAL_EMULATION
case HSR_SYSREG_DBGDTR_EL0:
/* DBGDTR[TR]X_EL0 share the same encoding */
case HSR_SYSREG_DBGDTRTX_EL0:
return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0);
+#endif
+
HSR_SYSREG_DBG_CASES(DBGBVR):
HSR_SYSREG_DBG_CASES(DBGBCR):
HSR_SYSREG_DBG_CASES(DBGWVR):
diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c
index 5087125111..52a8732423 100644
--- a/xen/arch/arm/vcpreg.c
+++ b/xen/arch/arm/vcpreg.c
@@ -575,6 +575,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr
hsr)
case HSR_CPREG32(DBGOSLSR):
return handle_ro_read_val(regs, regidx, cp32.read, hsr, 1, 1 << 3);
+#ifdef CONFIG_PARTIAL_EMULATION
case HSR_CPREG32(DBGDTRTXINT):
{
/*
@@ -584,6 +585,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union hsr
hsr)
*/
return handle_raz_wi(regs, regidx, cp32.read, hsr, 0);
}
+#endif
case HSR_CPREG32(DBGVCR):
case HSR_CPREG32(DBGBVR0):
--
2.25.1
