Hi Oleksii,
On 05/02/2024 15:32, Oleksii Kurochko wrote:
Signed-off-by: Oleksii Kurochko
---
Changes in V4:
- update the comment above p2m_type_t. RISC-V has only 2 free for use bits in
PTE, not 4 as Arm.
- update the comment after p2m_ram_rw: s/guest/domain/ as this also applies
for
On Mon, 2024-02-12 at 16:16 +0100, Jan Beulich wrote:
> On 05.02.2024 16:32, Oleksii Kurochko wrote:
> > Signed-off-by: Oleksii Kurochko
>
> Acked-by: Jan Beulich
> with two more nits:
>
> > --- /dev/null
> > +++ b/xen/arch/riscv/include/asm/p2m.h
> > @@ -0,0 +1,102 @@
> > +/*
On 05.02.2024 16:32, Oleksii Kurochko wrote:
> Signed-off-by: Oleksii Kurochko
Acked-by: Jan Beulich
with two more nits:
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/p2m.h
> @@ -0,0 +1,102 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef __ASM_RISCV_P2M_H__
> +#define
Signed-off-by: Oleksii Kurochko
---
Changes in V4:
- update the comment above p2m_type_t. RISC-V has only 2 free for use bits in
PTE, not 4 as Arm.
- update the comment after p2m_ram_rw: s/guest/domain/ as this also applies
for dom0.
- return INVALID_MFN in gfn_to_mfn() instead of mfn(0).
-
