Re: [yocto] How to modify a meta third party layer sources from my custom layer

2018-05-16 Thread Anuj Mittal 
On 05/14/2018 04:58 AM, Stefano Cappa wrote:
> Hello everyone, 
> I'm new to yocto so please don't kill me :). I have a question, probably
> very stupid and simple, but I'm really don't know how to understand this
> so I'm trying to ask to the cummunity.
> 
> I'm using Yocto 2.4 for an hardware with meta-freescale layer to support it.
> However I have to apply some changes. I'm able to build if I
> modify/overwrite and delete some files by myself, but when I try to use
> a custom layer to do that I cannot build, because obviously I don't know
> what I should do.
> 
> My custom layer applies some patches to work and work-shared dirs and
> everything is ok, but I don't understand how to add files and changes to
> my layer to modify meta-freescale sources.
> 
> I can create a fork of that layer, but I prefer to add all changes to my
> layer.
> In particular I need to add some .inc, .bb files into
> /recipes-bsp/u-boot/ of meta-freescale and a folder with some files and
> patches taken from poky/meta//u-boot/
> like u-boot-fw-utils-imx_2017.09.bb
>  and u-boot-common_2017.09.inc
> 
> How can I do this from a custom layer? Which is the right procedure?
> 
> Custom layers can modify only work and work-shared dirs content or also
> other layer sources, because that they are executed?
> 

Please take a look at:
https://www.yoctoproject.org/docs/latest/mega-manual/mega-manual.html#prioritizing-your-layer

and the sections around it, and see if that answers your question.
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Re: [yocto] apt-get error

2018-05-16 Thread Anuj Mittal 
On 05/16/2018 06:31 PM, Rahul jangra wrote:
> Hi
> i am facing the so many issues to creating .deb base yocto raspberry pi
> image now i am getting this error.
> someone can help me how to resolve this error.
> 
> ERROR: core-image-full-cmdline-1.0-r0 do_rootfs: Unable to install
> packages. Command
> '/home/nsspl/rpi/build/tmp/work/raspberrypi3-poky-linux-gnueabi/core-image-f
> ull-cmdline/1.0-r0/recipe-sysroot-native/usr/bin/apt-get install
> --force-yes --allow-unauthenticated mender psplash-raspberrypi shadow
> run-postinsts hello-mender packagegroup-core-boot kernel-devicetree
> packagegroup-core-ssh-openssh apt dpkg base-passwd kernel-image-4.14.37

It'd help if you can share more details - layers that you are using,
which version, local configuration and the complete error.

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Re: [yocto] Enabling the recipe from menuconfig

2018-05-16 Thread chandrasekhar 
Hi 

You can use 

IMAGE_INSTALL += "Package Name/Recipes name"

 

Regards,

Chandrasekhar

 

From: yocto-boun...@yoctoproject.org [mailto:yocto-boun...@yoctoproject.org] On 
Behalf Of Ugesh Reddy
Sent: Wednesday, May 16, 2018 9:57 PM
To: Yocto-mailing-list
Subject: [yocto] Enabling the recipe from menuconfig

 

Hello Team,

 

 I have a list of recipes in my custom layer. The recipes in this layer shall 
be enabled/selected through the menuconfig, once it is enabled then it shall be 
the part of image. is it possible to achieve it ? do we have any references? 

 

Regards,

Ugesh

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Re: [yocto] How to create img file from a working machine

2018-05-16 Thread Scott Rifenbark 
Yes - that is a good place to look.  The topic is from the Yocto Project
Development Tasks Manual (
https://www.yoctoproject.org/docs/2.5/dev-manual/dev-manual.html#creating-partitioned-images-using-wic
).

Scott

On Wed, May 16, 2018 at 6:27 AM, Alan Martinovic 
wrote:

> Hey,
> perhaps this will help you:
> https://www.yoctoproject.org/docs/2.4/mega-manual/mega-
> manual.html#creating-partitioned-images-using-wic
>
> On Wed, May 16, 2018 at 8:49 AM, Denis  wrote:
> >
> >
> > Hi. This is my first experience with Yocto.
> >
> > After having create a working machine this is the machine file list
> >
> >
> >
> > bzImage
> > bzImage--4.14.30+git0+ea9330894e_74f6cd2b69-r0-
> qemux86-20180515055407.bin
> > bzImage-qemux86.bin
> > core-image-minimal-qemux86-20180515055407.testdata.json
> > core-image-minimal-qemux86-20180515141056.qemuboot.conf
> > core-image-minimal-qemux86-20180515141056.rootfs.ext4
> > core-image-minimal-qemux86-20180515141056.rootfs.manifest
> > core-image-minimal-qemux86-20180515141056.rootfs.tar.bz2
> > core-image-minimal-qemux86-20180515141056.testdata.json
> > core-image-minimal-qemux86.ext4
> > core-image-minimal-qemux86.manifest
> > core-image-minimal-qemux86.qemuboot.conf
> > core-image-minimal-qemux86.tar.bz2
> > core-image-minimal-qemux86.testdata.json
> > core-image-sato-qemux86-20180515175948.qemuboot.conf
> > core-image-sato-qemux86-20180515175948.rootfs.ext4
> > core-image-sato-qemux86-20180515175948.rootfs.manifest
> > core-image-sato-qemux86-20180515175948.rootfs.tar.bz2
> > core-image-sato-qemux86-20180515175948.testdata.json
> > core-image-sato-qemux86.ext4
> > core-image-sato-qemux86.manifest
> > core-image-sato-qemux86.qemuboot.conf
> > core-image-sato-qemux86.tar.bz2
> > core-image-sato-qemux86.testdata.json
> > modules--4.14.30+git0+ea9330894e_74f6cd2b69-r0-
> qemux86-20180515055407.tgz
> > modules-qemux86.tgz
> >
> >
> >
> > Now how can I create a img file? I have searched on the web but I have
> found
> > nothing.
> >
> >
> >
> > Regards.
> >
> >
> >
> >
> > --
> >
> > +39.347.4070897
> >
> > www.labcsp.com
> >
> > www.denisgottardello.it
> >
> > GMT+1
> >
> > Skype: mrdebug
> >
> >
> > --
> > ___
> > yocto mailing list
> > yocto@yoctoproject.org
> > https://lists.yoctoproject.org/listinfo/yocto
> >
> --
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Re: [yocto] How to create img file from a working machine

2018-05-16 Thread Alan Martinovic 
Hey,
perhaps this will help you:
https://www.yoctoproject.org/docs/2.4/mega-manual/mega-manual.html#creating-partitioned-images-using-wic

On Wed, May 16, 2018 at 8:49 AM, Denis  wrote:
>
>
> Hi. This is my first experience with Yocto.
>
> After having create a working machine this is the machine file list
>
>
>
> bzImage
> bzImage--4.14.30+git0+ea9330894e_74f6cd2b69-r0-qemux86-20180515055407.bin
> bzImage-qemux86.bin
> core-image-minimal-qemux86-20180515055407.testdata.json
> core-image-minimal-qemux86-20180515141056.qemuboot.conf
> core-image-minimal-qemux86-20180515141056.rootfs.ext4
> core-image-minimal-qemux86-20180515141056.rootfs.manifest
> core-image-minimal-qemux86-20180515141056.rootfs.tar.bz2
> core-image-minimal-qemux86-20180515141056.testdata.json
> core-image-minimal-qemux86.ext4
> core-image-minimal-qemux86.manifest
> core-image-minimal-qemux86.qemuboot.conf
> core-image-minimal-qemux86.tar.bz2
> core-image-minimal-qemux86.testdata.json
> core-image-sato-qemux86-20180515175948.qemuboot.conf
> core-image-sato-qemux86-20180515175948.rootfs.ext4
> core-image-sato-qemux86-20180515175948.rootfs.manifest
> core-image-sato-qemux86-20180515175948.rootfs.tar.bz2
> core-image-sato-qemux86-20180515175948.testdata.json
> core-image-sato-qemux86.ext4
> core-image-sato-qemux86.manifest
> core-image-sato-qemux86.qemuboot.conf
> core-image-sato-qemux86.tar.bz2
> core-image-sato-qemux86.testdata.json
> modules--4.14.30+git0+ea9330894e_74f6cd2b69-r0-qemux86-20180515055407.tgz
> modules-qemux86.tgz
>
>
>
> Now how can I create a img file? I have searched on the web but I have found
> nothing.
>
>
>
> Regards.
>
>
>
>
> --
>
> +39.347.4070897
>
> www.labcsp.com
>
> www.denisgottardello.it
>
> GMT+1
>
> Skype: mrdebug
>
>
> --
> ___
> yocto mailing list
> yocto@yoctoproject.org
> https://lists.yoctoproject.org/listinfo/yocto
>
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[yocto] apt-get error

2018-05-16 Thread Rahul jangra 
Hi
i am facing the so many issues to creating .deb base yocto raspberry pi
image now i am getting this error.
someone can help me how to resolve this error.

ERROR: core-image-full-cmdline-1.0-r0 do_rootfs: Unable to install
packages. Command
'/home/nsspl/rpi/build/tmp/work/raspberrypi3-poky-linux-gnueabi/core-image-f
ull-cmdline/1.0-r0/recipe-sysroot-native/usr/bin/apt-get install
--force-yes --allow-unauthenticated mender psplash-raspberrypi shadow
run-postinsts hello-mender packagegroup-core-boot kernel-devicetree
packagegroup-core-ssh-openssh apt dpkg base-passwd kernel-image-4.14.37


Best Regards
rahul
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Re: [yocto] -c populate_sdk question

2018-05-16 Thread ChenQi 

On 05/16/2018 03:12 AM, Steve Pavao wrote:

Hello,

Is there an easy way to exclude a section of my local conf when I am building 
with -c populate_sdk option?

Long story short, I have some multilib-related entries in my local.conf which I 
need when building only the OS image, but which cause errors when building the 
SDK.

It’s be easiest if I could put a conditional around the multilib-related 
entries in my local.conf.  Then when I build with the -c populate_sdk option, 
they would be excluded from that build.

I noticed there are many SDK* variables in the Bitbake system, but I’m not so 
sure what are the best one/ones to use for my purpose, and what is the 
recommended syntax to achieve this conditional exclusion in my local.conf.

Thanks in advance for any ideas.

- Steve Pavao
Korg R



I don't think there's some easy and automatic way to do so.
Why not just comment the lines out?

FYI, the SDK and the target image should match, and our SDK is supposed 
to support multilib.


Best Regards,
Chen Qi
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Re: [yocto] Set root password from a recipe

2018-05-16 Thread ChenQi 
Such setting should be in global conf files like .conf or 
local.conf.

Setting root password from a recipe does not have effect.

If you really want to set a root password from recipe, maybe you need to 
take a look at base-passwd recipe.


'-P' is an option added to support clear text password. The patch only 
applies to shadow-native.

So it does not affect the shadow on target.

Best Regards,
Chen Qi

On 05/16/2018 04:46 PM, Mauro Ziliani wrote:

Hi all.

I need to set a well know password for root user.

I follow the istruction to do this with


inherit extra_users

EXTRA_USERS_PARAMS = " \

usermod -P secret root; \

"


But it does not work.

I think the problem i for usermod

I sse the man page and the -p parameter needs the output of crypt(3) 
function.


While -P parameter (p-uppercase) is not a valid parameter for usermod


Any idea?


Thanks

   Mauro



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[linux-yocto] [PATCH 11/14] FogBugz #554835-3: Intel RSU binding documentation

2018-05-16 Thread Meng.Li 
From: David Koltak 

commit 800553eb887b2477bed3693e931c6aadf484eefb from
https://github.com/altera-opensource/linux-socfpga.git

Documentation showing the proper device tree node
and binding for the Intel Remote System Update (RSU)
driver for Stratix 10 SoC FPGAs.

Signed-off-by: David Koltak 
Signed-off-by: Meng Li 
---
 .../bindings/firmware/intel,stratix10-rsu.txt  | 28 ++
 1 file changed, 28 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt

diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt 
b/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt
new file mode 100644
index 000..9df6f89
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt
@@ -0,0 +1,28 @@
+Intel Remote System Update (RSU) for Stratix10 SoC FPGAs
+
+The Intel Remote System Update (RSU) driver exposes interfaces
+accessed through the Intel Service Layer to user space via SysFS
+device attribute nodes. The RSU interfaces report/control some of
+the optional RSU features of the Stratix 10 SoC FPGA.
+
+The RSU feature provides a way for customers to update the boot
+configuration of a Stratix 10 SoC device with significantly reduced
+risk of corrupting the bitstream storage and bricking the system.
+
+Required properties:
+---
+The intel-rsu node has the following mandatory properties and must be located
+under the firmware/svc node.
+
+- compatible: "intel,stratix10-rsu"
+
+Example:
+---
+
+   firmware {
+   svc {
+   rsu {
+   compatible = "intel,stratix10-rsu";
+   };
+   };
+   };
-- 
2.7.4

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[linux-yocto] [PATCH 14/14] intel-socfpga: dts: improve qspi node for rsu feature

2018-05-16 Thread Meng.Li 
From: Limeng 

There are 2 modification in qspi node for rsu feature as below:
- The QSPI read delay must be changed from the default of 3 to 1
   in order to make sure it works on Stratix10 platform.
- The MTD partition used by LIBRSU must start at the beginning
   of SPT0(sub-partition table 0) in flash

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 533b4cb..f6da74a 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -155,7 +155,7 @@
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
-   cdns,read-delay = <3>;
+   cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
@@ -164,7 +164,7 @@
partition@qspi-boot {
label = "Boot and fpga data";
/* 64MB for boot and FPGA data */
-   reg = <0x0 0x400>;
+   reg = <0x0091 0x036F>;
};
 
partition@qspi-rootfs {
-- 
2.7.4

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[linux-yocto] [PATCH 13/14] intel-socfpga: dts: add rsu node to enable rsu driver

2018-05-16 Thread Meng.Li 
From: Limeng 

Add a corresponding dts node in socfpga_stratix10.dtsi to enable
rsu drvier.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 375d68a..1cdd800 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -968,6 +968,9 @@
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <_reserved>;
+   rsu {
+   compatible = "intel,stratix10-rsu";
+   };
};
};
};
-- 
2.7.4

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[linux-yocto] [PATCH 12/14] FogBugz #514234: arm64: dts: stratix10: Add PL330 DMA to Stratix10 dts

2018-05-16 Thread Meng.Li 
From: Graham Moore 

commit 8927da5c28eeb5c36f969860b3945c0adb7cdb14 from
https://github.com/altera-opensource/linux-socfpga.git

This patch is part of the bringup of the Stratix10 SoC.  It depends upon
Uboot to take the PL330 out of reset in non-secure mode.

Signed-off-by: Graham Moore 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 83f4f35..375d68a 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -752,6 +752,25 @@
reg = <0xffe0 0x10>;
};
 
+   pdma: pdma@ffda {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda 0x1000>;
+   interrupts = <0 81 4>,
+<0 82 4>,
+<0 83 4>,
+<0 84 4>,
+<0 85 4>,
+<0 86 4>,
+<0 87 4>,
+<0 88 4>,
+<0 89 4>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
-- 
2.7.4

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[linux-yocto] [PATCH 08/14] FogBugz #549288-3: edac: Add support for Stratix10 SDRAM EDAC

2018-05-16 Thread Meng.Li 
From: Thor Thayer 

commit a2884ad40e8120fe44c268f48b162e4fcff68feb from
https://github.com/altera-opensource/linux-socfpga.git

edac: altera: Add support for Stratix10 SDRAM EDAC

Support for Stratix10 SDRAM ECC requires the use of SMC
calls to a higher priority exception level.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 drivers/edac/Kconfig   |   2 +-
 drivers/edac/altera_edac.c | 455 +++--
 drivers/edac/altera_edac.h | 126 +++--
 3 files changed, 555 insertions(+), 28 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 96afb2a..8ed7bc2 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -379,7 +379,7 @@ config EDAC_THUNDERX
 
 config EDAC_ALTERA
bool "Altera SOCFPGA ECC"
-   depends on EDAC=y && ARCH_SOCFPGA
+   depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
help
  Support for error detection and correction on the
  Altera SOCs. This must be selected for SDRAM ECC.
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 7717b094..fcd0c95 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1,20 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
+ *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
  *  Copyright 2011-2012 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see .
- *
- * Adapted from the highbank_mc_edac driver.
  */
 
 #include 
@@ -81,6 +69,25 @@ static const struct altr_sdram_prv_data a10_data = {
.ue_set_mask= A10_DIAGINT_TDERRA_MASK,
 };
 
+static const struct altr_sdram_prv_data s10_data = {
+   .ecc_ctrl_offset= S10_ECCCTRL1_OFST,
+   .ecc_ctl_en_mask= A10_ECCCTRL1_ECC_EN,
+   .ecc_stat_offset= S10_INTSTAT_OFST,
+   .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
+   .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
+   .ecc_saddr_offset   = S10_SERRADDR_OFST,
+   .ecc_daddr_offset   = S10_DERRADDR_OFST,
+   .ecc_irq_en_offset  = S10_ERRINTEN_OFST,
+   .ecc_irq_en_mask= A10_ECC_IRQ_EN_MASK,
+   .ecc_irq_clr_offset = S10_INTSTAT_OFST,
+   .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
+   .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
+   .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
+   .ce_ue_trgr_offset  = S10_DIAGINTTEST_OFST,
+   .ce_set_mask= A10_DIAGINT_TSERRA_MASK,
+   .ue_set_mask= A10_DIAGINT_TDERRA_MASK,
+};
+
 /*** EDAC Memory Controller Functions /
 
 /* The SDRAM controller uses the EDAC Memory Controller framework.   */
@@ -240,6 +247,7 @@ static unsigned long get_total_mem(void)
 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
{ .compatible = "altr,sdram-edac", .data = _data},
{ .compatible = "altr,sdram-edac-a10", .data = _data},
+   { .compatible = "altr,sdram-edac-s10", .data = _data},
{},
 };
 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
@@ -487,6 +495,285 @@ static int altr_sdram_remove(struct platform_device *pdev)
return 0;
 }
 
+/ Stratix 10 EDAC Memory Controller Functions /
+
+/**
+ * s10_protected_reg_write
+ * Write to a protected SMC register.
+ * @context: Not used.
+ * @reg: Address of register
+ * @value: Value to write
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ *INTEL_SIP_SMC_REG_ERROR on error
+ *INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_write(void *context, unsigned int reg,
+  unsigned int val)
+{
+   struct arm_smccc_res result;
+
+   arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
+ 0, 0, 0, );
+
+   return (int)result.a0;
+}
+
+/**
+ * s10_protected_reg_read
+ * Read the status of a protected SMC register
+ * @context: Not used.
+ * @reg: Address of register
+ * @value: Value read.
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ *INTEL_SIP_SMC_REG_ERROR on error
+ *INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_read(void *context, unsigned int reg,
+ unsigned int *val)

[linux-yocto] [PATCH 10/14] FogBugz #554835-1: Add Stratix 10 SoC RSU Driver

2018-05-16 Thread Meng.Li 
From: David Koltak 

commit 000af215119d8a7ccb469d49535a59a5dbb12ad7 from
https://github.com/altera-opensource/linux-socfpga.git

Add a kernel driver to expose interfaces required to
support the Remote System Update (RSU) feature of Stratix
10 SoC FPGAs.  The driver uses SysFS device attribute nodes.
The accesses are performed through the intel-service layer.

Signed-off-by: David Koltak 
Signed-off-by: Meng Li 
---
 drivers/misc/Kconfig |  17 ++
 drivers/misc/Makefile|   1 +
 drivers/misc/intel-rsu.c | 377 +++
 drivers/misc/intel-service.c |  51 -
 drivers/misc/intel-smc.h |  41 
 include/linux/intel-service-client.h |  15 +-
 6 files changed, 498 insertions(+), 4 deletions(-)
 create mode 100644 drivers/misc/intel-rsu.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 5a48b8a..02f3359 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -151,6 +151,23 @@ config INTEL_SERVICE
 
  Say Y here if you want Intel service layer support.
 
+config INTEL_RSU
+   tristate "Intel Remote System Update"
+   depends on INTEL_SERVICE
+   help
+ The Intel Remote System Update (RSU) driver exposes interfaces
+ accessed through the Intel Service Layer to user space via SysFS
+ device attribute nodes. The RSU interfaces report/control some of
+ the optional RSU features of the Stratix 10 SoC FPGA.
+
+ The RSU feature provides a way for customers to update the boot
+ configuration of a Stratix 10 SoC device with significantly reduced
+ risk of corrupting the bitstream storage and bricking the system.
+
+ Enable RSU support if you are using an Intel SoC FPGA with the RSU
+ feature enabled and you want Linux user space control.
+
+ Say Y here if you want Intel RSU support.
 
 config SGI_IOC4
tristate "SGI IOC4 Base IO support"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0cbc82f..837d9f0 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_AD525X_DPOT_I2C)   += ad525x_dpot-i2c.o
 obj-$(CONFIG_AD525X_DPOT_SPI)  += ad525x_dpot-spi.o
 obj-$(CONFIG_INTEL_MID_PTI)+= pti.o
 obj-$(CONFIG_INTEL_SERVICE) += intel-service.o
+obj-$(CONFIG_INTEL_RSU)+= intel-rsu.o
 obj-$(CONFIG_ATMEL_SSC)+= atmel-ssc.o
 obj-$(CONFIG_ATMEL_TCLIB)  += atmel_tclib.o
 obj-$(CONFIG_DUMMY_IRQ)+= dummy-irq.o
diff --git a/drivers/misc/intel-rsu.c b/drivers/misc/intel-rsu.c
new file mode 100644
index 000..4dc834b
--- /dev/null
+++ b/drivers/misc/intel-rsu.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Intel Corporation
+ */
+
+/*
+ * This driver exposes some optional features of the Intel Stratix 10 SoC FPGA.
+ * The SysFS interfaces exposed here are FPGA Remote System Update (RSU)
+ * related.  They allow user space software to query the configuration system
+ * status and to request optional reboot behavior specific to Intel FPGAs.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_U64_STR_LEN 22
+
+/*
+ * Private data structure
+ */
+struct intel_rsu_priv {
+   struct intel_svc_chan *chan;
+   struct intel_svc_client client;
+   struct completion svc_completion;
+   struct {
+   unsigned long current_image;
+   unsigned long fail_image;
+   unsigned int version;
+   unsigned int state;
+   unsigned int error_details;
+   unsigned int error_location;
+   } status;
+};
+
+/*
+ * status_svc_callback() - Callback from intel-service layer that returns SMC
+ * response with RSU status data. Parses up data and
+ * update driver private data structure.
+ * client - returned context from intel-service layer
+ * data - SMC response data
+ */
+static void status_svc_callback(struct intel_svc_client *client,
+   struct intel_svc_c_data *data)
+{
+   struct intel_rsu_priv *priv = client->priv;
+   struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1;
+
+   if (data->status == BIT(SVC_STATUS_RSU_OK)) {
+   priv->status.version =
+   (unsigned int)(res->a2 >> 32) & 0x;
+   priv->status.state = (unsigned int)res->a2 & 0x;
+   priv->status.fail_image = res->a1;
+   priv->status.current_image = res->a0;
+   priv->status.error_location =
+   (unsigned int)res->a3 & 0x;
+   priv->status.error_details =
+   (unsigned int)(res->a3 >> 32) & 0x;
+   } else {
+   dev_err(client->dev,

[linux-yocto] [PATCH 09/14] FogBugz #549288-4: dts: add Stratix10 sdram ecc

2018-05-16 Thread Meng.Li 
From: Thor Thayer 

commit aa9b366a54171468663f221ae46baa6e34c35288 from
https://github.com/altera-opensource/linux-socfpga.git

arm64: dts: stratix10: add sdram ecc

Add the Stratix10 ECC Manager and SDRAM EDAC nodes to the
device tree.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index dc0a4a6..83f4f35 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -913,6 +913,21 @@
status = "disabled";
};
 
+   eccmgr: eccmgr {
+   compatible = "altr,socfpga-s10-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupts = <0 15 4>, <0 95 4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ranges;
+
+   sdramedac {
+   compatible = "altr,sdram-edac-s10";
+   interrupts = <16 4>, <48 4>;
+   };
+   };
+
qspi: spi@ff8d2000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
-- 
2.7.4

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[linux-yocto] [PATCH 05/14] mtd: spi-nor: cadence-quadspi: Fix page fault kernel panic

2018-05-16 Thread Meng.Li 
From: Thor Thayer 

commit c1de85b2b1dd9dcad21a2514fca327d74d03b571 from
https://github.com/altera-opensource/linux-socfpga.git

[backport 'commit 47016b341fc3 ("mtd: spi-nor: cadence-quadspi:
 Fix page fault kernel panic")']

Backported from spi-nor-next/master

The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4 bytes at a time.

[7.947754] spi_nor_read[1048]:from 0x037cad74, len 1 [bfe07fff]
[7.956247] cqspi_read[910]:offset 0x58502516, buffer=bfe07fff
[7.956247]
[7.966046] Unable to handle kernel paging request at virtual
address bfe08002
[7.973239] pgd = eebfc000
[7.975931] [bfe08002] *pgd=2fffb811, *pte=, *ppte=

Notice above how only 1 byte needed to be read but by reading 4 bytes
into the end of a mapped page, an unrecoverable page fault occurred.

This patch uses a temporary buffer to hold the 4 bytes read and then
copies only the bytes required into the buffer. A min() function is
used to limit the length to prevent buffer overflows.

Request testing of this patch on other platforms. This was tested
on the Intel Arria10 SoCFPGA DevKit.

Fixes: 0cf1725676a97fc8 ("mtd: spi-nor: cqspi: Fix build on arches missing 
readsl/writesl")
Signed-off-by: Thor Thayer 
Cc: 
Reviewed-by: Marek Vasut 
Signed-off-by: Boris Brezillon 
Signed-off-by: Meng Li 
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 9f8102d..0404898 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -495,7 +495,9 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
void __iomem *reg_base = cqspi->iobase;
void __iomem *ahb_base = cqspi->ahb_base;
unsigned int remaining = n_rx;
+   unsigned int mod_bytes = n_rx % 4;
unsigned int bytes_to_read = 0;
+   u8 *rxbuf_end = rxbuf + n_rx;
int ret = 0;
 
writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
@@ -523,11 +525,24 @@ static int cqspi_indirect_read_execute(struct spi_nor 
*nor,
}
 
while (bytes_to_read != 0) {
+   unsigned int word_remain = round_down(remaining, 4);
+
bytes_to_read *= cqspi->fifo_width;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
-   ioread32_rep(ahb_base, rxbuf,
-DIV_ROUND_UP(bytes_to_read, 4));
+   bytes_to_read = round_down(bytes_to_read, 4);
+   /* Read 4 byte word chunks then single bytes */
+   if (bytes_to_read) {
+   ioread32_rep(ahb_base, rxbuf,
+(bytes_to_read / 4));
+   } else if (!word_remain && mod_bytes) {
+   unsigned int temp = ioread32(ahb_base);
+
+   bytes_to_read = mod_bytes;
+   memcpy(rxbuf, , min((unsigned int)
+(rxbuf_end - rxbuf),
+bytes_to_read));
+   }
rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
-- 
2.7.4

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[linux-yocto] [PATCH 06/14] FogBugz #549288-1: misc: Stratix10 Protected register access defines

2018-05-16 Thread Meng.Li 
From: Thor Thayer 

commit da941c6dc017d0eebf0d7c72d9a84231c5447c61 from
https://github.com/altera-opensource/linux-socfpga.git

Add the defines for the Stratix10 Protected register
accesses. This syncs with the U-Boot version of this
file.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 drivers/misc/intel-smc.h | 64 
 1 file changed, 64 insertions(+)

diff --git a/drivers/misc/intel-smc.h b/drivers/misc/intel-smc.h
index 0b92560..d92dcd7 100644
--- a/drivers/misc/intel-smc.h
+++ b/drivers/misc/intel-smc.h
@@ -66,12 +66,17 @@
  *
  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
  * There is error during the FPGA configuration process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
  */
 #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION  0x
 #define INTEL_SIP_SMC_STATUS_OK0x0
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY  0x1
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED   0x2
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_REG_ERROR0x5
 
 /*
  * Request INTEL_SIP_SMC_FPGA_CONFIG_START
@@ -202,4 +207,63 @@ 
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
 
+/*
+ * Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/*
+ * Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
+ *
+ * Update one or more bits in a protected register using a
+ * read-modify-write operation.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_UPDATE.
+ * a1: register address
+ * a2: Write Mask.
+ * a3: Value to write.
+ * a4-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: Not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
+#define INTEL_SIP_SMC_REG_UPDATE \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+
 #endif
-- 
2.7.4

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[linux-yocto] [PATCH 07/14] FogBugz #549288-2: Add Stratix10 ECC Manager binding

2018-05-16 Thread Meng.Li 
From: Thor Thayer 

commit 97a3b7365253bc7757b2c885a23e4bd57be9d25b from
https://github.com/altera-opensource/linux-socfpga.git

Documentation: dt: socfpga: Add Stratix10 ECC Manager binding

Add the device tree bindings needed to support the Stratix10
ECC Manager and SDRAM ECC.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 .../bindings/arm/altera/socfpga-eccmgr.txt | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 4a1714f..fe582f6 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -231,3 +231,45 @@ Example:
 <48 IRQ_TYPE_LEVEL_HIGH>;
};
};
+
+Stratix10 SoCFPGA ECC Manager
+The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
+in a shared register similar to the Arria10. However, ECC requires
+access to registers that can only be read from Secure Monitor with
+SMC calls.
+Therefore the device tree is slightly different.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-s10-ecc-manager"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt 
controller
+- #interrupt-cells : must be set to 2.
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+SDRAM ECC
+Required Properties:
+- compatible : Should be "altr,sdram-edac-s10"
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt, in this order.
+
+Example:
+
+   eccmgr: eccmgr {
+   compatible = "altr,socfpga-s10-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupts = <0 15 4>, <0 95 4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ranges;
+
+   sdramedac {
+   compatible = "altr,sdram-edac-s10";
+   interrupts = <16 4>, <48 4>;
+   };
+   };
-- 
2.7.4

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[linux-yocto] [PATCH 02/14] FogBugz #251539-2: dts: Add Altera Quad SPI Driver Device Tree Binding

2018-05-16 Thread Meng.Li 
From: VIET NGA DAO 

commit 990acaf14261901a67c96f2effab389556d87c60 from
https://github.com/altera-opensource/linux-socfpga.git

This patch adds Device Tree Binding for Altera Quad SPI Driver.

Signed-off-by: Viet Nga Dao 
Signed-off-by: Ooi, Joyce 
Signed-off-by: Meng Li 
---
 .../devicetree/bindings/mtd/altera_quadspi.txt | 42 ++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt

diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt 
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..626b602
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,42 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be "altr,quadspi-1.0"
+- reg: Address and length of the register set  for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  "avl_csr": Should contain the register configuration base address
+  "avl_mem": Should contain the data base address
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>.
+- flash device tree subnode, there must be a node with the following fields:
+   - compatible: Should contain the flash name
+   - #address-cells: please refer to /mtd/partition.txt
+   - #size-cells: please refer to /mtd/partition.txt
+   For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+   quadspi_controller_0: quadspi@0x180014a0 {
+   compatible = "altr,quadspi-1.0";
+   reg = <0x180014a0 0x0020>,
+ <0x1400 0x0400>;
+   reg-names = "avl_csr", "avl_mem";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   flash0: epcq256@0 {
+   compatible = "epcq256-nonjedec";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   partition@0 {
+   /* 16 MB for raw data. */
+   label = "EPCQ Flash 0 raw data";
+   reg = <0x0 0x100>;
+   };
+   partition@100 {
+   /* 16 MB for jffs2 data. */
+   label = "EPCQ Flash 0 JFFS 2";
+   reg = <0x100 0x100>;
+   };
+   };
+   }; //end quadspi@0x180014a0 (quadspi_controller_0)
-- 
2.7.4

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[linux-yocto] [PATCH 03/14] arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver

2018-05-16 Thread Meng.Li 
From: "Ooi, Joyce" 

commit bf0c54db1dff12fbef7aedf7538a741e78328fc7 from
https://github.com/altera-opensource/linux-socfpga.git

The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay.

Signed-off-by: Ooi, Joyce 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index ec18609..533b4cb 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -92,7 +92,7 @@
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
-   txc-skew-ps = <1860>; /* 960ps */
+   txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
max-frame-size = <3800>;
-- 
2.7.4

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[linux-yocto] [PATCH 01/14] FogBugz #251539-1: Add Altera Quad SPI Driver

2018-05-16 Thread Meng.Li 
From: VIET NGA DAO 

commit 09dc2f10a87141935cfef75a8adbbe4a3928465f from
https://github.com/altera-opensource/linux-socfpga.git

This patch adds linux driver for Altera Quad SPI controller.
Quad SPI controller is a soft IP designed to access EPCS, EPCQ
and Micron flash chips.

Signed-off-by: Viet Nga Dao 
Signed-off-by: Ooi, Joyce 
Signed-off-by: Meng Li 
---
 drivers/mtd/devices/Kconfig  |   7 +
 drivers/mtd/devices/Makefile |   2 +-
 drivers/mtd/devices/altera_quadspi.c | 667 +++
 3 files changed, 675 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/devices/altera_quadspi.c

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 58329d2..a0c0968 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -221,4 +221,11 @@ config BCH_CONST_T
default 4
 endif
 
+config MTD_ALTERA_QUADSPI
+   tristate "Altera Quad SPI Flash Driver"
+   help
+ This enables access to Altera EPCQ/EPCS/Micron flash chips,
+ used for data storage. See the driver source for the current list,
+ or to add other chips.
+
 endmenu
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index 7912d3a..b09511d 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -17,6 +17,6 @@ obj-$(CONFIG_MTD_SST25L)  += sst25l.o
 obj-$(CONFIG_MTD_BCM47XXSFLASH)+= bcm47xxsflash.o
 obj-$(CONFIG_MTD_ST_SPI_FSM)+= st_spi_fsm.o
 obj-$(CONFIG_MTD_POWERNV_FLASH)+= powernv_flash.o
-
+obj-$(CONFIG_MTD_ALTERA_QUADSPI) += altera_quadspi.o
 
 CFLAGS_docg3.o += -I$(src)
diff --git a/drivers/mtd/devices/altera_quadspi.c 
b/drivers/mtd/devices/altera_quadspi.c
new file mode 100644
index 000..3990b7d
--- /dev/null
+++ b/drivers/mtd/devices/altera_quadspi.c
@@ -0,0 +1,667 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ALTERA_QUADSPI_RESOURCE_NAME   "altera_quadspi"
+
+/* max possible slots for serial flash chip in the QUADSPI controller */
+#define MAX_NUM_FLASH_CHIP 3
+#define EPCS   1
+#define NON_EPCS   2
+
+#define WRITE_CHECK1
+#define ERASE_CHECK0
+
+#define NOR_OP_RDID0x9F
+#define NOR_OP_RDSR0x05
+
+/* Define max times to check status register before we give up. */
+#define QUADSPI_MAX_TIME_OUT_USEC  4
+
+/* defines for status register */
+#define QUADSPI_SR_REG 0x0
+#define QUADSPI_SR_WIP_MASK0x0001
+#define QUADSPI_SR_WIP 0x1
+#define QUADSPI_SR_WEL 0x2
+#define QUADSPI_SR_BP0 0x4
+#define QUADSPI_SR_BP1 0x8
+#define QUADSPI_SR_BP2 0x10
+#define QUADSPI_SR_BP3 0x40
+#define QUADSPI_SR_TB  0x20
+#define QUADSPI_SR_MASK0x000F
+
+/* defines for device id register */
+#define QUADSPI_SID_REG0x4
+#define QUADSPI_RDID_REG   0x8
+#define QUADSPI_ID_MASK0x00FF
+
+/*
+ * QUADSPI_MEM_OP register offset
+ *
+ * The QUADSPI_MEM_OP register is used to do memory protect and erase 
operations
+ *
+ */
+#define QUADSPI_MEM_OP_REG 0xC
+
+#define QUADSPI_MEM_OP_CMD_MASK0x0003
+#define QUADSPI_MEM_OP_BULK_ERASE_CMD  0x0001
+#define QUADSPI_MEM_OP_SECTOR_ERASE_CMD0x0002
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_CMD  0x0003
+#define QUADSPI_MEM_OP_SECTOR_VALUE_MASK   0x0003FF00
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_VALUE_MASK   0x1F00
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_SHIFT8
+/*
+ * QUADSPI_ISR register offset
+ *
+ * The QUADSPI_ISR register is used to determine whether an invalid write or
+ * erase operation trigerred an interrupt
+ *
+ */
+#define QUADSPI_ISR_REG0x10
+
+#define QUADSPI_ISR_ILLEGAL_ERASE_MASK 0x0001
+#define QUADSPI_ISR_ILLEGAL_WRITE_MASK 0x0002
+
+/*
+ * QUADSPI_IMR register offset
+ *
+ * The QUADSPI_IMR register is used to mask the invalid erase or the invalid
+ * write interrupts.
+ *
+ */
+#define QUADSPI_IMR_REG

[linux-yocto] [PATCH 04/14] FogBugz #554812: fpga: stratix10: unitialized data

2018-05-16 Thread Meng.Li 
From: Alan Tull 

commit e85199e8db5bc5c8880f95b5e8fec05d52ddd5d0 from
https://github.com/altera-opensource/linux-socfpga.git

Address the following issue caught by static code analysis:

drivers/fpga/stratix10-soc.c:206 --  -- UNINIT.STACK.MUST
(1:Critical) Analyze 'payload.flags' is used uninitialized
in this function.

Signed-off-by: Alan Tull 
Signed-off-by: Meng Li 
---
 drivers/fpga/stratix10-soc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
index 9648387..2974c8e 100644
--- a/drivers/fpga/stratix10-soc.c
+++ b/drivers/fpga/stratix10-soc.c
@@ -201,6 +201,7 @@ static int s10_ops_write_init(struct fpga_manager *mgr,
uint i;
int ret;
 
+   payload.flags = 0;
if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
dev_info(dev, "Requesting partial reconfiguration.\n");
payload.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
-- 
2.7.4

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[linux-yocto] : [yocto-4.12]: intel-socfpga: get latest patches from sdk for remote system feature

2018-05-16 Thread Meng.Li 
From: Limeng 


Hi Bruce,

Now, there are some update for intel-socfpga, Stratix10 SoC from SDK.
These patches are used to implement remote system update feature.

Please help to meger below patches into linux-yocto, kernel 4.12, branch is 
standard/base
 
0001-FogBugz-251539-1-Add-Altera-Quad-SPI-Driver.patch
0002-FogBugz-251539-2-dts-Add-Altera-Quad-SPI-Driver-Devi.patch
0003-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch
0004-FogBugz-554812-fpga-stratix10-unitialized-data.patch
0005-mtd-spi-nor-cadence-quadspi-Fix-page-fault-kernel-pa.patch
0006-FogBugz-549288-1-misc-Stratix10-Protected-register-a.patch
0007-FogBugz-549288-2-Add-Stratix10-ECC-Manager-binding.patch
0008-FogBugz-549288-3-edac-Add-support-for-Stratix10-SDRA.patch
0009-FogBugz-549288-4-dts-add-Stratix10-sdram-ecc.patch
0010-FogBugz-554835-1-Add-Stratix-10-SoC-RSU-Driver.patch
0011-FogBugz-554835-3-Intel-RSU-binding-documentation.patch
0012-FogBugz-514234-arm64-dts-stratix10-Add-PL330-DMA-to-.patch
0013-intel-socfpga-dts-add-rsu-node-to-enable-rsu-driver.patch
0014-intel-socfpga-dts-improve-qspi-node-for-rsu-feature.patch

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt|   42 
Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt |   28 
Documentation/devicetree/bindings/mtd/altera_quadspi.txt   |   42 
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  |   37 
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts |6 
drivers/edac/Kconfig   |2 
drivers/edac/altera_edac.c |  455 ++
drivers/edac/altera_edac.h |  126 +
drivers/fpga/stratix10-soc.c   |1 
drivers/misc/Kconfig   |   17 
drivers/misc/Makefile  |1 
drivers/misc/intel-rsu.c   |  377 +
drivers/misc/intel-service.c   |   51 
drivers/misc/intel-smc.h   |  105 +
drivers/mtd/devices/Kconfig|7 
drivers/mtd/devices/Makefile   |2 
drivers/mtd/devices/altera_quadspi.c   |  667 
++
drivers/mtd/spi-nor/cadence-quadspi.c  |   19 
include/linux/intel-service-client.h   |   15 
19 files changed, 1962 insertions(+), 38 deletions(-)


thanks,
Limeng


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Re: [yocto] Set root password from a recipe

2018-05-16 Thread Mauro Ziliani 

Sorry

inherit extrausers


Il 16/05/2018 10:46, Mauro Ziliani ha scritto:

Hi all.

I need to set a well know password for root user.

I follow the istruction to do this with


inherit extra_users

EXTRA_USERS_PARAMS = " \

    usermod -P secret root; \

"


But it does not work.

I think the problem i for usermod

I sse the man page and the -p parameter needs the output of crypt(3) 
function.


While -P parameter (p-uppercase) is not a valid parameter for usermod


Any idea?


Thanks

   Mauro



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[yocto] Set root password from a recipe

2018-05-16 Thread Mauro Ziliani 

Hi all.

I need to set a well know password for root user.

I follow the istruction to do this with


inherit extra_users

EXTRA_USERS_PARAMS = " \

    usermod -P secret root; \

"


But it does not work.

I think the problem i for usermod

I sse the man page and the -p parameter needs the output of crypt(3) 
function.


While -P parameter (p-uppercase) is not a valid parameter for usermod


Any idea?


Thanks

   Mauro

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Re: [yocto] LIC_FILES_CHKSUM: spaces in file names

2018-05-16 Thread Damien LEFEVRE 
Thanks Mark it works.

-Damien

On Tue, May 15, 2018, 17:29 Mark Hatle  wrote:

> On 5/15/18 7:25 AM, Damien LEFEVRE wrote:
> > Hi,
> >
> > I have a base recipe generated with devtool.
> >
> > The package I build has several license files which contain space
> characters in
> > the file names.
> >
> > LIC_FILES_CHKSUM =
> "file://COPYRIGHT.md;md5=b229ca0c79785e9e86311477e7bdd9ea \
> >  file://LICENSES/MIT
> > License.txt;md5=3ba96e7848c3cedc5df2d00094a0d0f3 \
> >  file://LICENSES/FreeImage Public
> > License.txt;md5=ffcd65468a2d2b3e3e43fbaf63ceedf7 \
> >  file://LICENSES/Boost Software
> > License.txt;md5=2c7a3fa82e66676005cd4ee2608fd7d2 \
> >  file://LICENSES/zlib-libpng
> > License.txt;md5=09b00738058950409d6955872d715416 \
> >  file://LICENSES/OpenSIFT
> > License.txt;md5=7a69fc0ac94076df51f7db9b0c02fe7c \
> >  file://LICENSES/ISSL
> > License.txt;md5=1ba0d78ed416760e4a8ef3dc121e69c8"
> >
> > Bitbake fails and seem to break at the first space character
> > LIC_FILES_CHKSUM contains an invalid URL:
> > License.txt;md5=3ba96e7848c3cedc5df2d00094a0d0f3
> >
> > How can I deal with this? Any other options than renaming the files?
> >
> > I tried surrounding with quotes, "\ "using, nothing helps.
>
> I've not tried it, but since these are URIs, did you try %20?
>
> --Mark
>
> > Thanks,
> > -Damien
> >
> >
>
>
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[yocto] How to create img file from a working machine

2018-05-16 Thread Denis 
Hi. This is my first experience with Yocto.
After having create a working machine this is the machine file list

*bzImage* 
*bzImage-qemux86.bin* 
*core-image-minimal-qemux86-20180515141056.rootfs.tar.bz2* 
*core-image-minimal-qemux86.ext4* 
*core-image-minimal-qemux86.manifest* 
*core-image-minimal-qemux86.qemuboot.conf* 
*core-image-minimal-qemux86.tar.bz2* 
*core-image-minimal-qemux86.testdata.json* 
*core-image-sato-qemux86-20180515175948.rootfs.tar.bz2* 
*core-image-sato-qemux86.ext4* 
*core-image-sato-qemux86.manifest* 
*core-image-sato-qemux86.qemuboot.conf* 
*core-image-sato-qemux86.tar.bz2* 
*core-image-sato-qemux86.testdata.json* 
*modules--4.14.30+git0+ea9330894e_74f6cd2b69-r0-qemux86-20180515055407.tgz* 
*modules-qemux86.tgz*


Now how can I create a img file? I have searched on the web but I have found 
nothing.

Regards.



+39.347.4070897
www.labcsp.com[1] 
www.denisgottardello.it[2] 
GMT+1
Skype: mrdebug


[1] http://www.labcsp.com
[2] http://www.denisgottardello.it
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