On 15.02.2024 17:46, Roger Pau Monne wrote: > The feature is defined in the tertiary exec control, and is available starting > from Sapphire Rapids and Alder Lake CPUs. > > When enabled, two extra VMCS fields are used: SPEC_CTRL mask and shadow. Bits > set in mask are not allowed to be toggled by the guest (either set or clear) > and the value in the shadow field is the value the guest expects to be in the > SPEC_CTRL register. > > By using it the hypervisor can force the value of SPEC_CTRL bits behind the > guest back without having to trap all accesses to SPEC_CTRL, note that no bits > are forced into the guest as part of this patch. It also allows getting rid > of > SPEC_CTRL in the guest MSR load list, since the value in the shadow field will > be loaded by the hardware on vmentry. > > Signed-off-by: Roger Pau Monné <roger....@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
