On 2024-03-05 02:43, Stefano Stabellini wrote:
On Mon, 4 Mar 2024, Nicola Vetrini wrote:
Hi,
as the maintainers of this subsystem, would you prefer Jan's version
or the
one in the patch?
Both are fine w.r.t MISRA Rule 20.7 because the macro arguments
themselves are
parenthesized.
I prefer Jan's version. Thanks for asking Nicola.
Ok, thanks. I'll modify it and keep an eye for possibly additional
opinions of other maintainers.
> > > --- a/xen/arch/arm/include/asm/vgic-emul.h
> > > +++ b/xen/arch/arm/include/asm/vgic-emul.h
> > > @@ -6,11 +6,11 @@
> > > * a range of registers
> > > */
> > >
> > > -#define VREG32(reg) reg ... reg + 3
> > > -#define VREG64(reg) reg ... reg + 7
> > > +#define VREG32(reg) (reg) ... (reg) + 3
> > > +#define VREG64(reg) (reg) ... (reg) + 7
> >
> > #define VREG32(reg) (reg) ... ((reg) + 3)
> > #define VREG64(reg) (reg) ... ((reg) + 7)
> >
> > ?
> >
>
> The outer parentheses are not required, but I can add them if the
> maintainers share your view.
--
Nicola Vetrini, BSc
Software Engineer, BUGSENG srl (https://bugseng.com)
