Hi Ayan,
On 07/03/2024 12:39, Ayan Kumar Halder wrote:
When user enables HVC_DCC config option in Linux, it invokes access to debug
transfer register (i.e. DBGDTRTXINT). As this register is not emulated, Xen
injects an undefined exception to the guest and Linux crashes.
To prevent this crash, introduce a partial emulation of DBGDTR[TR]XINT (these
registers share the same encoding) as RAZ/WI and DBGDSCRINT as TXfull.
Refer ARM DDI 0487J.a ID042523, G8.3.19, DBGDTRTXint:
"If TXfull is set to 1, set DTRTX to UNKNOWN".
As a pre-requisite, DBGOSLSR should be emulated in the same way as its AArch64
variant (i.e. OSLSR_EL1). This is to ensure that DBGOSLSR.OSLK is 0, which
allows us to skip the emulation of DBGDSCREXT (TXfull is treated as UNK/SBZP)
and focus on DBGDSCRINT. DBGOSLSR.OSLM[1] is set to 1 to mantain consistency
with Arm64.
Take the opportunity to fix the minimum EL for DBGDSCRINT, which should be 0.
NIT: Strictly speaking Arm32 is using PL (Priviledge) rather than EL
(Exception Level) to describe each level :).
Anyway,
Signed-off-by: Ayan Kumar Halder <ayan.kumar.hal...@amd.com>
Signed-off-by: Michal Orzel <michal.or...@amd.com>
Acked-by: Julien Grall <jgr...@amazon.com>
Cheers,
--
Julien Grall
