These will replace svm_feature_flags and the SVM_FEATURE_* constants over the
next few changes. Take the opportunity to rationalise some names.
Drop the opencoded "inherit from host" logic in calculate_hvm_max_policy() and
use 'h'/'!' annotations. The logic needs to operate on fs, not the policy
object, given its position within the function.
Drop some trailing whitespace introduced when this block of code was last
moved.
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Roger Pau Monné <roger....@citrix.com>
CC: Stefano Stabellini <sstabell...@kernel.org>
CC: Xenia Ragiadakou <xenia.ragiada...@amd.com>
CC: Sergiy Kibrik <sergiy_kib...@epam.com>
CC: George Dunlap <george.dun...@citrix.com>
CC: Andrei Semenov <andrei.seme...@vates.fr>
CC: Vaishali Thakkar <vaishali.thak...@vates.tech>
---
tools/misc/xen-cpuid.c | 11 +++++++++++
xen/arch/x86/cpu-policy.c | 17 +++++------------
xen/include/public/arch-x86/cpufeatureset.h | 14 ++++++++++++++
xen/tools/gen-cpuid.py | 3 +++
4 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index ab09410a05d6..0d01b0e797f1 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -266,6 +266,17 @@ static const char *const str_m10Ah[32] =
static const char *const str_eAd[32] =
{
+ [ 0] = "npt", [ 1] = "v-lbr",
+ [ 2] = "svm-lock", [ 3] = "nrips",
+ [ 4] = "v-tsc-rate", [ 5] = "vmcb-cleanbits",
+ [ 6] = "flush-by-asid", [ 7] = "decode-assist",
+
+ [10] = "pause-filter",
+ [12] = "pause-thresh",
+ /* 14 */ [15] = "v-loadsave",
+ [16] = "v-gif",
+ /* 18 */ [19] = "npt-sss",
+ [20] = "v-spec-ctrl",
};
static const char *const str_e1Fa[32] =
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 4b6d96276399..da4401047e89 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -9,7 +9,6 @@
#include <asm/amd.h>
#include <asm/cpu-policy.h>
#include <asm/hvm/nestedhvm.h>
-#include <asm/hvm/svm/svm.h>
#include <asm/intel-family.h>
#include <asm/msr-index.h>
#include <asm/paging.h>
@@ -748,22 +747,16 @@ static void __init calculate_hvm_max_policy(void)
if ( !cpu_has_vmx )
__clear_bit(X86_FEATURE_PKS, fs);
- /*
+ /*
* Make adjustments to possible (nested) virtualization features exposed
* to the guest
*/
- if ( p->extd.svm )
+ if ( test_bit(X86_FEATURE_SVM, fs) )
{
- /* Clamp to implemented features which require hardware support. */
- p->extd.raw[0xa].d &= ((1u << SVM_FEATURE_NPT) |
- (1u << SVM_FEATURE_LBRV) |
- (1u << SVM_FEATURE_NRIPS) |
- (1u << SVM_FEATURE_PAUSEFILTER) |
- (1u << SVM_FEATURE_DECODEASSISTS));
- /* Enable features which are always emulated. */
- p->extd.raw[0xa].d |= (1u << SVM_FEATURE_VMCBCLEAN);
+ /* Xen always emulates cleanbits. */
+ __set_bit(X86_FEATURE_VMCB_CLEANBITS, fs);
}
-
+
guest_common_max_feature_adjustments(fs);
guest_common_feature_adjustments(fs);
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 0f869214811e..80d252a38c2d 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -358,6 +358,20 @@ XEN_CPUFEATURE(RFDS_CLEAR, 16*32+28) /*!A Register
File(s) cleared by VE
/* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 */
/* AMD-defined CPU features, CPUID level 0x8000000a.edx, word 18 */
+XEN_CPUFEATURE(NPT, 18*32+ 0) /*h Nested PageTables */
+XEN_CPUFEATURE(V_LBR, 18*32+ 1) /*h Virtualised LBR */
+XEN_CPUFEATURE(SVM_LOCK, 18*32+ 2) /* SVM locking MSR */
+XEN_CPUFEATURE(NRIPS, 18*32+ 3) /*h Next-RIP saved on VMExit */
+XEN_CPUFEATURE(V_TSC_RATE, 18*32+ 4) /* Virtualised TSC Ratio */
+XEN_CPUFEATURE(VMCB_CLEANBITS, 18*32+ 5) /*! VMCB Clean-bits */
+XEN_CPUFEATURE(FLUSH_BY_ASID, 18*32+ 6) /* TLB Flush by ASID */
+XEN_CPUFEATURE(DECODE_ASSIST, 18*32+ 7) /*h Decode assists */
+XEN_CPUFEATURE(PAUSE_FILTER, 18*32+10) /*h Pause filter */
+XEN_CPUFEATURE(PAUSE_THRESH, 18*32+12) /* Pause filter threshold */
+XEN_CPUFEATURE(V_LOADSAVE, 18*32+15) /* Virtualised VMLOAD/SAVE */
+XEN_CPUFEATURE(V_GIF, 18*32+16) /* Virtualised GIF */
+XEN_CPUFEATURE(NPT_SSS, 18*32+19) /* NPT Supervisor Shadow Stacks
*/
+XEN_CPUFEATURE(V_SPEC_CTRL, 18*32+20) /* Virtualised MSR_SPEC_CTRL */
/* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 19 */
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index bf3f9ec01e6e..f07b1f4cf905 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -280,6 +280,9 @@ def crunch_numbers(state):
# standard 3DNow in the earlier K6 processors.
_3DNOW: [_3DNOWEXT],
+ # The SVM bit enumerates the whole SVM leave.
+ SVM: list(range(NPT, NPT + 32)),
+
# This is just the dependency between AVX512 and AVX2 of XSTATE
# feature flags. If want to use AVX512, AVX2 must be supported and
# enabled. Certain later extensions, acting on 256-bit vectors of
--
2.30.2
