[PATCH 01/12] drm/amdgpu: Write masked value to control register

[Maíra Canal]

On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable
should be written into the control register instead of 0.

Fixes: b00861b9 ("drm/amd/amdgpu: port of DCE v6 to new headers (v3)")
Fixes: 2285b91c ("drm/amdgpu/dce8: simplify hpd code")
Signed-off-by: Maíra Canal <mairaca...@riseup.net>
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index f5a29526684d..0a7b1c002822 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -339,7 +339,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 
                tmp = RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
                tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-               WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+               WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
                amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
        }
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 780a8aa972fe..f57f4a25cf5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -333,7 +333,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 
                tmp = RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
                tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-               WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+               WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
                amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
        }
-- 
2.36.1